DE3226929C2 - - Google Patents

Abstract

Some at least of the control signals usually produced by manual control members and applied to the control circuit of the watch to control the performance of the different functions thereof are produced directly from words pronounced by the user, belonging to a pre-determined vocabulary, by an assembly for producing control signals by means of speech, which comprises electro-acoustic means for converting a pronounced word into an analog signal representing that word, means for transforming the analog signal into an item of logic control information and means for transforming the logic information into a control signal which can be directly applied to a control circuit for controlling performance of the function corresponding to the word pronounced.

Description

The invention relates to a voice-controlled device with the preamble of the claim 1 specified characteristics. Such a device is out of the DE-OS 20 20 753 known. In this known device Schrägensig nal of the filtered analog signals compared to a threshold value to assign the respective digital value.

It is also known from DE-OS 23 26 517, in a voice-controlled or the speech recognition device known, the filtered analog To sample signals and to compare the scanning patterns with thresholds. Furthermore, there are memory circuits for words in coded form of the vocabulary as references, each reference being a command to perform at least certain functions. The ko The digitized digital signal is compared with at least some of the references and the reference most similar to the coded digital signal is selected, and which is that, the user will be informed.

Object of the present invention is in a generic device the required storage volume and the cost of the evaluation to decrease. For this purpose, in the characterizing part of patent claim 1 provided for. Namely, when the sampling patterns around the Threshold around, become first (or second) digital values that isolated between second (or first) digital values appear as "wrong" treated and processed as if they had the value of their neighbors.

Such a reduction in storage volume, processing overhead and also Energy consumption is particularly desirable when the sprachge controlled device is a small device, so about a battery-powered clock. By way of example, the invention will be described below with reference to FIG to the enclosed drawings.  

Fig. 1 shows a simplified block diagram of the entirety of the clock, in particular the means for input and identification of a coded word are set is;

Fig. 2 shows the microprocessor assembly for coding and storage of the word spoken by the user;

Figures 2a to 2c show logic circuits associated with the actual microprocessor;

Fig. 3 is a coding table for the microinstructions of the program of the microprocessor;

Fig. 4 shows in simplified form the algorithm for the program of the microprocessor;

Fig. 5 shows in detail the algorithm of the subroutine WORD contained in Fig. 4;

Figures 5a and 5b diagrammatically show time phases of the processing of the spoken word in accordance with particular instructions of the subroutine of Figure 5;

Fig. 6 shows the algorithm of the subroutine NORM of Fig. 4;

Figs. 6a and 6b show the execution of the subroutine CORR of Fig. 4;

Fig. 7 shows the algorithm of the subroutine BEST of Fig. 4;

Fig. 8 shows a first embodiment of the logic control circuit of the clock;

Fig. 9 shows a first embodiment of the control circuit of the clock; the figure is drawn in two parts 9a and 9b;

Fig. 10 shows two tables representing the correspondence between the numerical value of the control signals and the information contained in these signals;

Fig. 11 shows a sequence of operation of the timepiece according to the invention;

Fig. 12 shows a second embodiment of the control circuit of the clock;

Fig. 13 shows a third embodiment of the control circuit of the clock;

Fig. 14a shows a fourth embodiment of the control circuit of the watch;

FIG. 14b shows an indication of the clock commands according to the fourth embodiment and FIG

Fig. 14c shows a coding table of the command signals for deriving the display of Fig. 14b.

The following explanation refers to the Case that the voice-controlled device an electronic O'clock is. However, one skilled in the art will readily understand that the voice control system applies to other devices is, if you stick to the fact that for the Control of the device used vocabulary be limited must and must consist of given words.

As can be seen in Fig. 1, the clock according to the invention essentially comprises an assembly A for the processing of the command signals by voice and a clock circuit B, which allows the display of time and very often other functions while processing the command signals, which are generated by the assembly A. The part B of the clock comprises a time base 2 , for example a quartz oscillator, which provides a signal of frequency 32 kHz, a divider 4 of several divider stages, which supply at their outputs signals of different frequencies, a control circuit 6 , on the one hand, the pulse trains of the receives different frequencies and on the other hand, the control signals indicating means 8 supplies, which are controlled by the control circuit 6 ge and, for example, consist of six display elements. The part B further includes a speaker 10 , the z. B. can give a wake-up signal, as well as a Anzeigeein device 11 , which makes it possible to make the function of the clock in question visible.

The assembly A for the processing of the command signals can in turn be subdivided into electro-acoustic order translator C, which the acoustic signal S, pronounced by the user, transform into an analog signal S ', the re representative is for the acoustic signal S, a circuit D circle for providing the logical control information which transforms the analog signal S 'into a numerical information N representative of the acoustic signal S, and finally a switching circuit E for generating the command signals containing the numerical information N in one Implement control signal P, which can be applied directly to the control circuit 6 for controlling the functions of the clock.

The device for the electroacoustic conversion C essentially comprises a microphone 12 and a pre-amplifier 14 comprehensive transducer which provides the signal S '. The preamplifier 14 has a gain of about 100, which is sufficient for the output of a microphone. Furthermore, the pre-amplifier emphasizes the higher frequencies up to 3 kHz with a slope of 20 decibels per decade.

The processing circuit D essentially comprises a coding circuit 16 which converts the analogue signal S 'into a coded digital signal T, memory means 18 for these various digital signals, numerical information storage circuits 20 , each numerical in formation corresponding to one of the words of the vocabulary used for the Control of the clock are required, this numerical information should be referred to as references later, as well as for the storage of further data required for the operation of the circuit, and a circuit 22 for monitoring the memory 18 and 20 and for comparing a Digital signal representing the coding of a word spoken by the user with the various references stored in the memory 20 . This comparison will be explained later in its course. It should be understood that channels 24 connect the output of the coding circuit 16 to the input of the memory 18 and the comparison circuit 22 and the memories 18 and 20 with the comparison circuit 22nd Similarly, a channel 26 connects the output of the circuit 22 to the memories 18 and 20 and to the input of a logic control circuit E for generating control signals.

The circuit for generating the control signals essentially comprises a decoder 28 , which made it light, each control information N, representative of a word to assign a corresponding control signal P, for example in binary form, which can be applied directly to the control circuit 6 .

In general terms, the apparatus of Figure 1 comprises an electroacoustic transducer C; a circuit 16 for coding the analog signal generated by the converter C; Circuits 20 for storing references forming the vocabulary required for the control of the device; Circuits 22 for comparing the coded digital signal with the references and for selecting the reference closest to the coded signal; Means 8 for informing the user of the selected reference; Circuits 28 for converting the selected reference into a control or command signal; and finally actuating means for performing the functions of the device. It should be noted that the display means play a dual role. They inform the user about the selected reference and are also part of the actuating means.

Fig. 1 shows in detail a possible imple mentation of the Kodierkreises 16th This circuit comprises n 'bandpass filters 30 which simultaneously filter the analog signal S'. There are, for example, 7 filters with the reference characters 30 ₁ to 30 ₇. These filters cover the entire spectrum of frequencies contained in the usable speech information.

Each filter 30 provides at its output a ge filtered analog signal B 1 to B 7 corresponding to a portion of the signal S ', which is contained in each of the pass band. The outputs of the filter 30 are each connected to the A inputs of 7 sampling circuits 32 ₁ to 32 ₇. These circuits 32 provide at their output a mean value of the analog signal S 'associated with them during the period of the sampling which is, for example, 10 milliseconds. The circuits 32 supply at their output analog signal sampling U₁ to U₇ corresponding to the respective filtered analog signals B₁ to B₇. The signals U₁ to U₇ are in threshold circuits 34 ₁ to 34 ₇ entered. At their outputs is a logic signal of level 1, when the applied signal at one input is higher than the threshold, and a logic signal of level 0 in the opposite case. This threshold may be fixed or, preferably, a function of the mean of the patterns provided by the 7 filter channels. In this case, the coding circuit 16 additionally grasps a circuit for fixing a reference level. The input of this Festlegeschalt circle is multiplexed to successively receive the sampling pattern of the signal U₁ to U₇. The circuit determines the average of these scan patterns. In addition, it adds a fixed threshold voltage V _th .

The voltage obtained in this way represents the reference voltage which is stored permanently. For example, storage and calculation of the mean value are realized by means of capacities. In this way, the output of the reference magnitude circuit provides a variable reference voltage that depends on the average of the preceding sample patterns. This reference voltage is applied to one input of the threshold circuits 34 ₁ and 34 ₇, whose other input receives the sampling pattern U₁ to U₇. Each signal U 'thus represents in binary form the changes in amplitude over time of the acoustic signal S for one of the filter bands. Looking back against the 7 signals U 'at a given sampling instant, this group of signals forms a 7-digit binary number representing the frequency spectrum of the acoustic signal at the instant in question. The totality of the 7 signals U ', corresponding to a spoken word, thus forms a coding in the form of a matrix of this word, one side of which would present the time axis re and the other side represents the numbers of the different channels for the filtering. This totality represents the spoken word in coded digital form.

It is understood that the signal T actually from a certain An number of "words" with 7 binary digits. The number of these words will be finally ge to a number of fixed sampling used to normalize the spoken words.

For example, the total number of scanning patterns is 16. It is this information which is stored in the memory 18 after any processing for reducing the number of information. It is understood that the references contained in the memory 20 are formed by numerical coded signals having the same nature as the signal T. That is, the coding process of these references is the same as that coded for the processing of the coded, words spoken by the user had been used.

The way the watch works is simply the fol lowing. The user acts on a switch 40 to place the clock in a listening position. He then pronounces the word of the vocabulary to which the function to be commanded is assigned. The acoustic signal is encoded to provide a coded digital signal which is stored in the memory 18 . The circuit 22 compares the digital signal associated with the spoken word with the entirety of the references contained in the memory 20 using a correlation algorithm applied by the circuit 22 . The circuit 22 selects the most similar to the coded word reference. The command information corresponding to the word recognized by the circuit 22 is applied to the input of the circuit 28 , which generates a signal P and applies it to the control circuit 6 . The control circuit, in response to the control signal P, displays corresponding information on the Anzeigeein direction 8 or 11 at. When the user determines that the spoken word has been correctly recognized by the clock, he enters the following word of the command sequence. If the word displayed by the clock is incorrect, the user must correct it.

Fig. 2 shows the structure of the microprocessor, which allows the conversion of the digital signals T from the output of the coding circuit 16 in the numerical signals N, which are applied to the input of the logic control circuit 28 .

The microprocessor of course includes for the references a read-only memory 20 , a random access memory 18 and the entirety of the United processing circuits, which are summarized under the reference numeral 22 , Fig. 1.

The output of the coding circuit 16 acts on an INPUT designated input register having a clock input S₂₀. The output of the input register is connected to a channel for data designated DATA BUS. This channel includes, for example, 8 parallel lines. Similarly, the input of the sales circle 28 with the signal N of an output register, labeled OUTPUT, acted upon, having a clock input S₅ and whose data input is connected to the data channel DATA BUS.

In the representation of the memory 20 one recognizes a first field designated OPCODE, which contains the instructions of the program, which the microprocessor has to carry out, a data field DATA, which contains the references in coded form for the words of the vocabulary as well as the Para meter, the be used in the program of the microprocessor, and an address field ADR. The output of the field OPCODE of the memory 20 is ver connected via parallel lines 400 with inputs of a programmable logic PLA. Other inputs of the matrix PLA receive the output signal of a counter 402 , at the clock input 402 a, the clock signal CK is present and the reset to zero bar via the input 402 . Another output 402 c of the counter 402 is connected to the input of a logic circuit 404 which generates the synchronization signals Φ₂ and ₂ and the carry signals Φ₁. The output of the die PLA is connected to the input of a decoder circuit 406 via parallel lines 408 . The decoder circuit 406 provides at its outputs s₀ to s₂₃ control signals which applied directly or indirectly to the control inputs or clock inputs of the various elements of the microprocessor who the. Each instruction of the program contained in the field OPCODE of the memory 20 and transmitted to the matrix PLA is converted into a variable sequence of micro instructions as will be explained later.

Each microinstruction from the matrix PLA, applied to the input of the decoder 406 , is converted into 24 binary logic signals which are supplied to the outputs s₀ to s₂₃ of the decoder. The conversion table between the microbe missing and the signals appearing at the outputs will be given later. The data field of the memory 20 is connected to the data channel DATA BUS via a decoupling register 410 having a control input s₁₃. The address field ADR of the memory 20 is connected to the address channel ADR BUS via a multiplexer MUX. The output of the field DATA is also connected to one of the inputs of the multiplexer MUX. This multiplexer MUX comprises a select input S₁₀ and an output control input S₁₁. In other words, the data field DATA can be brought into connection with either the data channel DATA BUS or the address channel ADR BUS.

Random memory 18 is intended to contain inter alia the spoken word information encoded by circuit 16 .

This memory 18 is connected to the data channel DATA BUS via eight parallel lines 411 . The random access memory 18 comprises a read / write input S₈ and a write select input S₉. Further, this memory includes address inputs 412 and 414 . The input 412 is connected to the address register ADRH, while the input 414 is connected to the channel ADR BUS. This latter channel is connected to the input of a second address register ADRL. The address registers ADRH and ADRL are also connected to the data channel DATA BUS. The register ADRL comprises the clock input S₂, while the register ADRH has the clock input S₁ and the output control input S₁₂.

The address input of the random access memory can accordingly receive information either from the multiplexer MUX or from the register ADRL. The input 412 is for addressing the sides of the memory 18 , while the input 414 is for addressing the instructions contained in one side of this memory.

The microprocessor further comprises an arithmetic and logic unit ALU with control inputs S₁₅, S₁₆, S₁₇ and S₁₈. The central unit ALU is assigned a buffer 416 , which is connected to the central unit ALU via parallel lines 418 . This buffer 416 is also connected to the data channel DATA BUS via parallel lines 420 . The buffer 416 comprises the clock input S₄ and the output control input S₁₉. It further includes an output 422 which controls a flip-flop 424 for storing the remainder. The flip-flop 424 further includes a clock input S₀; it supplies the residual signals C _y and _y .

The input 426 of the central unit ALU is connected via parallel lines 428 to the data channel DATA BUS. Another input 430 of the central unit ALU is connected to the output of the operand register 432 . The input 434 of this register is connected to the data channel DATA BUS. The register 432 further includes a clock input S₃ and an output control input S₂₁.

The addressing in the memory 20 is realized by two registers PCH, PCL serving as program counters and the register PCL BUS. The inputs of the counters PCH and PCL are connected to the data channel DATA BUS. The output of this counter acts on the address inputs of the memory 20 , wherein the output of the register PCL is additionally connected to the input of the register PCL BUS. The counters PCL and PCH include the clock inputs S₆ and S₇ and the zero reset inputs 440 and 442 . The register PCL BUS comprises an output control input S₂₃. Its task is to return on the data channel the contents of the register PCL, which must be incremented by the central unit ALU for each new command.

Looking at the decoding circuit 406 , it can be seen that the s₁ to s₇ the same pending at the outputs s₁ apply a logic gate 44 , which is provided with a control input 46 to which the signal ₂ is applied. This circuit has the only effect to synchronize the signals at the outputs s₁ to s₇ of the circuit 406 signals with the signal ₂. The outputs of the circuit 444 are designated s'₁ to s'₇.

The microprocessor further comprises three logic circuits for processing the control signals and these circuits are shown in Figures 2a, 2b and 2c, respectively. The circuit labeled CSL in Fig. 2a is a circuit for controlling conditional jumps, allowing the value of the remainder or carry ("CARRY") to intervene.

The circuit CSL comprises a first NAND gate 450 , the signal at its inputs _y , supplied from the rest circuit 424 , and the signal from the output s₁₄ of the coding circle 406 receives. A second NAND gate 452 em receives at its inputs the signal supplied from the output s₂₂ of the circuit 406 , and the signal C _y supplied from the residual circuit 424 . The outputs of the gates 450 and 452 act on a third NAND gate 454 , whose output from one of the two inputs of a NAND gate 456 via an inverter 458 applied. The second input of the gate 456 receives the signal from the output s'₆ of the circuit 444 . Finally, another NAND gate 460 receives at one of its inputs the signal supplied by the gate 456 and at its other input the signal φ₂ supplied by the logic synchronizing circuit 404 . The output of gate 460 is labeled S'₆.

The circuit RL of FIG. 2b is a logic circuit for the control of the random access memory 18 . This circuit comprises a NAND gate 462 which receives at its inputs the signals from the outputs s₈ and s₀ of the decode circuit 406 . The output of the gate 462 is connected to an input of a NAND gate 464 , which receives at its other input the signal from the output s₉ of the circuit 406 . The output of gate 464 is labeled S'₉. The circuit RL further comprises an inverter 466 which receives at its input the signal originating from the output s₈ of the circuit 406 , while its output is denoted S'₈.

Finally, the circuit CL is a zero reset circuit. It consists of a NAND gate 468 , whose one input is connected to the output of a circuit 470 and whose other input is connected to the output S'₆ of the circuit CSL. The circuit 470 simply has the task of providing an initiation pulse when the power source has been inserted into the timepiece. The output 472 of the gate 468 supplies the zero-reset signal CLEAR is applied to the zero reset input 402 b of the counter 402, while the signal directly supplied from the switch 470, at two zero reset inputs 440 and 442 of the program counter PCL and PCH is placed.

The outputs s₁₀ to s₂₃ are connected directly to the ent speaking control inputs S₁₀ to S₂₃ of the components of the microprocessor. Likewise, the outputs s₁ to s₅ and s₇ of the circuit 444 are connected to the corresponding control inputs S₁ to S₅ or S₇ of the components of the micro processor. Finally, the output S'₆ of the circuit CSL is connected to the control input S₆ of the register PCL and the outputs S'₈ and S'₉ of the circuit RL are connected to the inputs S₈ and S₉ of the random access memory 18 a related party.

After the structure of the microprocessor has been explained is, its logic will now be described.

Fig. 3 shows the correspondence table between the microinstructions (MINSTR) used for the programming of the microprocessor and the binary value of the signals applied to the control inputs S₀ to S₂₃ of the various elements of the microprocessor for controlling the execution of these commands. In the left part of the table you can see the binary value of each signal for the various microinstructions (MINSTR), in the central column the microinstructions in symbolic form and in the right column the number of these microinstructions.

As usual, the character "<" is used to indicate that the information on the right is inserted in the leftmost element, optionally indicating an address, if it is the memory 20 , which is accordingly designated RAM , Furthermore, the indication DATA symbolizes a data value contained in the read-only memory 18 , ADR symbolizes an address of the memory 18 , CARRY the carry or residual signal and NOT CARRY the inverted signal; A denotes the buffer 416 or the information which it contains and B the register 432 or the information contained in it.

For example, the microinstruction 00 consists of writing in the memory 20, under the address contained in the address register ADRL, the information DATA contained in the memory 20 . The instruction 01 be is that the content of the register PCL is incremented by 1 and that this value is written into the buffer A is. The command 06 is to transfer to the program counter PCL the carry of the information DATA. The command 9 is to transfer to the output register OUTPUT the information contained in the memory 20 at the address ADR.

The instruction 16 is to perform the logical operation and between the contents of the register B AND in the memory 20 at the address corresponding to the content of the address register ADRL and to transfer the result to the buffer A. The instructions 18 and 1A are identical to the instruction 16, but the logical operation AND is replaced by the operation OR or EXCLUSIF respectively. The other commands are readily understandable, starting from the previous He refineries and it is therefore not necessary to make further comments here.

These micro-commands define the base transfers of the microprocessor. The micro-commands (MINSTR) will be combined to define the more complicated operations, which represent the instructions from which the program of the microprocessor is generated.

The first command is labeled LDI A8, D8. It consists of a transfer of the value of the field DATA from the memory 20 (ROM) to the RAM at a position whose address is given by the field ADR of the ROM. Here runs a sequence of three basic transfers, namely the transfer of this data into the RAM under addressing by the field ADR; the transfer of the state of register PCL into the buffer A and its incrementation, while the third transfer is the return of this incremented value to the PCL (microinstructions OEH, OIH and O2H in hexadecimal code).

The second command of this processor is an indirect one Transfer labeled LII A8, D8.  

Its definition is RAM (D8) <RAM (A8)). This command consists of a sequence of eight basic Transfers as follows: Loading the address register ADRL the value of the field DATA from the ROM; Transfer of the content the RAM thus driven into the buffer A; Transfer the content of the buffer to the address field of the buffer R.A.M; Transfer of the content of ADRL addressed RAM in the buffer; Transfer of the contents of the field ADRL of the ROM addressed RAM in the register ADRL; Transfer of Contents of the buffer in this memory location of the RAM and the last two transfers are the same as before explained command the incrementing of the PCL (MINSTR OF, OB, IE, OB, 10, 13, 01, 02). The following command, which is a direct transfer of position RAM in position RAM is designated LDD A8, D8 net and consists of a transfer of the RAM (D8) into the RAM (A8). This command can be executed in five stages First of all, the loading of the address D8 is effected, that is, DATA in ADRL; then you transfer the Contents of the RAM displayed in the buffer and that temporary; the third stage consists of the transfer the contents of this buffer into the RAM indicated by the ADR and the last two stages serve to increment from PCL (MINSTR OF, OB, 12, 01, 02).

The following command LID A8, D8 is a transfer from the RAM to the RAM, with the source address directly is and the destination address offline. Accordingly, becomes the instruction is referred to as RAM (D8) <RAM (RAM (D8)). The sequence of transfers that the execution of this Enable command corresponds to the microinstructions OF, OB, 10, 13, 01, 02. The following command is JMP D8 it is an unconditional jump instruction, which comes from the Transfer D8 <PCL, that is, the content of the Field DATA is written in the register PCL, what leads to a program jump (micro-instruction 4).

The following command JC D8 is the same command as the previous command except that it is conditional. Namely, it is the value of the remainder (CARRY) that allows to carry out this transfer, that is, if CARRY is 1, the transfer is made, but is omitted if CARRY has the value 0, and the normal instructions of the increment of the register PCL are carried out. Here is an important note to note: It will be noted that in the logic circuit CSL of Fig. 2a, each time a JMP instruction is executed, the counter 402 of Fig. 2 is reset to 0. That is, the instructions of incrementing the PCL register can not be executed and it is directly the following instruction in which to initiate the jump that is now to be performed.

Of course, the entire program uses more Commands defined based on the microinstructions become. These further commands are not in detail explained as they are with regard to the previous one Explanations for the expert are clear.

After explaining the structure and function of the micro-processor, the program will be described, which controls the microprocessor, with reference to Fig. 4 to 7 reference.

Fig. 4 shows in simplified form the algorithm of the program. It first comprises a subroutine 500 INIT for initiation with the aim of controlling the transfer of the data relating to the words of the vocabulary of the clock, which were originally entered and referred to as references. This information is transferred from the DATA field of read-only memory 20 to random memory 18 to facilitate the processing of this information. The algorithm further includes a subroutine 502 for encoding the binary information supplied by the coding circuit 16 , which subroutine is designated WORD. Further, a subroutine 504 called NORM is provided for normalizing the form in which the information relating to a spoken word is conserved. Finally, a comparison loop is provided for the comparison of the spoken word in its coded and normalized form with the words of the stored vocabulary, which of course have been coded and normalized in the same way.

This loop initially includes a subroutine 506 . The subroutine 506 sets the variable k to zero, increments the variable k by one unit after each loop (k = k + 1), and finally compares the value of k with the total number of words of the vocabulary n, and then breaks the cycle. if k equals n, then the program then goes to the output subroutine 508 OUTPUT. The loop also includes a subroutine of correlation 510 CORR which measures the distance between the spoken word and each word of the vocabulary. It finally includes a subroutine 512 BEST for comparing these different distances and selecting that word of the vocabulary whose distance from the word spoken is the shortest.

FIG. 5 shows in detail the algorithm of the subroutine 502 WORD. Prior to the description of this algorithm, with the aid of the timing diagram of Figs. 5a and 5b, the processing to which the algorithm subjects the signal T from the output of the coding circuit 16 , or more precisely the seven parallel signals U'₁ to U'₇, will be described together form this signal T. This processing aims to simplify these signals without loss of information. It is to be noted that the words of the vocabulary of the clock contained in the read-only memory 20 are encoded in the same way as any word spoken by the user with which it wishes to control its clock. It is clear that with increasing simplification of the signal, the number of pieces of information required to store this signal will be reduced. The number of storage spaces required is reduced in this way.

The first curve of Fig. 5a shows the signal U'₁ as a function of the time t at the output of the circuit 34 ₁, wherein the unit is the sampling period, which is for example 10 milliseconds.

It can be seen in this curve that in the zone Z₁, the signal U'₁ has the value 1 with the exception of two sampling periods Z₁ and Z₂, where it has the value zero. These two periods with the value zero are namely not significant for the initial acoustic signal, but only from the fact that in the time zone Z₁, the signal U'₁ has fluctuated around the threshold around. Accordingly, it is desirable to "stuff" these holes by assigning the value 1 to the corresponding samples. Similarly, in the zone Z₂ the signal U'₁ has the value zero except for the sampling periods z₃ and z₄. For the reasons explained above, it is desirable to suppress these transitions by assigning the sampling patterns z₃ and z₄ the value zero. It proves useful, in order not to lose any information, first to suppress the isolated zeros before suppressing the isolated 1 values. The curve U''₁ provides the signal obtained after suppression of the isolated zeroes in the signal U'₁ and the curve U '''₁ shows the signal obtained after successively the isolated zero values and then the isolated ones 1 values have been suppressed in the signal U'₁. This process is subjected to each signal U ' _i .

The procedure shown in Fig. 5b is to globally apply to the totality of the seven signals U '''₁ to U''' ₇ which have already been subjected to processing, as explained above with reference to Fig. 5a. This procedure corresponds to the fact that they are the transitions, that is, the changes in the logic level of the signals that are characteristic of the acoustical message contained in the electrical signal. Accordingly, when a vowel is pronounced in a word, the seven signals U'₁ to U'₇, or more specifically, the signals U '''₁ to U''' ₇ may all retain the same logic value during a higher number of consecutive sampling periods. This situation is accordingly effectively represented.

As already explained, each one ent speaking signal "normalized" or standardized, that is, the number of scanning patterns, which actually be processed for each signal, z. B. is limited to 16. Every normalization consists of Homoth'tie, applied to the totality of Scanning pattern of a word. If, for example, the Comprise signals U '' '₁ to U' '' ₇ each n₁ scanning pattern, the ratio 16 / n₁ is applied in each signal. This means that in every signal and for each Segment, that is, for each successive, the same group of sample patterns, the number of patterns of the segment with the ratio 16 / n₁ is multiplied. It is accordingly clear that by maintaining the important portions of the signals U '' '₁ to U' '' ₇, for which there are no transitions, not only the quality of the retained signal is not improved but this may even be changed because of the fact that in Homoth'tie the fast Transitions the signals can be lost. In addition, these transitions contain an interest sante imformation.

The procedure illustrated by Fig. 5b is as follows. It is detected in the set of signals U '''₁ to U''' ₇ the successive scanning patterns, for which none of the signals has a transition. If this number of sampling patterns exceeds a value of n₂ (in the example of Fig. 5b, the value of n₂ = 5), the sampling patterns are suppressed from the (n₂ + 1) most until a transition is detected at any of the signals U '. '' ₁ to U '''₇.

It can be seen accordingly in Fig. 5b, that between the times t₁ and t'₁ the signals U '''₁ to U''' ₇ (only the signals U '''₁,U''' ₂ and U ''' ₇ are drawn to simplify the illustration), maintain their logic level 1. Similarly, between the times t₂ and t'₂ keep the signals the logic level 0. According to the above-mentioned processing, the patterns of the signals between t₁ and t'₁ + 5 are maintained and suppressed between the times t₁ + 5 and t'₁. In the same way, the sampling between the times t₂ and t₂ + 5 are maintained, but suppressed between the times t₂ + 5 and t'₂. The signals W₁, W₂ and W₇ represent the signals obtained after this processing and correspond to U '''₁,U''' ₂ and U '''₇.

In order to realize these various operations, the subroutine WORD of Fig. 5 uses a plurality of variables to be specified. The variable LENGTH is related to the length of the word; the variable SEGNUM is a memory pointer; the variable GAP is related to the number of consecutive samples of logic level 0 after a non-zero sample of that word has been detected. The variable V is related to the successive number of sample patterns without a transition having occurred. The variables L, K, J, I represent positions of the RAM memory 18, and L (8) represents the highest binary digit binary value of the information contained in the memory 18 at the address L. This binary value is always 1 and is used to synchronize the program.

After beginning 600 of the program, instruction 601 initially sets the variable LENGTH to zero.

The instruction 602 sets the reference of the memory SEGNUM to the value BUF1, which is the address of the first position of the random access memory, intended to receive the sampling patterns of the word to be coded.

Command 604 sets variables V and GAP to zero.

Command 606 sets the variables I, J, and K to zero.

The command 608 causes the transfer of the input register INPUT scanning pattern contained in the storage position L. The 610-614 commands are used Synchroni organization of the program. Test block 614 compares the pattern contained in memory at address L to zero. If the test is negative, that is, if the pattern is not zero, then the instruction 618 holds the variable GAP at zero or returns it to zero.

The instruction group 620 implements the processing of FIG. 5a, that is, the suppression of isolated zeroes and ones. For this purpose, the four memory positions L, K, J, I play the role of a shift register with four digits. By the commands 620 a to 620 e each scan pattern passes successively through the positions of L and I in increments of one at each clock signal. Command 620 f suppresses isolated zeros. It consists of performing the logical operation K = K (OR) (J ∧ L), where OR represents the function or and ∧ the function AND. Of course, this operation will affect the 7-bin positions of the scan patterns simultaneously. It is well known that if a pattern of the address J and / or the pattern of the address L is zero, that is, if the pattern K is not "enclosed" by patterns J and L of the values 1, the term J ∧ L is zero and the value of the pattern K is not modified. On the other hand, if J and L are both equal to 1, the value of K is brought to 1, regardless of its original value. The 620 g command causes the isolated ones to be suppressed. It consists of the logical sequence J = J ∧ (I OR K). If the pattern J is initially zero, it retains that value. If J 1 it, this pattern assumes zero only if the patterns I and K are both zero. This corresponds exactly to the suppression of an isolated "one". The operation 620g is offset by a storage position relative to the operation 620f, so that this latter is executed first.

Instruction 622 serves to detect a possible transition between the two consecutive patterns L and I. It consists of the logical operation L '= L (XOR) I, where the symbol (XOR) signifies the function OR EXCLUSIF.

It can be seen that if L and I are different that is, if there is a transition in one of the Signals U '' '₁ to U' '' ₇, L 'takes the value 1. On the other hand, if L and I are identical, L 'takes the value Zero on.  

Instruction 624 compares the value of L 'to zero. If L 'deviates from zero, that is, if L and I are different, instruction 626 sets variable V to zero or returns it to zero. The entirety of the instructions 628 transfers to the random access memory at the address SEGNUM the scan pattern L; it increments the variable SEGNUM by 1; it transfers the value of the variable LENGTH to the random access memory under the new address SEGNUM and finally increments the variables LENGTH and SEGNUM by 1. Thereafter, the subroutine is returned to the instruction 608 for processing the following sample pattern.

If instruction 616 has determined that L = 0, that is, sample L is all zeros, the subroutine goes to instruction 630 , which compares variable LENGTH to zero. If this variable is zero, the subroutine returns to instruction 602 . This means that the already entered scanning patterns are all zero. If the variable LENGTH deviates from zero, the instruction 632 increments the variable GAP by 1 and the instruction 634 compares this new value of GAP with 20. If the variable GAP is 20, one leaves the subroutine WORD for entry into the subroutine NORM. It will be appreciated that if 20 consecutive sample patterns are zero after non-zero sample patterns had occurred (LENGTH ≠ 0), the user's spoken word is considered completed. However, if the variable GAP is less than 20, go to command 620 .

If instruction 624 has determined that L = zero, that is, there is a repeat, instruction 636 increments variable V by one unit and instruction 638 compares this new value of V to 6.

If variable V is less than 6, instruction 640 increments variable LENGTH by one unit and the subroutine returns to instruction 608 . However, if variable V = 6, the subroutine returns directly to instruction 608 .

It will be appreciated that commands 624, 636, 638 and 640 implement the processing described in connection with FIG. 5b. Namely, instruction 624 determines whether a scan pattern is identical to the previous scan pattern; command 636 counts the number of consecutive identical scan patterns and command 638 compares that number to 5. Once this number is greater than 5, it will be seen that the variable LENGTH is no longer incremented, corresponding to the suppression of scan patterns. This suppression is maintained until instruction 624 determines that L 'is zero, that is, a repeat occurs.

It should be noted, however, that in the random memory 18 is an address of two for storing the value of a sample and the following address of the storage of the value of the variable LENGTH, which determines the position of this sample in the word, after this the described processing ent has been subjected to the Fig. 5a and 5b has been subjected. Further, it will be appreciated that storage by instruction 628 occurs only when L 'deviates from zero. That is, a scanning pattern is stored only if it deviates from the previously stored sampling pattern.

In the sequence of this subroutine, the random access memory 18 accordingly contains, under successive addresses, information representing the value of a scanning pattern other than the previous scanning pattern and information LENGTH representing the position of this scanning pattern in the signal.

The subroutine NORM shown in FIG. 6 has the task of standardizing or normalizing the number of scanning patterns forming the coding of the spoken word. In the example considered, the number of scan patterns = 16. The total number of sample patterns stored at the end of the subprogram WORD is equal to the final value of the variable LENGTH reduced by 20. Namely, the end of a word when the variable GAP = 20 is zero corresponding to 20 sample patterns. Accordingly, the number representing the position of a sample in the word must be multiplied by the ratio 16 / (LENGTH-20). This is done in the subroutine NORM.

The subroutine NORM uses the variables I and J, which represent the addresses of the random access memory 18 . The instruction 650 sets the variables I to the value BUF I corresponding to the first address of the random access memory containing information concerning that word; it increments the variable 1 by two units and compares the variable I with the value SEGNUM, which indicates the last address of the random memory containing an information concerning the word. The following instruction 652 increments the variable I by one unit and extracts from the random access memory the information of the address I + 1, which is written M (I + 1). This information corresponds to the value of the variable LENGTH for the scanning pattern whose value is stored under the address I. The instruction 652 then calculates the quantity M (I + 1) × 16 / LENGTH-20) and feeds this calculated value back under the address I + 1.

Instruction 654 compares the value of M (I-1) -M (I + 1) with 1. If this difference is greater than 1, the subroutine returns to instruction 650 , which increments variable I by two units. This implies that I takes a new value corresponding to the address in the Random memory 18 for the position information associated with the following scan pattern. If the difference is less than 1, this means that there is a "telescoping" between the sample patterns of addresses I-2 and I due to normalization. In other words, this means that the duration of the ent speaking segment before normalization was insufficient, that this segment would still exist after normalization.

In this case, one must suppress the information regarding sampling patterns of this segment and shift the following information by two addresses. This is accomplished with instructions 656 and 658 . Command 656 reduces by 2 the value of variable SEGNUM because the word contains two less information; he substitutes the variable J for the variable I; it increments the variable J by 2 and compares the value of J with the new value of the variable SEGNUM. The command 658 effects the shift by two steps of the entirety of the information. Subcommand M (J) = M (J + 2) transfers to address J, the information originally stored at address J + 2. It is an information of the value of the scanning pattern. The sub-instruction M (J + 1) is = M (J + 3), transferred to the address J + 1, the information originally stored at the address J + 3. It is an information of the position of the sample in the word. Once instruction 656 detects J = SEGNUM, that is, all information has been advanced by two steps, the subroutine returns to instruction 652 because the loop formed by instructions 656, 658 already increments variable I by two units Has.

If after a certain number of cycles the instruction 650 determines that the variable I is greater than SEGNUM, the program proceeds to the subroutine CORR, which measures the measurement of the distance between the user-pronounced and the sub-programs WORD and NORM coded or normalized word and the various words of the vocabulary of the clock, which were originally stored in the read-only memory and have been transferred to the random access memory of the subroutine INIT. It is understood that these words referenced here have been coded and normalized with the same algorithms as the word spoken by the user.

After a word spoken by the user of the watch coded and normalized, the information,  which it contains, in the form of a matrix with i-lines and j columns. In the example above i has the value 7 and j the value 16. Each column contains the 7-binary information of a sample and a Line contains the binary information, derived from the coding and normalization of the signal generated by has been submitted to a filter channel.

A word is defined in the following way:

Word = (word _i , _j ; i = 1, 2, _... , 1, j = 1, 2, ..., J)

where word _i , _j ∈ (0, 1)

for example, in the case of Fig. 6a, the information word _{3, 13 is} zero and word _{7, 15 is} one. Similarly, the memory 20 of the references may be defined as a set of coded word reference information defined by:

Ref = (Ref ^k , k = 1, 2, ..., n)

where n is the number of references originally contained in the memory, that is, the number of words of the vocabulary. Each word of the memory is denoted by Ref ^k with

Ref ^k = (Ref ^k _{i, j} ; i = 1, 2 _{, ...} , I, j = 1, ..., J).

The distance between an encoded word "word" and a reference of the memory Ref ^k is given by the equation:

Where is the character ⊕ the logical function OR EXCLUSIF, I indicates the number of channels and J is the number of scanning patterns.

It is clear that this distance can be defined concretely in the following way. It is based on a table similar to that of FIG. 6a, corresponding respectively to the words "WORD" and the reference Ref ^k and you superimpose these two tables each other. The numerator of the right-hand part of Equation 1 is equal to the number of points of the two tables with the binary value 1 which do not overlap each other, while the denominator is equal to the sum of points of both tables having the binary value 1. In Fig. 6b, a table corresponding to a word and a table corresponding to a reference Ref² are shown. It can be seen immediately that when the two tables are superimposed, as they are, the points with the binary value 1 which are superposed on one another are not present in large numbers. In other words, the distance between these two words is great. It can be seen, however, that by moving the contour of the table of the word to the left without modification of the position of the points with the binary value 1, the similar speed between the two tables modified in this way is very large. It is easy to understand that in fact the word and the reference belong to the same spoken word, and that the apparent difference derives exclusively from a total shift in the recording and coding of the word. Accordingly, in order for the measurement of the distance between two words to be truly useful, it is desirable, inter alia, to contemplate the possibilities of displacement between the words to be compared or between the word and the reference to be compared with it. This will be explained below, the shift being denoted by 1, which in the case of Fig. 6b is -1.

Introducing the displacement l, the distance δ ₁ between the word WORD and the reference Ref ^{k is} defined as follows:

To compare a word and a reference or two words together you calculate the Ab states δ for the displacements of l = l₁ to l = -l₁ in steps of 1. Example: l₁ = 2.

The distance δ _k between the spoken word WOR T and the reference Ref ^k is defined by the relationship:

δ _k = INF (δ _l : l = -l 1 ... + l 1)

In this case, BEST _{k is to be} the smallest distance between the word spoken by the user of the clock and the word of the vocabulary designated Ref ^k .

The subroutine BEST selects among the values BEST _k for k continuously from 1 to n (n: number of ref of the vocabulary) that is the smallest. In this way, the reference word Ref ^{k is} selected.

The subroutine BEST of FIG. 7 includes the instruction 670 which compares BEST _k that has just been calculated with BEST, which represents the smallest distance so far defined. If BEST is less than BEST _k , the program returns to instruction 506 of FIG. 4 to calculate a new value of BEST _k . If BEST _{k is} less than BEST; Command 672 substitutes the new value of BEST _k for the previous value of BEST. If the instruction 506 determines that all references of the vocabulary have been compared to the spoken word (k = n), the program proceeds to the output subroutine OUTPUT 508 . This subprogram provides the signal N for the control of the circuit 28 . This signal is divided into a signal WORT, which contains in binary form a coding of the reference which has been selected, and a signal PRET, which is simply a pulse indicating that a word has actually been heard and chosen is through the whole of the processing facilities B.

As explained above, the circuit D generates for generating the logic information for each ge Word word, on the other hand, a signal WORD that characterizes ristic is for the spoken word and on the other hand a signal PRET indicating that actually a word  is available.

Fig. 8 shows the individual the structure of the conversion circuit 28 for the logic controller.

Before this circuit is described in detail, is it useful to explain the way in which the logic information, which consists essentially of the Signals WORD exist, are processed to the tax generate signals. In the first example considered the clock has three functions, a function MONTRE for the time display with hours, minutes and seconds Customers, a function REVEIL which the hours and minutes indicates a function TEMPORISATEUR, the ge usually called TIMER and at the hour, Minutes and seconds occur.

For each function or function mode must you can control the release DEPART or the lock ARRET can. Finally, the specification requires a complete the use of 6 digits (hours, Minutes, seconds) from zero to nine. That for the Control of the clock required vocabulary includes accordingly 15 words. There are accordingly 15 different signals WORD.

It will be appreciated that full control requires a function of multiple instructions which the user must enter into the clock in precise order. The first command concerns the function to be performed. It is a command "MODE". The user then has to indicate whether the function should be started or ended (DEPART or ARRET). Finally, the user must sequentially specify the corresponding digits associated with a time information. These digits correspond successively to the tens digit of the hour (DH), the digit of the hour (H), the tens of the minutes (DM) and the digit of the minutes (M), for the function REVEIL, and beyond that the tens of seconds ( DS) and the units of seconds (S) for the functions MONTRE and TEMPORISATEUR. The complete control of a function accordingly requires the input of six or eight consecutive instructions classified chronologically. To account for all of this information, circuit 28 provides three control signals: a MODE signal which can take three binary numeric different values corresponding to the MONTRE, REVEIL and TEMPORISATEUR functions, respectively; a signal INFO, which may take ten binary different values for the representation of either the DEPART or ARRET information or one of the ten digits, and a SEQ signal that represents, in binary form, the rank of the command given by the MODE or INFO signal in the Sequence of commands according to the commissioning of a function is given. The signal SEQ assumes the value zero when the signal MODE is generated. For example, it assumes the values one to five or one to seven to mark the input of the command DEPART or ARRET (as at 1) and the input of the signals INFO corresponding to DH, H, DM, M (values 2 to 5) or DH , H, DM, M, DS, S (values 2 to 7). At each instant in which the clock is under control, the circuit 28 generates a signal MODE indicative of the function to be performed, a signal INFO and a signal SEQ, the combination of which provides the data which one wishes to input, finally triggering or terminating the respective one Function.

To generate the signals MODE, INFO and SEQ, the circuit 28 comprises a multiplexer 50 , the input 50 a receives the signal MOT. This multiplexer comprises two outputs 50 b and 50 c, which provide the signals MODE and INFO, and a control input 50 d. Depending on the binary logic level, which is at this input 50 d, the output signal from the multiplexer 50 appears on the output 50 b or the output 50 c. The output 50 b of the multiplexer is connected to the input 52 a of a memory 52 to a charging input 52 b.

The signal PRET is applied to the control ring 54 a of a monostable circuit or flip-flop 54 which produces a pulse at its output 54 b with a delay r, relative to the time of application of the control signal. This delay r is example, 5 seconds. The output 54 b of the flip-flop is connected to the clock input 56 a of a counter for N ', which is designated 56 . N 'is the integer equal to the total maximum number of commands required to control a function of the clock. In the example considered, N 'is equal to 8.

First, the counter is set to zero. Each time a period of time r (5 seconds) has passed between a pulse of the signal PRET and the next pulse of this same signal, the latter pulse causes the Incre mentation of the counter 56 by one unit about the tilting circular 54th When the contents of the counter arrive at seven, the following pulse resets the counter to zero. Since the application of a pulse of the signal PRET to the flip-flop 54 corresponds to the application of the signal MOT to the multiplexer 50 , it is clear that the successive contents of the counter 56 corresponds to the rank of the instructions for one and the same function successively in the Clock can be entered.

The output 56 b of the counter 56 accordingly supplies the signal SEQ. The signals MODE, INFO and SEQ are respectively applied to the outputs 58 and 60 or 62 of the circuit 28 .

The circuit 28 further includes a zero comparator 64 , the input 64 a to the output of the counter 56 is connected ver. The circuit 64 provides a signal of logic level 1 when the signal SEQ at its input 64 a is zero. This logic level 1 controls the activation of the output 50 b. Conversely, when the input 50 d is at level zero, it is the output 50 c, which is activated. The output of the comparator 64 is further applied to an input of an AND gate 66 , to the second input of which the signal PRET is applied. The output of the AND gate 66 is connected to the charging input 52 b of the memory 52 . The circuit 28 further includes a circuit 68 which allows the reset to zero of the counter 56 when the function to be performed is the function REVEIL and the four corresponding numerical information has been entered. For this purpose, the circuit 68 comprises a six-capacitor 70 whose input 70 a is connected to the output 56 b of the counter.

It should be kept in mind that the signal SEQ takes the value 6 after the display of the fourth numerical information and that this information is the last to be delivered in the case of the function REVEIL. The circuit 68 further includes a detector 72 for the mode REVEIL. The detector 72 receives at its input 72 a signal MODE supplied from the memory 52 and at its input 72 b has a numerical value entspechend the value of signal MODE for the function REVEIL (z. B. 1). The outputs of the detectors 70 and 72 are connected to two inputs of an AND gate 74 . When the signals at the output of the detectors 70 and 72 are both at logic level 1, the gate 74 provides a logic signal of level 1 to reset the counter 56 to zero.

A circuit 76 has the task of setting the counter 56 to zero when the commanded function requires only two commands, namely a MODE command and a DEPART or ARRET command. This is the case, for example, if the user only wants to put the watch into operation after it has been stopped. The commands are according to MONTRE and DEPART. For this purpose, circuit 76 includes a paired comparator 78 , whose input 78 a is connected to the output of the counter 56 . It is important to remember that the signal SEQ takes the numerical value 2 for the input of the first numerical data. The output of the detector 78 beauf hits one input of an AND gate 80 , the other input 80 b receives the pulses of the signal PRET. The output of the gate 80 is connected to the input S of a flip-flop RS 82 . The output of flip-flop 82 provides a signal which sets counter 56 to zero when this signal is at logic level one. The outputs of the flip-flop 82 and the gate 74 of the circuit 68 are connected to the inputs of an OR gate 84 . The output of gate 84 is connected to an input of an AND gate 86 and the second input of gate 84 receives the signal from flip-flop 54 .

The output of the gate 86 is connected to the zero reset input 56 c of the counter 56 . For example, the detectors 64, 70, 72 and 78 are comparators which compare the binary positions of the two signals one after the other and output an identity signal if the total of the binary positions of both signals are identical.

The function of circle 28 is the following:

When the user pronounces the first word associated with one of the three functions, a signal MODE and a pulse of the Signlas PRET appear at the inputs 50 and 52 . Taking into account the time constant of the mode-stable multivibrator or flip-flop 54 , the counter 56 remains at zero and the signal SEQ has the value zero.

The information contained in the signal MOT is input to the multiplexer 50 . Simultaneously, the detector 64 provides a signal of the logic level 1, which controls the Akti vation of the output 50 b of the multiplexer. The information contained in the signal MOT is accordingly interpreted as a signal MODE whose respective value defines the function to be performed. Further, the logic level 1 signal supplied from the gate 66 controls the loading of the information MODE into the memory 52 . If the user is wrong in the function, he has 5 seconds to enter a new function. Namely, for 5 seconds, the counter 56 remains at zero, and every newly-spoken word during this period of time is thus regarded as information substituting MODE for the previous one. Of course, if the user corrects the name of the function, the new pulse of the PRET signal will restart for 5 seconds. At the end of 5 seconds, the user can introduce the second indication. The counter 56 is accordingly 1, the signal SEQ is 1 and this command is interpreted as a DEPART or ARRET command. The detector 64 controls the excitation of the output 50 c of the multiplexer and at the output 60 the signal INFO assumes the corresponding value for the command DEPART or ARRET. 5 seconds later, the counter 56 is incremented to 2 (the signal is 2). The user can accordingly enter the third command within a delay of 5 seconds. If it does not, that is if the function includes only two instructions, the circuit 76 detects this situation and resets the counter 56 to zero.

However, if the user pronounces a word within these 5 seconds, the counter will not be reset to zero and the INFO signal will take the value corresponding to the spoken word. This is a number representing the tens digit of the hours. The fact that it is the tens of hours is represented by the value 2 of the signal SEQ. Thereafter, the user inputs further information, whereby each time the counter 56 is incremented by one unit and accordingly the numerical value of the signal SEQ. When the controlled function is the REVEIL function, the circuit 68 resets the counter 56 to zero after entering four numerical information. If it is another function, counter 56 will automatically reset to zero after entering six numerical information (DH, H, DM, M, DS and S). Of course, after entering each of these data, the user has a period of 5 seconds or more, generally a period of time r to correct the data, and after this correction, he re-verifies over a 5 second period for re-correction the data. It can be seen clearly that the circuit 28 has a user-independent auto matism, with the rank of the user is given information and thus their nature is determined. As will be explained, this automatism also serves to inform the user of the nature of the errand which he must give the watch.

Fig. 9 shows in more detail the section B of the watch, and in particular the display control circuit 6 . This circuit comprises in conventional manner ago divider stages 101 to 106 , starting from a signal of 1 Hz respectively the second signals (S), the tens of seconds (DS), the one minutes (M), the ten minutes (DM), the one-off of hours (H) and tens of hours (DH). These dividers serve to generate the time display information. They are designated by the reference numeral 107 in total. This corresponds to the function or the mode MONTRE accordingly. The circuit further comprises divider stages 113 to 116 , corresponding to the generation of an alarm time (REVEIL function). They each provide the information M, DM, H or DH and are denoted overall by 117 . Finally, dividers 121 to 126 are found , which are designed as down counters and respectively supply the signals S, DS, M, DM, H and DH. These dividers are used to generate the function TEMPORISATEUR and have the overall reference 127 . Furthermore, in a classical embodiment, a counter 128 is found which compares the state of the time counters 103 to 106 with the state of the wake-up counters 113 to 116 . When the comparator 128 detects the identity between these two groups of counters, it activates the acoustic generator 10 . The circuit further comprises decoders 131 to 136 known per se, which control the numerical display elements 141 to 146 in accordance with the information S, DS, M, DM, H and DH and are denoted overall by 8 in FIG . Finally, the display means for the function comprise the symbols 151, 152 and 153 corresponding respectively to the function MONTRE, the function REVEIL and the function TEMPRISATEUR. Overall, they carry the reference numeral 11 in FIG. 1.

The circuit 28 further includes special elements associated with the control of the clock by voice. Among these elements, the Adressierbaugruppe 160 to mention that a MODE signal receives on a first input 160 and to the second input 160b, the signal SEQ.

This addressing unit 160 serves to control the charging of the counter, which must receive the information contained in the signal INFO. The signal INFO is simultaneously applied to all parts 101 to 106 , 113 to 116 and 121 to 126 via a collection channel BUS 162 . For each of these dividers, the loading entrance is labeled b to simplify the drawing. In addition to these dividers, there are three memories 164, 166, and 168 , respectively, associated with the MONTRE, REVEIL, and TEMPORISATEUR modes, respectively. These memories store DEPART or ARRET information for each function. The channel bus 162 of course sets the signal INFO also to the inputs of the memory 164, 166 and 168 , which are also marked with b. The INFO signal also contains the information DEPART or ARRET. The memories 164 and 168 also have the task of applying or interrupting the application of the signal of 1 Hz from the divider stages 4 to the clock input CK of the groups of counters 107 and 127 for the time function or for the temporary function. For this purpose, the output c of the memories 164 and 168 is connected to an input of an AND gate 170 and 172 , respectively. The other input of these gates receives the signal of 1 Hz.

To describe the addressing circuit 160 , it is assumed that the signal MODE assumes the numerical values 0, 1 or 2 for the functions MONTRE, REVEIL or TEMPORISATEUR. It is further assumed that the signal SEQ takes the numerical values 0 to 7 for the signal MODE or the information ARRET or DEPART and for the information DH, H, DM, M, DS, S, which results in the table according to FIG ,

The input 160 a is connected to the first inputs 174 a, 176 a and 178 a of the comparators 174, 176 and 178 , which respectively compare the applied signal at its first input with numerical values 0, 1 and 2. As a result, a signal of the logic level appears 1 at the output of comparator 178 , when the TEMPORISATEUR function is controlled, at the output of comparator 176 for the REVEIL function and at the output of comparator 174 for the MONTRE function. The input 160 b of the construction group 160 is connected to a first input of the divided into three groups and 190 to 196, 200 and 203 to 206 and 210 to 216 divided comparators, each group is assigned to a function. The addressing can be divided in this way in three modules 160 ₁, 160 ₂ or 160 ₃, which are assigned to the functions MONTRE AND REVEIL or TEMPORISATEUR. These assemblies have similar structure to each other. The comparators 190 to 196 each compare the signal SEQ with numerical values 1, 7, 6, 5, 4, 3 and 2, the meaning of which is given by the information in the table in FIG . Similarly, the comparators 200 and 203 through 206 compare the signal SEQ with the values 1, 5, 4, 3, and 2. Finally, the comparators 210 through 216 compare the signal SEQ with values 1, 7, 6, 5, 4, 3, and 2 Consequently, when a logic signal of level 1 appears at the output of the comparators 190, 200 and 210 , this means that the signal INFO contains the information DEPART or ARRET when a logic signal of level 1 appears at the output of the comparators 193, 203 and 213 , this means that the INFO signal contains minute information (M), etc.

With the first group of comparators 160 ₁, seven AND gates 220 to 226 are connected to 2 inputs. Each AND gate receives at one of its inputs the output of comparator 190 to 196 , which has a reference with the same one digit as itself, and at its other input the output of the comparator 174 . AND gates 230 and 233 to 233 to 236 are assigned to the second group 160 ₂ of comparators, and AND gates 240 to 246 are assigned to the third group 160 ₃ of comparators in an analogous manner. The outputs 220 b to 226 b, 230 b, 233 b and 240 b to 246 b of the AND gate at the same time form the outputs of addressing 160 . It will be understood that the linear cascade structure of the circuit 160 is the equivalent of a three column and seven row matrix structure. It need not be explained in detail that at any one moment only one of the AND gates carries logic 1 at its output. It is that gate which is assigned to the value which the signals MODE and SEQ are currently having. For example, the AND gate 234 provides the logic signal 1 when the user commands the display of tens of minutes for the REVEIL function. Each output 220 b to 246 b is connected to a charging control input a of the corresponding counter 101 to 126 or the corresponding memory 164 to 168 . It will be appreciated that at any one time the information contained in the signal INFO is applied to all the load inputs b of the counters 101 to 126 and the memories 164 to 168 and that this information is input to the associated memory or counter by applying to its load control input a Signal of the logic level 1, supplied by one of the outputs 220 b to 246 b of the addressing circuit 160 , which output is defined by the numerical value of the signals MODE and SEQ, which are present at the same moment.

The state outputs 101 c to 106 c of the counters 101 to 106 are connected to lines 251 to 256 . Similarly, the outputs 113c to 116c of the counters 113 to 116 are connected to the lines 263 to 266 , and the outputs 121c to 126c of the counters 121 to 126 are connected to lines 271 to 276, respectively. Finally, the outputs 164 c to 168 c of the memory 164 to 168 are placed on lines 284 to 286 . It goes without saying that the first group of four inputs 128 a of the alarm triggering comparator 128 is connected to the lines 253 to 256 , while the second group of four inputs 128 b of the comparator 128 is connected to lines 263 to 266 , As is well known, comparator 128 provides a logic signal when the values at its two groups of inputs are identical. This signal is applied to one of the inputs of an AND gate 289 . The other input of this AND gate 289 is on line 286 . In this way, the signal is applied to the acoustic generator 10 only when the memory 166 contains the information DEPART, that is, has been arranged to wake up the function.

The decoders 131 to 136 are fed by multiplexers 291 to 296 . Each multiplexer has three inputs labeled a, b and c, respectively. The inputs a are connected to a line of a first group of lines 251 to 256 , the inputs b to a line of a second group of lines 263 to 266, and the inputs c to a line of a third group of lines 271 to 276 . Of course, the multiplexers 292 and 291 , which cause the display of the seconds and the seconds to be set, have their input b set to zero because the function REVEIL does not include the seconds. More specifically, one of the inputs a, b or c of a multiplexer is connected to the line of the group of lines corresponding to the same time unit as the multiplexer. For example, the input a of the multiplexer 293 serving the minute display is connected to the line 253 , its input b to the line 263 and its input c to the line 273 . Each multiplexer receives at its inputs three information corresponding to three functions of the clock. It is necessary to select those of the three pieces of information to be supplied to the associated decoder. For this purpose, each multiplexer comprises a control input d, which receives the signal MODE via line 300 . The value of this signal determines that of the three pieces of information that should appear at the output e of the multiplexer.

In order to inform the user of the clock about the information which he can control by voice, it is provided either to flash the entirety of the display elements 141 to 146 or only one of these elements or none. To do this, each decoder includes a control input a. Either there is no signal at this input and the display is permanent, or he receives a signal of 2 Hz, which comes via the line 302 .

For each decoder, the application of the 2 Hz signal to input a is controlled by a logic circuit. There are accordingly six logic circuits 311 to 316 . Each logic circuit comprises a numerical comparator portion and a gate portion controlled by the comparison signal. An input a of each logic circuit receives the signal of 2 Hz. The other input b of the logic circuit receives the signal SEQ, transmitted via line 304 . The comparator part of each logic circuit compares the numerical value of the signal SEQ with the value 1 and with a numerical value, corresponding to the numerical value of the signal SEQ for the display of the time units, which the respective decoder has to control. The table indicates these numeric values. For example, the circuit 313 associated with the minute-setting decoder 133 compares the signal SEQ with the values 1 and 5, the value corresponding to 5 minutes.

If the signal SEQ has a value of 1 or a value of comparison, the gate part is turned on and the 2 Hz signal is supplied to the decoder, resulting in the flashing of the display element driven by this decoder. In the other case, the gate part remains locked. Accordingly, no signal is applied to the input a of the decoder. So if the user can enter the depart or ARRET commands, the signal SEQ is set to 1 and all the display elements 141 will flash until the 146th After that, it is the display element that the user can control, which flashes.

Finally, it is necessary to be able to control the excitation of the elements 151, 152 and 153 for the function display. This control takes place via the logic circuit 320 . This circle 320 comprises three OR gates 321, 322 and 323 . Each of these gates receives a 2 Hz signal at one of its inputs, supplied via line 324 .

The other input a of each OR gate, which has an inverting effect, is connected to one of the lines 284, 286, 288 . Consequently, each input of which receives a state of that memory 164-168, is associated with the function that controls the considered OR gate. The circuit 320 further includes three logic circuits 321 ', 322' and 323 ' . Each logic circuit receives on a first input a the signal output from the associated logic gate to a second input b the signal MODE transmitted via line 300 .

This logic circuits have the same nature as the circuits 311 through 316. They comprise a numerical comparator part in which the signal MODE applied to the input b is compared in one of the three values which the signal MODE can assume, and a gate part which the signal applied to the input a can only pass through if the signal Comparison is positive.

In other words, memory 166 is in state 0 when the user sequentially commands REVEIL and ARRET.

The input a of the OR gate 321 is inverting and this gate receives a signal of the logic level 1 which accordingly blocks the 2 Hz signal. The logic circuit 322 ' compares the signal MODE with the value 2. Since the user has arranged the function REVEIL, the signal MODE has the value 2. The circuit 322' accordingly supplies at its output the DC signal applied to its input a. The display element 152 is accordingly constantly energized. However, if the user had sequentially commanded REVEIL and DEPART, the OR gate 322 would have delivered the 2-Hz signal and the indicator 152 would have flashed.

Hereinafter, the function of the clock will be explained with reference to the command sequence of FIG. 11.

In this figure, the first column shows the number the phase of the function. The second column shows the vo 60302 00070 552 001000280000000200012000285916019100040 0002003226929 00004 60183m User pronounced words and the third shows what the display device of the clock represents. In this Figure is the seconds and tens seconds presented to simplify the understanding. These Ads only change during clock control and only because of the passage of time when the function MONTRE is triggered. The example considered relates to a change of the time zone.

At the beginning of this sequence, assume that the MONTRE function of the clock is in operation, that is, memory 164 is loaded with the value 1. As a result, and in the absence of other instructions, the dividers 101 through 106 are incremented by the 1 Hz signal. The user places the watch in the listening position by operating the switch 40 .

The counter 65 is at zero and the signal SEQ accordingly has the value zero corresponding to the input of a "MODE". The user pronounces the word MONTRE (Phase 1). The circuit D analyzes the word uttered, compares it with the stored references, and generates a signal MOT whose value corresponds to the associated reference and a pulse PRET.

Since the signal SEQ is null, MOT is interpreted as a signal MODE, whose value is stored in the memory 52nd Since the signal SEQ is zero, all outputs of the addressing circuit 160 are at zero level. Only the 1 Hz signal increments counters 101 through 106 because gate 170 is open. The signal MODE is applied to the control circuit 320 .

The logic circuit of the circuit 320 , which makes the comparison with a value equal to that which the signal MODE actually has, is accordingly opened and the display element 151 to 153 corresponding thereto is energized. The user can thus control whether the reference used by the circuit D coincides with the word he has actually spoken. If it is the indicator 151 which is being energized, the user will notice that the watch has correctly understood the word MONTRE. If so, and if, as already indicated, the clock is in the working position (DEPART), the display element flashes. If the clock was in the ARRET position, the item 151 had not flashed. If the energized element is Element 152 (REVEIL function), the user determines that there is an error and has 5 seconds to repeat the word MONTRE. It is assumed that element 151 is the one which is flashing. 5 seconds after the word MONTRE has been asserted, monostable multivibrator 54 emits a pulse which increments counter 56 by one. The signal SEQ now has the value 1. The logic circuits 311 to 316 determine that the signal SEQ has the value 1 and the signal with 2 Hz is accordingly applied to all decoders 131 to 136 . The six display elements 141 to 146 flash. This is shown in FIG. 11 as phase 2. The user knows he can enter the command DEPART or ARRET. In the example considered, the user says ARRET. The signal MOT containing this information is applied to the input of the multiplexer 50 . Since the signal SEQ has the value 1, the output 50 c of the multiplexer is energized.

A signal INFO is thus obtained, since the signal MODE stored at 52 , still has the value zero and the signal SEQ has the value 1, a logic level 1 signal appears at the output of the gate 220 of the addressing circuit 160 . The memory 164 is open and the value of the INFO signal is input to this memory. This closes the AND gate 170 and the dividers 101 to 106 are no longer incremented. The clock stops. In addition, the input a of the logic circuit 321 ' receives a continuous signal. The display element 151 does not blink accordingly. On the other hand, elements 141 to 146 continue with the process (phase 3).

If the user wants to restart his watch, 5 seconds following the word ARRET will give him the word DEPART. This possibility is indicated by the fact that the entirety of the display elements 141 to 146 flashes. Phase 4 illustrates the restart of the clock.

If during this period of 5 seconds the user has not said anything, the monostable circuit will again pulse and the signal SEQ will now be 2. This value is detected by the circuit 78 . Moreover, if the user does not pronounce a word for 5 seconds (no PRET pulse), the output of the circuit 76 emits a logic signal that sets the counter 56 to zero and the clock returns to the initial state. Assume that the user has actually said DEPART, that is, that the clock has been set in motion. 5 seconds after the user said DEPART, the monostable circuit again provides a pulse and the signal SEQ is 2. Since the MODE signal is still zero and the SEQ signal is 2, it is the address circuit gate 226 160 ₁, which outputs a signal which opens the counter 106 (tens of hours). Further, the display element 151 continues to blink. The logic circuit 311 detects that the signal SEQ has the value 2. The 2-Hz signal is accordingly applied to the decoder 131 and the display element 141 continues to flash. The other logic circuits 312 to 316, on the other hand, are not open (since the signal SEQ is neither 1 nor has the value to which these circuits are programmed). The display elements 142 to 146 therefore end the flashing operation (phase 5 of FIG. 11). The user thus knows that he can modify the digit of the counter of the hour display, which is indicated by their flashing.

The user says UN (IST = 1). The circuit D provides a signal MOT corresponding to the selected reference and a pulse PRET. The signal MOT supplies to the output 50 c of the multiplexer 50, a signal INFO corresponding to this reference. As already explained, only the divider 106 is open. The value contained in the signal INFO is accordingly loaded into the divider 106 . The new content of divider 106 is applied to multiplexer 296 , which selects the input a corresponding to the MONTRE function. This new content is displayed by the display element 146 , which continues to flash. If this display element actually displays UN, the user determines that the clock has correctly understood his command (Phase 6). 5 seconds after the word UN has been pronounced, monostable circuit 54 provides a new pulse. The signal SEQ now has the value 3. As a result, it is the gate 225 of the addressing circuit 160 which outputs a logic level 1 signal with the result that the divider 105 is opened.

At the same time, the signal SEQ is applied to the logic circuits 311 to 316 . Since the signal SEQ has the value 3, it is the circuit 315 that opens and the display element 145 is the only one that blinks (phase 7). The user knows he can enter a new command to change the hour-by-one digit. It is assumed that the user wants to replace the numeral 8 with the numeral 6. He accordingly pronounces the word SIX (IST = 6). The circuit D supplies a signal MOT corresponding to the reference which it has selected to be the one closest to the spoken word SIX and a pulse PRET. The information contained in the signal MOT is converted into a signal INFO, the value of which is input to the divider 105 by the same process as already described for the modification of the hour digits. The display element 145 displays the numeral corresponding to the new content of the divider 105 . The user determines that it is a 7 that appears instead of a 6 (phase 8). It is therefore an error. The user has a 5-second period to correct this digit by repeating the word SIX. This correction option is indicated to the user by the flashing of the hour-one digit. The circuit 7 selects a new reference and generates a signal MOT and a new pulse PRET. The new signal MOT results in a new INFO signal. Since the signal SEQ is still worth 3, it is still the counter 105 that is loaded with the new value of the signal INFO. This new value appears on the display element 145 . If, as in the example of Fig. 11, the digit 6 appears (phase 9), the user may proceed to modify the following numbers, that is, those corresponding to the minutes. To this end, he must wait for the monostable circuit 54 to generate a new pulse with the effect that now the display element 144 will flash in the tens digit of the minutes. Thereafter, the user corrects the other digits using the same procedure. If the user wants to make only a change of the time zone, that is, only wants to change the tens and units of the hours, he will successively flash the display elements 144 to 141 without uttering words. These elements are accordingly not modified (phases 10 and 11).

The command of the REVEIL and TEMPORISATEUR functions is similar, with only the first command being modified. It should be noted, however, that in the command input to the REVEIL function, the cycle is automatically restarted after the fourth numerical information has been input, as already explained in connection with FIG .

It is further understood that the clock could have other functions, such as the time zone function. This function allows the change of the digit indicated by the display elements 146 and 145 . For this purpose, the MODE command may assume a fourth value (eg 3) corresponding to z. B. the pronunciation of the word FUSEAU. The decoder in this case comprises an additional circuit analogous to the circuit 68 of FIG. 4. In this circuit, the gate equivalent to the gate 72 detects the FUSEAU mode, and the gate circuit analogous to the gate 70 detects the value 4. This circuit sets the counter 56 accordingly automatically to zero when the FUSEAU function is commanded and, in addition, the first two numerical information corresponding to the tens digit and the unit digit of the hour that was entered. Furthermore, the part 160 ₁ of the addressing circuit must be slightly modified. Gate 174 must compare the signal MODE not only with 0 (time function) but also with the value corresponding to the function FUSEAU, which in this case is 3.

In the foregoing description, the case has been ins It is clear that the entirety of the information for the Performing the functions of the clock entered by language become. It is of course possible to have a hybrid controller to provide, that is a clock, in which certain commands be entered by language and others by conventional Facilities such as push buttons or Stellkronen.  The following description relates to the case where the Function (MODE) and the triggering or termination of the Function (DEPART, ARRET) controlled by the language while the numerical data regarding this Functions by a push button or any other control device are input, the control pulses generated.

In addition, to simplify the explanation, it has been assumed that the clock in digital form indicates only the hours and minutes. The vocabulary of the clock is limited to MONTRE, REVEIL, TEMPORISATEUR, DEPART and ARRET. The identification of the spoken word is exactly as described above. The changes relate only to the circuits of Fig. 8 and 9. Before these modifications are explained, it should be specified that with the help of a push button at the same time the information with respect to the hour (H) and the hour setting (DH) are entered and that at the same time Minute information (M) and minute information (DM). There is no information about the seconds anymore. As a result, the signal SEQ needs only four different values instead of eight. For example, it has the value 0 for the input of MODE, 1 for the input of DEPART and ARRET, 2 for the input via the pushbutton of DH and H and 3 for the input via the pushbutton of DM and M.

Referring to Fig. 8, the modifications are as follows. The circuit 68 disappears because there is no second information. For this, the circuit 76 remains. The signal INFO provides only one piece of information, namely the information DEPART or ARRET. The counter 56 is set to zero when it reaches the value 4 (only four instructions). Finally, the input 28 a of the circuit 28 , which originally received directly the signal PRET, is now connected to the output of an OR gate 700 , which receives at its inputs the signal PRET and the pulses BP, supplied by the push button which is used to input the numerical data is used. In this way, after entering the data relative to the hour display (DH, H), the user has a delay of 5 seconds to possibly correct this data before entering the minute data (DM, M) via the push button.

Fig. 12 shows the modifications to be made to the circuit of Fig. 9. These modifications are based essentially on the fact that, instead of transmitting commands in the form of the final state they are to assume, to the counters 101 to 126, these commands are now provided in the form of pulses which increment these counters. As already stated, the counters H and DH are controlled in series, as are counters M and DM.

The circuit comprises the addressing circuits 160 ' ₁, 160' ₂ and 160 ' ₃, which are similar to the addressing circuits 160 ₁ to 160 ₃ of Fig. 9. The number of comparators and the number of AND gates is of course reduced because of the reduction in the number of numerical data to be input. The circuit 160 ' ₁, includes the comparators 190, 196 and 195 and the gates 220, 226 and 225 . The outputs 220 b, 226 b and 225 b of these gates provide a signal of logic level 1 when the function MONTRE is commanded or when a DEPART command ARRET is input, if a DH, H command is entered, or when a command DM, M is entered. Similarly, the addressing circuit 160 ' ₂ associated with the function REVEIL, the comparators 200, 205 and 206 and the AND gates 230, 235 and 236 . The outputs 230 b, 235 b and 236 b of these gates provide a logic level 1 signal when the REVEIL mode is commanded and, respectively, when a DEPART, ARRET command is input, when a DH, H command is input, or when a Command DM is entered. The circuit 160 ' ₃ relates to the function TEMPORISATEUR and would have the same structure as before, so that it has not been drawn here for the sake of simplicity of the figure.

The section MONTRE comprises the memory 164 and the counters 103 to 106 . The output 103 d of the counter 103 acts directly on the clock input CK of the counter 104 , and the output 105 d of the counter 105 acts directly on the clock input CK of the counter 106 . The section REVEIL includes the counters 113 to 116 and the memory 166 . The output 113 d of the counter 113 acts directly on the clock input CK of the counter 114 and the output 115 d of the counter 115 acts on the clock input CK of the counter 116 . The TEMPORIZER section has exactly the same structure as the REVEIL section.

For example, in Fig. 12, reference numeral 702 indicates the control member a push button, and 704 denotes a logic circuit which converts the control pulses from the push button 702 into a number of electrical pulses according to the information input via the push button. These pulses BP are combined in an OR circuit 706 with the signal INFO. It should be remembered that this INFO signal contains only the commands DEPART or ARRET. The output of the gate 706 is connected to a line 162 ' , similar to the line 162 of FIG. 9. The line 162' is connected to the control inputs 164b and 166b of the memories 164 and 166 and that of the memory of the TEMPORISATEUR section. The line 162 ' is further connected to one of the two inputs of the AND gates 710 and 712 for the part MONTRE and 714 for the part REVEIL. The second inputs of these gates are respectively connected to the outputs 225 b, 226 b, 235 b and 236 b of the gates, 225, 226, 235 and 236 , respectively. The outputs of gates 710 to 716 apply directly to the clock inputs CK of the counters 103, 105, 113, 115 and the corresponding counter from the part temporisateur. As in the embodiment of Figure 9, gate 170 has an input connected to the output of memory 164 , while its other input receives the clock signal at a frequency of 1/60 Hz because there is no second indication. The connection between the output 104 d of the counter 104 and the clock input CK of the counter 105 via an AND gate 720 , whose control input is connected to the output of the AND gate 225 via the inverter 722 . One finds again the same structure for the part TEMPORISATEUR. The outputs c of the counters and memory are connected to lines 251 to 284 as in Fig. 9. The remainder of the circuit is identical to that of Fig. 9 except, of course, the multiplexer, decoder and display elements associated with the seconds and seconds setting were, which are omitted here.

The operation of this second embodiment of the watch is as follows. The command for the function (Signal MODE) is the same as in the first embodiment. 5 seconds later, the entire display of the display elements starts flashing to allow entry of the DEPART or ARRET information. The signal SEQ has the value 1. The user accordingly issues the command DEPART or ARRET. The signal INFO assumes the value 0 or 1 depending on the command that was actually entered. For example, when the MONTRE function has been commanded, the gate 220 provides a logic signal of level 1 which opens the memory 164 . The value of the signal INFO transmitted via line 162 ' is input to this memory. Depending on the value of the signal, the gate 170 is unlocked, which interrupts the transmission for the 1/60 Hz timing pulses into the totality of the counters 103 through 106 in cascade. Namely, the output of the gate 225 is at level 0, the gate 220 is unlocked, whereby the output 104 d of the counter 104 is applied to the clock input CK of the counter 105 . 5 seconds later, the signal SEQ goes to the value 2, and there is no more signal INFO. The signal SEQ of the value 2 supplies the decoder 135 and 136 with the 2-Hz signal, and the tens digit display elements 145 and 146 and the hour hand unit digit flash to indicate to the user that they can act on the push button 702 to input the numerical information regarding DH and H, respectively. The signal SEQ is still 2 and only the gate 226 carries logic 1 at its output. The pulses from the circuit 704 associated with the pushbutton 702 are supplied via line 162 . They pass through the gate 712 , which is the only one open, and accordingly increment the counters 105 and 106 . The user terminates the action on the push button 702 when the elements 145 and 146 indicate the desired hour information (DH and H). These pulses are also applied to the input of the circuit 28 of FIG. 8 via the OR gate 700 . These pulses are accordingly at the input 54 a of the monostable tilting circuit 54th After entering the last pulse, the user has a delay of five seconds to correct this information.

After elapse of this delay time, the counter 56 is incremented by one unit, and the signal SEQ has the value 3. Thus, it is now the gate 225 that provides only a logic level 1 signal. Accordingly, the gate 710 is opened while the gate 720 is closed. Simultaneously, at the value 3 for the signal SEQ, the decoders 133 and 134 receive the signal at 2 Hz. The display elements 143 and 144 flash for display to the user that can input minute information (DM and M). The user acts on the push button 702 to cause the circuit 704 to supply the number of pulses required to display the desired DM and M information. These pulses pass over line 162 ' and are accordingly applied to the clock input CK of counter 103 via gate 710 , which is open. Even if the number of pulses increments the totality of counters 103 and 104 to a value greater than 60, the pulse that would otherwise be transferred to counter 105 is blocked by gate 720 , which is closed. The hour information (DH and H) is not affected accordingly. 5 seconds after the last pulse has been applied, a new pulse goes to the counter 56 which goes to 0 accordingly. The clock is in position to receive a new command sequence.

The control of the TEMPORISATEUR function is exactly the same. The function REVEIL differs in its control from the function MONTRE only by the fact that no hour pulses are applied to the counters 113 to 116 outside of the control periods. The counters 113 and 114 and 116 can be disconnected and there is no need to provide a gate type 720 isolation gate.

The two embodiments described so far relate exclusively to the numerical display. The invention can of course also be applied in the case that a clock with analog display, for example with pointer display, is present. Fig. 13 shows an embodiment of a clock with indication by hands for the hours and minutes, wherein the entirety of the control information is input by voice. The vocabulary of this watch is accordingly identical to that of the first embodiment.

Since the seconds display (DS and S) is omitted, the signal SEQ can only assume the values 0 to 5.

With respect to the circuit 28 of Figure 8, the changes are in the omission of the circuit 68 , which need not be present because the counter 56 is returned to zero at the sixth pulse applied to its input.

Referring to Fig. 9, the address circuits 160 ₁ to 160 ₃ and the counting circuits for the time are not modified except for the fact that the components with respect to the second information and the ten-second information are omitted. Of course, the AND gates 170 and 172 are supplied with a 1/60 Hz signal. The changes concern that part which lies behind the output c of the time counters 101 to 126 .

Fig. 13 shows the third embodiment of the clock, and one recognizes multiplexers 293 to 296 corresponding to the minute or hour information with their inputs a, b, c, which receive the contents of the time counters, respectively assigned to the functions MONTRE, REVEIL and TEMPORISATEUR. These multiplexers receive the signal MODE at their control input d. They operate in the same way as in the case of FIG. 9. In other words, at their output e, they supply a numerical information in binary form which corresponds to the position which the minute hand ( 293, 294 ) or hour hand ( 295, 296 ) Namely, the positions controlled by the commands entered verbally by the user.

The hands are driven by a stepper motor 750 , which receives pulses from the pulse shaper circuit 752 which generates these pulses from the drive pulses IM which are present at its input. These pulses IM are generated in the following manner. Drive pulse counters 753, 754, 755 and 756 are constituted by dividers connected in series with division ratios corresponding to the values 10, 6, 10 and 2, respectively. These counters correspond to the information DH, H, DM and M. There are, of course, one not shown resetting the dividers 755 and 756 to zero when the divider 755 receives a new pulse while the dividers 756 and 755 indicate 1 and 1, respectively.

Numerical comparators 763-766 compare the contents of a counter 753-756 with the content of the corresponding multiplexer 293-296. Each comparator provides at its output a a logic signal of level 1, if the two numbers present at its input are equal and a signal of level zero in the opposite case. The outputs a of the counters 763 to 766 are connected to the inputs of a NAND gate 770 . The signal CD, which appears at the output of the gate 770, thus has the value zero, when the contents of the entirety of the counter 753-756 is identical to that of the multiplexers 293-296. A signal FM of the frequency of, for example, 64 Hz supplied from the divider stages is applied to one of the inputs of an AND gate 772 . The other input of this gate is connected to the output of the comparator circuit 774 , which compares the value of the signal SEQ with zero. The comparator 774 provides a signal of logic level 1 when the signal SEQ has the value zero and a signal of logic level zero in the other case. The output of the gate 772 is connected to an input of an AND gate 776 whose other input receives the signal CD supplied from the gate 770 . Gate 776 provides the drive pulses IM applied to the input of pulse shaping circuit 752 . The pulses IM are also applied to the clock input CK of the drive pulse counter 753 .

When the signal SEQ is zero, the 64 Hz pulses are applied to the input of the gate 776 . When the signal CD has the value 1, one has actually driving pulses IM, formed from the pulses of the signal at 64 Hz and these pulses are used likewise for incrementing the counters 753-756. It will be readily understood that the contents of the counters 753 to 756 representing the real position of the pointer while the multiplexers 293-296 specify that position, which are intended to achieve these pointers. The power of the motor 750 is stopped as soon as the contents of the counters 753 to 756 are identical to those of the multiplexers 293 to 296 .

This stopping is accomplished by closing gate 776 as soon as the signal CD goes to zero, that is, exactly when there is identity between the contents. It should be noted that the drive pulses are transmitted only when the signal SEQ has the value zero.

It is also clear that after entering each voice information, the user must verify that this information has been correctly understood by the watch and that the same user must be informed of the time when he can enter the following information. In the case of FIG. 9, these two pieces of information were transmitted to the user via the display elements 141 to 146 and 151 to 153 .

In the case of a clock with hands, there are usually no such display elements. In the third embodiment, this information is provided in an acoustic form. As shown in FIG. 13, the clock includes an acoustic circuit 780 that controls the electroacoustic transducer 10 .

Such a circuit is known in the watch art. It is accordingly not necessary to describe it in detail. It contains stored information which makes it possible to generate electrical signals which, after being applied to the loudspeaker 10, provide an acoustic signal corresponding to the word associated with the stored information. The circuit 780 may contain stored n groups of information associated with the addresses, each group of information enabling one word of the vocabulary to be restored. For the Restutionssteuerung a word, it is sufficient to apply to the address input 780 a of the circle the value of the address, associated with the group of information representing the word to be restituted. It is accordingly necessary to ensure that this circuit can restitute the entire vocabulary of the clock. It is also required that it give a certain signal as soon as new data can be entered, for example a GDP. It may be of interest that this circuit also generates the alarm signal when the gate 289 outputs the signal to trigger the audible alarm.

The addresses are generated by a coding circuit 779 which receives at its inputs the signals MODE, SEQ and INFO.

It need not be further explained here that the circuit 779 must control the restitution of one of the words MONTRE, REVEIL and TEMPORISATEUR, depending on the value of the signal MODE, if the signal SEQ has the value zero and independent of the value of the signal INFO; that it must restitute one of the words DEPART and ARRET, depending on the value of the signal INFO, if the signal SEQ has the value 1 and independent of the value of the signal MODE; that it must successively reset one of the digits zero to nine, depending on the value of the signal INFO for the values of the signal SEQ of 2 to 5 and independent of the value of the signal MODE and that he must finally control the output of a BIP sound at each Change the value of the signal SEQ.

The operation of this third embodiment is the following. The user pronounces the name of one of the functions. The value of the signal MODE corresponding to this is applied, inter alia, to the control inputs of the multiplexers 293 to 296 and to an input of the decoder 780 . Since the signal SEQ has the value zero, the speech circuit generates the word according to the information contained in the signal MODE. At the same time, the gate 772 is opened. However, since no new information has been input to the counters 103 to 126 , that is, to the multiplexers 293 to 296 , the signal CD has the value zero. Gate 776 is closed and the engine is not powered. Since the word restituted by the acoustic circuit corresponds to that pronounced by the user, the signal SEQ goes to the value 1 at the end of 5 seconds and the circuit 780 outputs a BIP tone. The user can accordingly enter the second instruction DEPART or ARRET. The signal SEQ has the value 1 and no drive pulse can be applied to the motor 750 . The speech circuit 780 controls the output of the word DEPART or ARRET depending on the value of the INFO signal. If the restituted word is wrong, the user has over 5 seconds to correct the word. At the end of the 5 seconds and without a word being entered, the signal SEQ goes to the value 2. The speech circuit 780 accordingly emits a BIP tone to indicate to the user that the digit can be entered according to the information of the hour. The user speaks that word and the circuit 780 generates the digit corresponding to the value of the INFO signal. At the same time, this value is input to those counters 106, 116 and 126 , respectively, selected by the addressing circuit 160 based on the value of the signal MODE. This value is input via the multiplexer 296 , which accordingly has a value different from that of the counter 756 and the signal CD accordingly has a value 1. Since the signal SEQ is now 2, no drive pulse is supplied to the motor. The hands of the clock do not move accordingly. If the digit reproduced by the circuit 780 is true, the cycle continues until the four numerical data have been input. After entering the fourth digit, the multiplexers 293 through 296 are loaded with the values that the user desires to see displayed by the clock.

As soon as the 5 seconds have elapsed, the SEQ signal returns to zero. At this moment, on the one hand, the acoustic circuit 780 emits a BIP tone to indicate that a new input cycle for instructions may begin while, on the other hand, the gate 772 is being opened because the signal SEQ is zero. Incidentally, since the multiplexers 293 to 296 have contents different from the contents of the drive pulse counters 753 to 756 , the signal CD is 1 and the gate 776 is open. Drive pulses IM are applied to the pulse shaper circuit 752 , which causes the hands to advance rapidly. The pulses are applied to the counters 753 to 756 until the signal CD returns to zero, that is, until there is identity again between the stored value (multiplexer) and the direction indicated by the pointers value (counter 753-756).

In the foregoing description, the acoustic circuit 780 emits the same BIP tone whenever the signal SEQ changes the value. It would be quite possible to construct the decoder 779 and the acoustic circuit 780 such that the acoustic circuit emits an acoustic signal varying with each change in the value of the signal SEQ to more accurately inform the user of the type of command he must enter, for example, the tens of hour digits or the single digits of the minutes.

In the third embodiment, which is A clock with analog display is the user informed by an acoustic signal that the Sprachkodierkreis D has recognized the correct word. In a fourth embodiment, which refers to an analogue Clock refers, this receipt is by the pointer itself  given which a specific position on the dial assume each position is one by language entered information corresponds.

Fig. 14b shows a possibility for such a display. This figure shows the dial 800 , the hour hand 802 and the minute hand 804 . The dial has the usual time- stamped marks, labeled 806 . It also has special references, MONTRE, REVEIL, TEMPORISATEUR, labeled 808, 810 and 812 respectively, and for each of these indications the indications ON or OFF respectively for DEPART and ARRET.

For example, MONTRE is assigned to the 3 o'clock display, MONTRE ON to the 2 o'clock display, MONTRE OFF to the 4 o'clock display; REVEIL is assigned to the 6 o'clock display, REVEIL ON at 5 o'clock, REVEIL OFF at 7 o'clock, etc. Otherwise, the hands are controlled so that the two pointers 802 and 804 overlap each other for information display. This corresponds to abnormal positions of the hands. The attention of the user is accordingly awakened.

In this embodiment, the command input for controlling the time display is all at once, that is, the information DH and H are combined. This means that the vocabulary of the clock also includes the numbers DIX and ONZE. It also follows that the signal SEQ can only assume five values 0 to 4, whereby the value 2 of the input of the hours (DH and H) corresponds to the value 3 of the input of the ten-minutes and the value 4 to the input of the one-minute. For this embodiment, modifications to the circuit of FIG. 8 are to be made in the following manner. The circuit 68 must be omitted and the counter 56 is reset to zero by the fifth pulse applied to its input 56a .

Looking at Fig. 9, the addressing circuits 160 , 160, and 160 are simplified, since each of them now needs to have the comparators for the values 1, 2, 3, and 4 of the signal SEQ.

The totality of the counters 101 to 126 is also modified because only the counters corresponding to DH and H, DM and M remain for each function. The memories 164, 166 and 168 remain. Of course, the display assembly and display control assembly is completely changed and this is shown in detail in Figure 14a.

This assembly comprises three multiplexers 293; 294 ' and 295' . The multiplexer 293 'associated with the hour information receives at its inputs a, b, c the state outputs C of the counters in accordance with the information DH and H for the three functions. Similarly, the multiplexer 294 ' receives at its three inputs a, b, c the state outputs of the counters corresponding to the information DM and the multiplexers 293' , the state outputs of the counters corresponding to the information M. Each multiplexer comprises a fourth input f whose task will be explained later. The time information display is done by means of two pointers, each pointer being driven by its own motor. In Fig. 14a, the motors carry reference numerals 820 (hour hand) and 822 (minute hand), respectively. The motors 820 and 822 are assigned the pulse shaper circuits 824 and 826 , respectively.

The drive pulses to be applied to the motors are generated substantially as explained in the third embodiment. The drive pulses for the motor 820 are generated by the circuit comprising the divisor 830 dividing by 6, the output of which is connected to the clock input of divide-by-12 divider 832 , a comparator 836 having at its inputs the state of the multiplexers 295 ' and 294 'receives, on the one hand, and the state of the divider 830 to 832 on the other hand, and wherein, finally, an aND gate is provided 834th The output 836 a of the comparator 836 provides a comparison signal CD of the logic level 1 when the values applied to the two groups of inputs are identical and the logic level 0 otherwise. This signal CD is applied to an input of the gate 834 via an inverter 835 while the signal at the other input is a 64 Hz signal supplied by the divider stages 4 of the clock. The output of the gate 834 is connected on the one hand to the clock input of the divisor 830 and on the other hand to the input of the pulse shaping circuit 824 .

As already explained, if the state of multiplexer 295 ' and divider 832 are identical, and the states of multiplexer 294' and divider 830 are also identical, signal CD is 1, and gate 834 is disabled , Neither the motor 820 nor the dividers are powered by the 64 Hz signal. On the other hand, if the states are different, then 64 Hz pulses are applied to the dividers and the motor until the states become again identical. Of course, the dividing divider by 12 corresponds to the hour information (DH and H). If the dividing divider were not present, the hour hand applied by the motor 820 would occupy a position which would correspond exactly to the mark for a certain hour (for example, 6 o'clock) without this position being affected by the position of the minute hand. For the representation of the time 6:58 minutes for example the hour hand would stand exactly on the mark for 6 o'clock. The divider 830 dividing by 6 simply has the task of modulating the position of the hour hand as a function of the position of the minute hand. Preferably, the state of the multiplexer 294 'is applied to one of the input groups of the comparator 836 via an AND gate 837 . A comparator 841 compares the value of the signal SEQ with the values 0,. 1 and 2 and provides a signal of logic level 1 only to the signal SEQ is equal to one of these three values. The output of the comparator 841 is connected to the control input of the gate 837 via an inverter 841 ' . Incidentally, the output of the inverter 841 ' acts on the zero reset input 839 of the divider 830 . It follows, accordingly, that for values of the signal SEQ of 0, 1 or 2, the gate 837 is blocked and the divider 830 is reset to zero. In other words, when the MODE and DEPART, ARRET commands are input, the comparator 836 performs the comparison only between the contents of the multiplexer 295 ' and the divider 832 . This allows the hour hand and the minute hand to move to the positions shown in Fig. 14b. Similarly, when inputting the hour information (DH and H), that is, when the signal SEQ is 2, the comparison is made only with respect to the content of the multiplexer 294 ' and the divisor 830 . It follows that the hour hand is only in alignment with the minute time display when the information is given with respect to the ten-digit place.

The control of the minute hand motor 822 is quite similar to that for the motor 820 . One recognizes a divider divide by 6 and divide by 10, labeled 840 and 842 , respectively, and associated with the comparator 846 , which compares the state of the multiplexers 293 ' and 294' and the dividers 840 and 842, respectively. The comparison signal CD 'controls via the inverter 845 a gate 846 corresponding to the gate 834 , thereby enabling the passage of 64 Hz pulses. The motor is energized until the state of dividers 840 and 842 is identical to multiplexers 293 ' and 294' .

As already indicated above, each multiplexer 293 ' and 295' includes a fourth input f which allows the hands to be moved to predetermined positions indicated in Fig. 14b so as to indicate the mode of operation adopted by the clock as well as the health status of this mode (DEPART and ARRET). A decoder 850 receives at its inputs the signal MODE and the signal INFO. This decoder supplies a control signal of a binary numerical signal generator 852 . This generator contains the numerical values which make it possible to bring the hands for hour and minute indication into defined positions according to FIG. 14b as a function of the value of the signals MODE or INFO. The generator 842 has three outputs a, b, c which respectively output the numerical values DH and H, DM and M, respectively. The output a is connected to the output f of the multiplexer 295 ' , the output b to the input of the multiplexer 294' and the output c to the input f of the multiplexer 293 ' . Fig. 14c shows the correspondence table between the value of the input signals of the decoder 850 and the value of the signals appearing at the outputs a, b and c of the generator 852 .

The multiplexers are controlled by a signal V which is applied via line 854 to the control inputs d of the multiplexers. The signal V is generated by a logic circuit 856 . The circuit 856 includes a comparator 858 which generates a logic signal of level 1 when the signal SEQ has the value 0 and 1. The output of the comparator 858 is connected on the one hand to an input of an AND gate 860 and on the other hand to an input of an AND gate 862 via an inverter 864 . The second inputs of gates 860 and 862 are connected to the signal MODE and a signal V ', respectively. This signal V 'is of the same nature as the signal MODE, but with the value 3, for example, while the signal MODE can assume the values 0, 1 and 2. The outputs of gates 860 and 862 are connected to the inputs of an OR gate 866 . The output of gate 866 provides the signal V. It will be readily understood that circuit 856 is a commutator which gives signal V the value of signal V 'when signal SEQ is 0 or 1 and signal V is the value of Signal MODE in the other case.

Depending on the signal 0, 1, 2 or 3 applied to the control input d of a multiplexer, it is the signal present at the input a, b, c or f which is transmitted to the output of the multiplexer. It should be added that the clock also has a circuit, not shown, which detects the changes in the value of the signal SEQ and controls the emission of a BIP-tone by the speaker 10 as soon as such a change is detected.

The operation of the fourth embodiment of Clock is readily apparent from the above explanation.

The user issues the first function command. The circuit 28 supplies a signal MODE, the value of which depends on 0 to 2 of the word that has recognized the decoding circuit and a signal SEQ with the value 0. The signal MODE is applied to the input of the decoder circuit 850 . The outputs a, b and c of the generator 852 apply to the inputs f of the multiplexers the numerical values corresponding to the detected MODE as shown in the table of Fig. 14c. Since the signal SEQ has the value 0, the gate 837 is disabled and the divider 830 is at 0, while the signal V has the value 3. Accordingly, the numerical values at the inputs f of the multiplexers are transferred to the groups of inputs of the comparators 836 and 846 . The comparators determine that there is no coincidence, and drive pulses are applied to the motors 820 and 822 until coincidence occurs again. The pointers accordingly assume the positions shown in Fig. 14b, corresponding to the function recognized by the coding circuit of the watch. The user can thus verify that the clock has understood his command correctly. He has five seconds to make a possible correction. At the end of the 5 seconds, the speaker 10 emits a BIP tone to indicate to the user that he can enter the DEPART or ARRET command. Thus, the signal SEQ now has the value 1 and the function is similar to that which has been described. The difference lies in the fact that the two hands will occupy those positions shown in Fig. 14b which correspond to the combination of the value of the signal MODE and the detected value of the signal INFO. At the end of 5 seconds, a second BIP tone indicates to the user that he can input the hour information (DH and H). The signal SEQ thus has the value 2. It will accordingly be the signal MODE which is now applied to the control input d of the multiplexers and the gate 837 is disabled while the divider 830 is set to zero. The signal INFO assumes a value corresponding to the number of hours recognized by the watch. This value is loaded into the multiplexer 295 ' . The comparator 836 determines if there is a difference between the states of the multiplexer 295 and the divider 832 . Pulses of 64 Hz are then applied to the motor 820 and dividers 830 and 832 until the comparator detects identity. The hour hand will now take a position corresponding to the value of the INFO signal. The user can thus check whether the clock has correctly understood the command given to it. It has a delay time of 5 seconds to enter a possible correction.

Finally, the user enters the command for the tens digit of the minutes (DM). The signal SEQ is equal to the value 3. The signal V is therefore equal to the signal MODE and the gate 837 is no longer locked, just as the divisor 830 is reset to zero. The value of the signal INFO appears at the outputs of the multiplexer 294 ' . The comparators 836 and 846 accordingly detect that their two groups of inputs are at different values. The gates 834 and 844 are disabled and the drive pulses are applied to both motors and to two groups of dividers. With respect to the hour hand (motor 820 ), the 64 Hz pulses are applied until dividers 832 and 830 have the same content as multiplexers 294 ' and 295' .

There is accordingly a certain offset of the hour hand to account for the number of minutes that has been commanded. With respect to the motor 822 , it receives pulses until the contents of the multiplexer 294 ' and the divider 840 are identical. Accordingly, the minute hand arrives in a position corresponding to the correct information of the minute-ten place, but information of the minute-setting, which is probably wrong, since it is the information corresponding to the previous display information.

Finally, the user inputs the information regarding the minute slot that appears on the multiplexer 293 ' . The gate 844 is accordingly unlocked and pulses are applied to the divider 842 and the motor 822 . If the information originally contained in counter 842 is less than the minute instruction, only counter 842 is incremented and the minute hand moves a fraction of a 10 minute portion. If, on the other hand, this command is less than the original content of divider 842 , the minute hand will go through a complete dial revolution minus the difference between the given command and the original state.

It should be noted that in this embodiment the movement of the hands controls after entering each time instruction. This makes it possible for the user to use two motors to control separately. Even in the worst case namely, there is a maximum of 59 pulses of the 64-Hz signal counting. This takes about one second accordingly.

The person skilled in the art will understand that the "watch" part can be replaced by other actuating means. For example, part B could include a plurality of stepper motors for effecting the displacement of movable elements of the device. The verbal commands correspond to the number of the motor to be operated in a desired direction of rotation and the number of steps to be performed. More specifically, the signals MODE, INFO and SEQ appear at the outputs of the circuit 28 , optionally for controlling other actuators. The values of the signal MODE are representative of the number of the actuator. The values of the signal INFO are representative of the states MARCHE or ARRET of the actuators and the numerical information for the determination of the number of steps. The values of the signal SEQ provide the meaning of the input information.

It follows accordingly from the entire preceding Explanation that the control system according to the invention it allows, in very considerable form, the control of various functions of the device in the example of the Simplify clock, as well as entering the appropriate Dates. It is clear that thanks to the direct connection between the different words of the vocabulary of the Device and the command to transmit to the device all memory efforts become virtually superfluous, what the Use of such a device makes it much more attractive. It should be added that this tax system works just as well for controlling part of the functions of the device as for the control of all these functions. Finally, the device can give the user the command from the user the device has been understood, either in visual form acknowledge (numeric or analog display or relocations of parts of the device) or in acoustic form.

It should also be added that the functions realized by the circuits of Figs. 8, 9 (9a and 9b), 12, 13 and 14a could also be realized by the structure of Fig. 2, either by the microprocessor through a group of appropriate programs would be completed or by adding a second microprocessor, which is designed so that it contains only the programs corresponding to these functions.

In the foregoing description, as well as used in the drawing figures, French words, because it is based on their meaning in the present Connection does not matter. Nevertheless, below a glossary containing, where appropriate, the Understanding will be easier, if you look at the literal meaning of the commands, etc. visualized:

INIT - Start, start WORD - Word STANDARD - Standard, standard BEST - maximum similarity CORR - Correction MOT - Word FASHION - Mode, operating mode INFO - Information SEQ - Sequence, sequence ARRET - Stop, termination DEPART - Start, start MONTRE - Time display REVEIL - alarm, alarm temporisateur - Time interval, short-term measurement FUSEAU - Time zone (change) MOT PRONONC' - Spoken word AFFICHAGE - Display U.N. - one SIX Six FONCTIONS - Functions

Claims (9)

1. Voice-controlled device for the execution of a plurality of functions, with

• an electroacoustic transducer ( 12, 14 ) for converting a word spoken by the user of the device, which belongs to a given vocabulary, into an analog signal (S '),
• a coding circuit ( 16 ) for coding this signal (S '), comprising:
  • ⚫ circuits ( 30 ₁- 30 ₇) for filtering the analog signal in a plurality of band-pass filters of different frequencies to produce a plurality of filtered analog signals (B₁-B₇),
  • ⚫ circuits ( 32 ₁- 32 ₇) for sampling the filtered analogue signals,
  • ⚫ circuits ( 34 ₁- 34 ₇) to set a threshold, and
  • ⚫ Circuits for comparing each sample (U₁-U₇) of each filtered signal with the threshold and assigning a first digital value to each sample when a signal correlated to the sample has an amplitude exceeding the threshold, or a second digital value in the opposite case the sum of the digital values (U₁-U₇) with respect to the samples associated with the same analog signal representing the coded digital signal (T),
• - On the coded digital signal responsive circuits for generating a control signal (P), and
• Actuating means ( 8 ) responsive to the control signal for performing the respective functions,

marked by

• - circuits ( 20 ) for storing in coded form all words of the given vocabulary as references, each reference corresponding to a command for performing at least certain functions of the device,
• - Circuits ( 22 ) for comparing the coded digital signal with at least a part of the references and for selecting the comparison frequency which is most similar to the coded digital signal,
• - Circuits ( 8, 11 ) for informing the user of the selected reference in dependence thereon,
• - Circuits ( 28 ) for converting the selected reference into the control signal (P),
• - wherein the coding circuit ( 18 ) further comprises a first circuit ( 620 ) for sequentially detecting an isolated sampling pattern having said second digital value and included by two sampling patterns having the first digital value in each filtered signal and associating the first one Digital value for that isolated sample, and a second circuit for sequentially capturing an isolated sample with the first digital value in each filtered signal enclosed by two samples having the second digital value and assigning the second digital value to that isolated sample ,

2. Apparatus according to claim 1, characterized in that the coding circuit ( 16 ) further circuits ( 622, 624, 626, 636, 638, 640 ) including circuits ( 622, 624 ) for sequentially comparing the digital value of each filtered signal at a given Sampling time with the value of the filtered signals at the previous sampling time and generating a transition signal whenever the comparing circuits ( 622, 624 ) detect a difference, circuits ( 636, 638 ) for counting the number of sampling times after generating a transition signal without a new one Transient signal, and circuits ( 624, 638, 640 ) for suppressing the sampling patterns of the filtered signals after that number has reached a predetermined value and until another transient signal occurs, the entirety of the retained digital values of the sampling patterns associated with the same analog signal forming the digital signal. 3. Apparatus according to claim 2, characterized in that it comprises circuits ( 628 ) for storing only the retained sampling pattern of the filtered signals, associated with the same sampling time, when the sampling patterns differ in their entirety from those of the previous sampling time, and for assigning an information element to each stored sample group representing the position of the stored sample group according to the chronological order of the preserved sample groups. 4. Apparatus according to claim 1, 2 or 3, wherein the execution of each function requires the input of a command cycle with at least one command for the selection of one of these functions and at least two digital information commands, characterized in that the reference memory circuits ( 20 ) for storing also the the references assigned to the function selection command and the digital information commands, and that the conversion circuits ( 28 ) comprise:

• Circuits for converting each selected reference into a digital signal in binary form and
• - Circuits ( 56, 68, 76 ) for assigning a signal to each digital signal in binary form, which is representative of the position of the command corresponding to the signal associated with the execution of the function in question in the cycle.

5. Apparatus according to claim 4, characterized in that the allocation circuits comprise:

• Circuits for generating a start pulse (PRET) in synchronism with each selected reference,
• a circuit ( 54 ) for receiving the start pulses and for supplying a stepping pulse if no start pulse has been applied to the circuit in a given period of time,
• - Circuits ( 56 ) for counting the start pulses and for supplying the continuation signal whose digital value is equal to the count of the counting circuits, and
• a circuit ( 68 ) for resetting the counter circuits ( 56 ) to zero when the number of applied pulses equals the total number of instructions in a cycle.

6. Apparatus according to claim 5, wherein the vocabulary comprises function selection commands (MODE), commands (DEPART, ARRET) for starting or stopping the selected function, and at least two commands (INFO) relating to the digital information for performing at least certain functions of the device, characterized in that the commands of one cycle are input in a predetermined order such that each command corresponds to a given value of the step-up signal in ascending order, and the conversion circuits ( 28 ) further comprise circuits ( 52 ) for storing the value of the digital signal in binary form if the progress signal (SEQ) has the value corresponding to the input of a function selection command, whereby a mode control signal (MODE) is obtained, and circuits ( 50 ) for generating an information control signal (INFO) if the progress signal has a different value. Apparatus according to any one of claims 1 to 6, characterized in that the information circuits comprise display means ( 141-146, 151-153, 802-812 ) for displaying at least part of the words of the vocabulary. 8. Apparatus according to any one of claims 1 to 7, characterized in that the information circuits comprise a sound generator ( 780, 10 ) whose output signal is representative of at least a part of the words of the vocabulary.