DE3224401C1 - Digital messaging system - Google Patents

Abstract

The invention relates to a digital message transmitter and digital message receiver. According to the invention, a digital message transmission channel 2 with a slow data rate is added to a frequency-shift keyed FSK message transmission network 1 with two frequencies, which can be operated independently and does not influence the primary message transmission processes. The data channel for slow data operates at a transmission rate of 1 baud, whereby a frequency shift of 1 Hz is applied to both tones of the primary message transmission. In the transmitter, a reference frequency signal 3 is fed to a frequency synthesizer 7-10, 15 which generates the four required frequencies and supplies the necessary signals for timing gates 13, 14 which ensure that the slow data is added to the primary data in phase coherence. The corresponding receiver comprises a receiver oscillator 21 which is tuned to one of the two primary frequencies. After demodulation (16-19), the received signals and the signal generated on the receiver side are compared in a phase comparator 20 and then filtered in a filter in order to separate the two message transmission channels 24, 25 from one another.

Description

The invention relates to long wave and long wave Message systems (VLF and LF message systems) that Include transmitter and receiver, and in particular one Channel for low data rates for operation with ent speaking frequencies.

The VLF and LF frequency bands of the radio frequencies cover the range of 3-300 kHz. These frequencies are because of their stable and relatively predictable Spread for message transmission over wide Ent distances and used for navigation. These frequencies  also represent the lowest frequencies without Antennas with huge dimensions can still be transmitted can. For example, the one working at 16 kHz Transmitter rugby an antenna that consists of several masts stands, which are each 256 m high.

A common method of using data transfer VLF and LF transmitters is frequency shift keying (FSK) of two sound frequencies. The carrier is between two frequencies, usually a distance of 50 Hz, switched, with a frequency one Mark and the other frequency be a space draws.

This procedure, however, was white then the need for long-term operability distances, especially when used for the night Straightening with submersible.

DE 25 29 386 A1 describes a method for the additional transmission of Data, telecontrol signals and the like via an FM stereo broadcast transmitter knows that works with multiple modulation and one with a multiplex signal a suppressed subcarrier that is not for stereo decoding is needed, added with a small amplitude and with additionally to over carrying signals is modulated, this second modulation by means of phases reverse modulation or another modulation method.

DE 25 14 359 A1 also describes a method and a circuit arrangement for the transmission of service information with delta modulated or Similar radio links are known where the frequency of a transmitter in a digital information transmission system simultaneously and under Use of different types of modulation on the one hand with an actual Lich useful signal and on the other hand with an additional service signal mo is dulated, the uncoded service signal using frequency modulation is modulated onto the carrier frequency and then the The modulated carrier frequency thus obtained is phase-modulated with the useful signal becomes.

From US 41 21 056 A is also a digital frequency division multiplex system be knows that allows the transmission of multiple signals, serial one running signals a first and at the same time the system clock a two ten sinusoidal sound-frequency carriers, each with frequency shift keying modulate and the resulting modulated carriers linear with each other be combined.

In contrast, the invention has for its object a digital Message transmission system with digital news transmitter and digital to create message receivers that have a narrow-band second channel with a slow data rate, which is necessary to achieve a larger night directional transmission range and without influencing the conventional VLF or LF operation can be operated.

The task is solved according to the requirements.

According to a first aspect, the invention provides a Digital news transmitter with a device for coding  tion or encryption of a first signal under Ver using two discrete frequencies for transmission with a first rate, a device for coding a second signal for transmission with a second, long sameren rate, the ratio of the second rates is an integer, and a device for combination of the first and second signals under phase coherence, whereby at least one of the two discrete frequencies the first signal is modulated by the second signal.

This way, when adding a second one Channel for slow data to a conventional message channel the narrower bandwidth of the second channel an expansion of the range or an increase in range same transmitted power. When using a conventional 50/75 baud FSK system for messaging Exchange with submarines is also added add a channel for slow data the depths wearing improved. Preferably both are discrete Frequencies modulated with the second signal. Hereby become the phase coherence requirements of VLF transmitters fulfilled, which also means that the second signal is available at all times compared to the present rend 50% of the time if only one of the two discre ten frequencies is modulated.

The modulation of the two discrete frequencies by preferably includes the second channel for slow data a frequency shift of both discrete frequencies. According to an alternative embodiment, the module tion include a phase shift.

The first signal is advantageously frequency-converted, where one of the discrete frequencies is a mark and the  other frequency a space in the encoded first Represent signal and the second signal a modulation of the first signal in such a way that a mark by changing the two discrete fre sequences is shown. In this way there are four frequencies generated by the transmitter. Preferably a single reference frequency source for generating the Frequencies for transmitting the two signals and for Generation of switching signals for coherent modulation used.

According to a favorable embodiment, the Reference frequency for controlling two bistable Circuits at the relevant frequencies of the data transmission of the first signal and the second signal used, the outputs of the two bistable Circuits for generating the switching signals be drawn.

The four frequencies are advantageously determined by An connection of the reference frequency to a phase controller (PLL), Connection of the output of the phase controller to a program adjustable divider and selectable programming of the divider to deliver a suitable frequency of the four frequencies generated. According to a preferred embodiment, the first signal at 50 baud and the second, slow data signal transmitted at 1 baud.

According to a second aspect, the invention relates to a message recipient to receive a first, with a first rate or speed on two discrete Frequencies transmitted signal and a second signal, that as a second modulation of the first signal with slower Rate is transferred; the receiver according to the invention  summarizes circuit devices for detection or demodu lation of the transmitted signals, a device for Generation of an electrical output signal at a of the two discrete frequencies, a comparator direction for comparing the detected signals with the generated signal and to generate a difference Output signal and a filter device for separation of the first and second signals from the differential output signal.

The detection or demodulation device is in front preferably a high-frequency amplifier (RF amplifier), which is a bandpass filter to improve sensitivity speed of the receiver.

The received signals and the generated signal who which is preferably compared in a phase comparator. The RF amplifier also advantageously includes a Be limiter to reduce amplitude sensitivity Recipient.

The invention is based on Ausfüh approximately examples with reference to the drawing he purifies; show it:

Fig. 1 is a block diagram of a transmitter according to the invention;

FIG. 2 is a block diagram of a receiver according to the invention;

FIGS. 3 and 4 (i) -4 (iii) detailed circuits of the transmitter of FIG. 1 and

Fig. 5-7: detailed circuits of the receiver of Fig. 2nd

With a typical frequency shift keying modulation system (FSK system), the transmitted signal is between a first tone (A tone) and a second tone (Z tone) switched. It is necessary that the shawl tion from one tone to another takes place in phase so that no large switching or transient currents and voltages are generated in the output circuits of the transmitter. This happens by ensuring that the length each bit is an exactly integer number of vibrations periods. With the rugby FSK system, for example the A-tone 16 kHz, the Z-tone 15 950 Hz and the bits length of each bit 20 ms corresponding to 320 oscillation period those of the A tone or 319 oscillation periods of the Z tone, the data transfer rate corresponding to 50 baud wearing.

In the block diagram of the transmitter according to the invention shown in Fig. 1, a first, frequency-shift keyed coded message signal with a data rate of 50 baud is led to an input 1 to a transmitter, so as to switch between the A-tone and the Z-tone as in to specify conventional FSK transmission signals. A second coded signal for transmission at a slow data rate is at an input 2 and generates a shift of 1 Hz in both components of the first frequency-shift keyed FSK signal. The input for the slow data rate is switched once per second, which corresponds to a data rate of 1 baud. A programmable frequency synthesizer is used as a frequency generator to generate the required frequencies of 16000 Hz (A-Ton), 16001 Hz, 15950 Hz (Z-Ton) and 15951 Hz. A 16 kHz standard signal 3 is connected to a 1:32 divider circuit 5 via an input buffer 4 . The 500 Hz output 6 is fed as an input to a PLL circuit 7 . The output of the PLL circuit 7 is amplified by an amplifier 8 and is connected to a 1: n divider circuit 9 . The n: n divider circuit 9 controls the frequency of the phase locked loop of the PLL circuit 7 in such a way that the output signal after passing through a 1: 500 divider circuit 10 is selectively equal to one of the four required frequencies. The 500 Hz signal at output 6 passes through a 1:10 divider circuit 11 and a 1:50 divider circuit 12 and supplies a 50 Hz control signal for a timing gate 13 for input 1 for the FSK data or a 1 -Hz control signal for a timing gate 14 for input 2 for the slow data. The FSK signal and the slow data signal are thus synchronized with the 16 kHz frequency standard by the corresponding timing gates. These two synchronized signals pass through a divider control circuit 15 to the 1: n divider circuit 9 , so that the corresponding de desired frequency arises at the signal output of the PLL circuit 7 .

In FIG. 2, a receiver is shown for demodulation of the transmitted signal. A signal received by the antenna 16 passes through an adjustable attenuator 17 , which allows an attenuation of up to 40 dB. The signal is then amplified by an RF amplifier 18 , which comprises a sensitive amplifier with a FET input in the first stage and a amplifier and limiter in the second stage. A bandpass filter 19 can be switched on between the first and the second amplifier stage of the RF amplifier 18 . The bandpass filter 19 is designed such that it can be tuned over a frequency range of 14.5-20 kHz and its Q value (quality factor) can be set. A Q value of 200 turned out to be favorable. The output of the RF amplifier 18 is connected to an input of a phase comparator 20 . A frequency synthesizer 21 is further connected to a second input of the phase comparator 20 , whereby a frequency standard can be compared with the received RF signal. The frequency synthesizer 21 delivers an output signal of 16 kHz, ie the same fundamental frequency as the transmitter, which is compared with the received RF signal in the phase comparator 20 . The phase comparator 20 provides a square wave output at the total frequency of the two inputs. The mark / space ratio of the square wave varies according to the phase relationship. The square wave output is filtered by a filter circuit 22 which has three outputs: an unfiltered output 23 , a low-pass output 24 filtered at approximately 100 Hz and an output 25 filtered at approximately 1 Hz. In this way, the conventional 50 baud signal is present at the low-pass output 24 , while the signal with a low data rate of 1 baud is available at the output 25 .

In FIGS. 3 and 4 (i) -4 (iii) are detailed scarf obligations of the transmitter of FIG. 1 where mean like numerals indicate like components and the carrying bushes af for clarity, the break points in the circuits call. The circuit blocks shown in these figures correspond to commercially available integrated circuits. The sinusoidal 16 kHz reference signal present at input 3 arrives at an input buffer circuit 4 comprising a Schmitt trigger, which has an external time setting capacitor 26 of 22 nF. The Schmitt trigger converts the reference signal arriving at the input into a digital output, which is fed to the 1:32 divider circuit 5 . The division he follows by four 1: 2 divider stages in the circuit 27 and a further 1: 2 division in the circuit 28 . The 500 Hz signal at output 6 serves as input 29 for generating the four frequencies required for the FSK signals and the signals with a slow data rate and for controlling the timing gates for synchronizing the signals. The 50 Hz timing signal 30 is obtained from the 500 Hz signal as in FIG. 1 by the 1:10 divider circuit (decade counter) 11 and, by further division by 50 by the decade counters 31 and 32, gives the 1 Hz Timing signal 33 . The 50 Hz timing signal 30 passes via a Schmitt trigger 34 to a first input 35 of a JK flip-flop in an integrated circuit 36 which contains two JK flip-flops. An external resistor 37 and a capacitor 38 , which are connected to the Schmitt trigger 34 , are selected so that there is an output pulse length that is narrow compared to the pulse length of the 1 Hz timing signal 33 . The 1 Hz timing signal 33 arrives at a second input 39 of the second JK flip-flop of the integrated circuit 36 .

The two flip-flops are designed so that they oscillate at 50 and 1 Hz. The 50 baud signal and its complement pass from input 1 to inputs 40 and 41 of circuit 36 after amplification and signal shaping by an amplifier 42 . An inverter 43 he generates the complement signal at the input 41st The slow data signal passes from input 2 via a switch 44 to input 45 of circuit 36 . An inverter 46 passes the complement of the slow data signal to another input 47 of circuit 36 . At the outputs 48 to 50 of the flip-flop circuit 36 , program output signals are generated which are provided for the programmable divider in order to generate the corresponding frequencies for transmission, as will be explained later in detail.

LEDs 51-53 are connected to the outputs 48-50 ; at the output 55 , a light-emitting diode 54 is connected to enable monitoring of the 50 baud signals and the signals with a slower data rate.

The two flip-flops in the circuit 36 accordingly change the signals at the outputs 48-50 as a function of the 50 baud and 1 baud input signals for slow data, the output changes being synchronized as a function of the timing signals 33 and 35 . The marks and spaces in the 50 baud signal are represented by the LEDs 53 and 52 , while the LEDs 51 and 54 indicate marks and spaces of the slow data.

Operation of the timing gates and control of the programmable divider are based on the standing table understandable in which the binary numbers are shown, which are the programmable divider for the required output frequencies for a given Input frequency needs. The columns represent each the required zero or one state of an output of the divisor to one of the numbers in the first column to achieve given frequencies. The entrances where no switch to switch between the four frequencies status change is required, ie those in the Groups E and C are for the value zero with 0 V and for a one connected with +5 V.

A or Ao changes to Z or Zo by changing the state of the inputs in the groups D and B in their complement. It happens in a similar way the change from A or Z to Ao or Zo by change the state of the input in group A of O in FIG. 1.  

To synchronize the timing pulses for the frequency changes, the 1 Hz and 50 Hz timing signals 33 and 35 are used to control the timing of the two JK flip-flops in the integrated circuit 36 , as explained above. One JK flip-flop is clocked for switching from A to Z or Ao in Zo at 50 Hz, the other JK flip-flop for changing A to Ao or Z in Zo is clocked at 1 Hz. The integrated circuit 36 has complementary outputs Q and Q from the flip-flops; accordingly, the output Q of one flip-flop (output 49 ) is connected to 2 ¹ 2 ² 2 ³ 2 ⁶ and Q (output 50 ) to 2 ⁷ , while Q (output 48 ) of the other flip-flop is connected to 2 ⁰ . The switching direction is controlled by specifying the J and K inputs of the flip-flops. If input K is held high and input J is held low, output Q will go to zero after clocking and vice versa. In this way, the data can be fed to these inputs at any time between the timing pulses; however, the switchover only takes place if clock or timing pulses are received.

The 500 Hz reference signal at input 29 in FIG. 4 is connected via a resistor 56 and a capacitor 57 to a phase comparator input 58 of the PLL integrated circuit 7 . The signal at the output 59 of the PLL circuit 7 is multiplied to approximately 8 MHz, from which the four output frequencies 16000, 16001, 15950 and 15951 can be derived by division by a 1: 500 divider circuit 60 . The PLL circuit 7 is fine-tuned with a trimmer 61 (Beehive trimmer). The gain of the PLL circuit 7 is reduced by a 560 ohm resistor 62 at the connections 63 , 64 for the low-pass filter on the PLL circuit 7 . The output 59 of the PLL circuit 7 passes through a monostable buffer circuit 65 before it reaches the programmable divider 15 and the 1: 500 divider circuit 16 .

The programmable divider 15 comprises four synchronous binary counters 66-69 , which are connected in series. The output signal of the monostable buffer circuit 65 is connected to the clock input 70 of each of the counters 66-69 , which are arranged so that the count by any of these counters is simultaneously a logic one (+5 V) at the enable input (CE input) 71 of the Counters and at the counter input (CI input) 72 required. The two inputs 71 and 72 of the first counter 66 are connected to +5 V, so that the counter counts all clock pulses. For every 16th clock pulse, an output pulse from the counter output (CO) 73 reaches the enable inputs 71 of the following counters 67-69 . The CI input 72 of the second counter 67 is connected to +5 V, so that this counter counts every 16th clock pulse. The CI inputs 72 of the last two counters 68 and 69 are connected to the CO outputs 73 of the previous counters. In this way, the counters 66-69 clock pulses count up to 2 ¹⁶ .

The binary count corresponding to the current counter reading is obtained by taking outputs 74-77 from the four stages of each counter and forwarding them to the relevant first inputs of the four two-input exclusive NOR gates (NOR / OR circuits) integrated in the corresponding ones Circuits 78-81 are included. The second inputs 82-85 of the exclusive NOR gates in each integrated circuit 78-81 are connected to a logic ONE (+5 V) or a logic ZERO (earth). The exclusive NOR gates are wired with an open roller so that their outputs 86-89 , which are all interconnected, are low unless the counter output and the binary program input at inputs 82-85 are the same; in this case, a pulse at common output 90 is applied via an inverter 91 to the reset inputs of counters 66-69 , which then begin to count from ZERO again. The pulse at output 90 is also the 500 Hz signal, which is required to complete the phase control, and via a second inverter 92 and a monostable circuit 93 , which converts the signal into a square wave with the same mark spacing, with the second input 94 of the phase comparator in the PLL circuit 7 connected. The programming signals at the outputs 48-50 of the JK flip-flops of the circuit 36 ( Fig. 3) are connected to the associated inputs 82-85 , whereby the division ratio of the divider 15 can be selectively set to 16000, 16001, 15950 or 15951, respectively depending on whether the outputs 48-50 are high (+5 V) or low (0). The PLL circuit 7 then acts so that it delivers an output signal at output 59 which corresponds to 500 times the division ratio. The signal at the output 95 from the three decade counters 96-98 , which form the 1: 500 divider circuit 60 , is coded at 16000, 16001, 15950 or 15951 Hz, corresponding to the 500 baud FSK input and the input for slow Data. The signal at output 95 is a square wave which is passed through an active low pass filter 99 which provides a sinusoidal output signal which in turn is passed to an emitter follower buffer circuit 100 so as to provide transmitter control. The transmitter output can be picked up as an unbalanced signal at output 101 or as a balanced signal at outputs 102 and 103 by a Balum transformer 104 .

In Figs. 5, 6 and 7 are detailed circuits of a receiver for decoding the 50-baud FSK signals and the signals for slow data shown. After selective attenuation, the received RF signal arrives at input 105 of an RF amplifier. The attenuation level is chosen so that the amplitude-sensitive receiver is not overloaded, which would lead to undesirable results from intermodulation products. The RF amplifier has an FET input stage 106 , which gives a high input impedance. The output from the FET input stage 106 is connected via an NPN transistor amplifier 107 to the output 108 of the first stage of the RF amplifier. The first stage has a voltage gain of over 200, the circuit values being chosen so that the operation in the VLF band is optimized. A bandpass filter 109 , which can be tuned, for example, in the range of 14.5-20 kHz, can be connected to the output 108 via a switch in order to improve the noise reduction of the receiver. The output 108 is connected to the inverting input 110 of an operational amplifier 111 without or with bandpass filtering.

The output of the operational amplifier 111 is connected via a potentiometer to the non-inverting input, whose adjustable wiper is connected to a voltage source of -12 V in order to be able to set the amplifier's zero level. The output of the operational amplifier 111 is limited by connection to a first input 113 of a comparator 114 , where the second input 115 is connected to a potentiometer 116 for setting the comparator threshold value. The output 117 of the comparator 114 carries a square wave signal when actuated by the operational amplifier 111 .

The amplified and limited received RF signal is compared in a coherent system with the output of a receiver oscillator of the same fundamental frequency as the transmitter, ie 16 kHz. In FIG. 6, a frequency synthesizer is shown for generating the receiver-side 16-kHz standard frequency, which is derived from a 1-MHz source. A 1 MHz signal from a reference frequency source, which is available for example in submarines, is connected to the input 118 . The input signal is buffered by a Schmitt trigger 119 and then divided by 1000 by three decade counters 120-122 , producing a 1 kHz signal. The 1 kHz signal reaches the reference input 123 of the phase comparator of an integrated PLL circuit 124 . When the PLL circuit 124 is disabled, the internal voltage controlled oscillator operates at 32 kHz. The output 125 of the PLL circuit 124 is divided by 2 and thus gives the required 16 kHz reference signal at the output 126 of a binary divider circuit 127 , which then results in a 1 kHz signal at the output 128 by division by 16, which corresponds to the second Phase comparator input 129 of the PLL circuit 124 is connected.

The RF signal input 117 and the input 126 for the 16 kHz reference signal are mixed in the phase comparator section of a PLL circuit 130 shown in FIG. 7. The output 131 of the PLL circuit 130 is a square wave with a variable mark / space ratio. This output signal is then integrated into a resulting signal that is proportional to the phase of the received signal.

The PLL circuit 130 has three outputs 132-134 . The first output 132 supplies the 1-baud signal with the slow data. The output 131 is connected to an active low-pass filter 135 , which is designed so that only the 1 Hz signal with the slow data passes through. The output of the low pass filter 135 is connected to the 1 Hz output 132 via a voltage follower buffer circuit 136 . The output 131 of the PLL circuit 130 is also connected to the second output 133 which, after low-pass filtering at approximately 100 Hz with an active low-pass filter 137 and buffering by the voltage follower circuit 138, supplies the 50 baud FSK signal. The third output 134 is used for test purposes and is not filtered and is connected to the output 131 of the PLL circuit 130 via a voltage follower circuit 139 . Another test connection 140 is connected to the buffered output 126 of the 16 kHz frequency synthesizer.

The invention summarizes one to one conventional 50 baud FSK transmission system complemen second channel. The second channel for slow Data is provided, thus expanding range and reach  the corresponding messaging system in considerable measure. Because the timing signals for multiplexing of the two channels and the transmission frequencies all Lich from a single basic transmission frequency the stability of the system depends consequently on the stability of the reference frequency.

Although the invention is above with reference to one Slow data channel described on the Apply 1 Hz modulation to both at the same time Frequencies of the existing FSK channel is based on those skilled in the art can immediately see that the inventive concept explained above also numerous Modifications and further training permits.

For example, by adding a two th channel with a slow data rate of, for example 7.5 Hz to a conventional 75 bit / s telegraph circuit (the same applies for example to 110 bit / s or higher rates) a device for duration transmission of commands or messages or others Purposes to be realized by the one at first Data channel ongoing message traffic is independent.

The second channel can be used instead of frequency modulation also be phase modulated. The two FSK tones can be selected rend transmission of a slow data mark direction by 360 ° and then at the next brand in back forward phase can be shifted by 360 °. This System affects the total number of oscillation periods, that have been transmitted over an extended period Not.

Claims (11)

1. Digital news channels with
a device for coding a message signal and
a device for transmitting the coded signal at a first data rate using transmissions at two discrete frequencies, characterized by
a device for coding a second signal ( 2 ) for transmission at a second, slower data rate, the ratio of the two data rates being an integer, and
a device ( 11-14 ) for combining the two coded signals with phase coherence, whereby at least one of the two transmissions of the first message signal is modulated with discrete frequencies by the second signal. 2. Digital news transmitter according to claim 1, characterized in that the second signal ( 2 ) modulates the two transmissions with two discrete frequencies. 3. Digital news transmitter according to claim 1 or 2, characterized in that the second signal ( 2 ) frequency-modulates the encoded first signal. 4. Digital news transmitter according to claim 3, characterized in that
that the first signal ( 1 ) is converted in frequency,
wherein one of the discrete frequencies is a mark and the other discrete frequency is a space in the encoded first signal and the second signal ( 2 ) is a modulation of the first coded signal such that a mark is represented by an equal change in the two discrete frequencies becomes. 5. Digital message transmitter according to one of claims 1 to 4, characterized in that a single frequency source ( 3 ) is used to generate the frequencies for transmitting the two message signals and for generating switching signals to ensure the phase coherence of the modulation. 6. Digital news transmitter according to claim 5, characterized in that the reference frequency source ( 3 ) for the control of two bistable circuits ( 36 ) with the respective data transmission rates of the first and second news messages signal is used, the outputs of the two bistable circuits ( 36 ) for generation the switching signals serve. 7. Digital news transmitter according to claim 5 or 6, characterized in that the first and the second message signal uses discrete frequency transmissions and the discrete frequencies by connecting the output from the reference frequency source via a phase control circuit (PLL circuit) ( 7 ) with a programmable divider ( 9 ) are generated, which is selectively controlled ( 15 ) in order to generate the appropriate discrete frequencies as an output according to the specification by the switching signals. 8. Digital message receiver for receiving the message signals transmitted by a digital message transmitter according to one of claims 1-7, characterized by
Circuit devices ( 16-18 ) for detecting the first and the second message signal,
a device ( 21 ) for generating an electrical output signal at one of the two discrete frequencies of the first message signal,
comparator means for comparing the detected signals with the generated signal and for generating a differential output signal, and
a filter device ( 22 ) for separating the first and second signals from the differential output signal. 9. Digital message receiver according to claim 8, characterized in that the detection device has a high-frequency amplifier (RF amplifier 18 ) with a bandpass filter ( 19 ) to improve the sensitivity. 10. Digital message receiver according to claim 9, characterized in that the RF amplifier ( 18 ) further comprises a limiter ( 113-116 ) for reducing the amplitude sensitivity of the receiver. 11. Digital message receiver according to one of claims 8-10, characterized in that the comparator device is a phase comparator ( 20 ).