DE3224036A1 - Converter for converting analog into digital signals by means of charge coupled devices (CCD) - Google Patents

Abstract

The invention relates to an analog/digital converter which operates in such a manner that a particular charge quantity is symmetrically divided by means of a charge divider. One of the part-charges is also symmetrically divided in a further charge divider. The other part-charge is compared with the unknown information. The smaller one of the two charges is increased by the one part charge of the second charge divider whereas the other part charge of the second charge divider is supplied to a third one. Now the next comparison is carried out between the said charges. This process is repeated in accordance with the number of bit positions to be weighted. Each electrode, which is contacted by charges used in comparisons contains at least one basic charge at any time.

Description

Converter for converting analog to digital signals by means of charge shifting arrangements (CCD).

The invention relates to a converter for converting analog to Dii, ta signals, for which the respective information - - --mationsladunç means Charge dividers generated reference charge compared in evaluation circuits and, if necessary generated before a next evaluation process by means of the same charge divider Reference charges is enlarged.

In charge transport storage - especially in charge-coupled devices (CCD) - is the charge storage capacity of the unit cell in contrast to the Dynamic MOS RAM memories with a very similar structure are not affected by the sensitivity the evaluation circuit limited downwards; rather, it already arises far above the evaluator sensitivity from the minimum dimensions of the storage electrode lower limit for the charge storage capacity.

The upper limit Q that can be stored in such a unit cell The charge is then several times higher than the detection limit Q of the charge transport storage evaluation circuit.

If it succeeds, at the entrance of a charge transport storage in the Storage elements optionally enter different charge quantities QX (Qo - 'Q = Q), and if it succeeds, these different amounts of charge at the output of the charge transport store to evaluate, can only with the effort for the necessary input and evaluation circuits the information storage capacity of a charge transport store is significantly increased be (; multi-level storage CCD MLS-CCD).

Analog-digital converter by means of CCD and especially from the field of MLS-CCD are already known. DPS 27 04 711 provides a counting method Evaluation of an unknown information load Q 'before: The input bit pattern (a1 a2.. a) correspondingly composed of a maximum of (29 - 1) partial charges Q ' Charge Q is poured into a first potential well, which is the - as small as possible -Has charge storage capacity Q '. When that first pot is filled, one takes care of it small potential gradient so that the remaining charge (Q'X ~ Q ') has another Pot of the charge storage capacity Q 'is reached, etc. Then all (2q - 1) Potential wells read out in parallel and by means of conventional (29 - 1) evaluation circuits checked for filling. An evaluation logic finally generates the bit pattern sought from the pattern of the first m of the (29-1) possible filling indicating evaluator outputs.

The process of gradually filling the potential wells by overflowing Without electrode clocking, this is naturally slow and requires long downtimes the charge transport arrangement. In an application according to US Pat. No. 3,958,210, therefore a larger number of rows of potential wells in parallel from an equally large number filled by output electrodes. These are then evaluated serially while at the same time the output electrodes are refilled serially. Result from this less downtime for the load transport device.

The evaluation method described is only very useful for MLS-CCD memories Conditionally suitable because the following applies to the upper limit of the information load: (29 - 1) - Q '.

The charge storage capacity of the evaluation pots can only go through Reduction of the applied DC voltage potentials can be kept small, what the disturbing influence of possible threshold voltage fluctuations increases.

Furthermore, the measurement by (2q - 1) takes place independently of one another geometrically defined structures. After all, malfunctions can occur that the higher-value potential wells are rarely even reached by charges whose surface states are constantly being emptied (no basic charge operation).

In an application according to US Pat. No. 4,085,459, the size of the up to tetravalent information charge on the extent of the charge reversal of the output diffusion area Three inverters are connected to the diffusion region tied together. The transistors in each inverter have different threshold voltage values.

It is obvious that three inverters make up the output diffusion region load capacitively and that three different, precisely adjustable threshold voltages can only be achieved with great effort.

The digital-to-analog converter described in U.S. Patent 4,087,812 does not reproduce Information charge pending under a refresh electrode in a step-by-step approach. A D / A converter then shows the extent of the charge to be determined in its final value at.

This procedure can evaluate charges that are below the limit value Q is the charge storage capacity of minimal CCD. However, it is time consuming because the individual bit positions are processed one after the other and also the number the time steps for a bit position still from the previous decision is dependent.

A fractional charge generator described in US Pat. No. 4,072,939 Q / 2i is also used to evaluate an information load QX. First, QX compared to Q / 21. If QX) Q2 /, then: a1 = 1, and a load switch increases the Compare charge by adding the 2 next charge fraction to (Q / 21 + Q / 22). If QX <Q / 2, then: a1 = 0, and the information Q / 22 adds the charge switch charge the next charge fraction Q / 22, whereupon (QX + Q / 22) with Q / 21 is compared, after exactly g.

The bit pattern (a1a2 ..... aq) is fixed in time steps.

q Charges below Q (limit value) can be assessed.

The arrangement is therefore suitable for MLS-CCD. There will be one The load is measured, then it is then only divided in a ratio of 1: 1 and postponed depending on the decision. Assessing a load with an accuracy of q bit requires q time steps. A basic charge operation is not possible. That The reference charge is gradually halved by means of an inserted separating electrode, which can very easily lead to asymmetries.

Another analog-to-digital converter is disclosed in U.S. Patents 4,070,667 and 4,145,689 presented according to charge shifting principles. A potential well opened by the analog signal is now filled by itself from a previously completely filled reference electrode. The charge loss of the reference electrode is then counted by adding balanced by m constant charge units Q again. The counting result Finally, m is converted into a bit pattern by means of evaluation logic.

The number m of time steps is information-dependent and can be up to to reach (29 - 1). A direct connection to an MLS-CCD memory is not possible, since charge units of the required size Q '= (Q lower Geometry limit value) are hardly reproducible.

In the application according to US Pat. No. 4,139,910, the same electrode is in which the four-stage charge package for input into an MLS-CCD is produced, used to evaluate the information charge at the output of the charge transport arrangement. The electrode potential of the cell containing the information charge is divided into four Steps increased. A neighboring electrode picks up any charge that may leak out. A connected evaluator recognizes whether there four times, three times, twice or only once Charge is present. An evaluation logic makes up the found in four time steps The result is a two-digit bit pattern.

US Pat. No. 4,136,335 teaches a means of charge transferring assemblies implemented binary search method described. The unknown cargo - in the area from 1/2 to (2q - 1/2) minimum charges Q - passes through a CCD arrangement in q steps, the dimensions of which are reduced by a factor of 2 from step to step. While the Information load Q 'may reach a maximum value of Q (29 - 1/2), is in the first Step checked whether it was actually taken by an electrode of capacitance Q 2q-1 becomes (a1 = 0) or not (a1 = 1). If the latter is true, an amount of charge becomes Q 2q-1 subtracted from Q'X. With a1 = ° Q 'remains unchanged. Then with proceed accordingly for an electrode with capacitance Q 2q-2. The bit pattern becomes read directly from the evaluator outputs after passing through the q levels The method is suitable for pipeline operation. While in the second stage that second bit of the first amount of charge is evaluated, can already in the first stage the first bit of the following amount of charge are recognized, etc. are in a time cycle to the q evaluators the bit values of successive q charges. The gain in speed is obvious: a completely new bit pattern is available for each time step.

However, the method is not suitable for MLS-CCD memories, since it is still the charge fraction Q of the last-digit bit is determined by the minimum electrode area will. Except - - ei> - - - - - - - - - - all subtractions correspondingly afflicted with different scatter in geometrically independent t 1 Electrodes, the edge defects of which have an increasing influence with decreasing electrode size to win. A basic charge operation is not possible.

An application according to US Pat. No. 4,206,446 also uses evaluation stages Potential pots of decreasing size. Because with increasing bit position it always has to smaller amounts of charge can be subtracted. The charge to be evaluated includes the area from 0 to (29 - 1) minimum charges Q. For the evaluation process, parallel (q-1) Loads of information needed. For q> 2, (q-2) of these become input charges successively by subtraction the decisions about the first (q-2) bis positions met. These results are used to charge from the last input exactly one of 2q 2 unifying charge paths a charge amount in the area from 0 to 3 minimum charges Q provide the information about the two contains last digit bits. Two further subtractions of one charge each Q and Logically linked evaluations ultimately result in the last two bit values.

The method is not suitable for MLS-CCD memories because (q-1) times the information load provided must become. The security the rating depends sensitively on the area ratio of different sizes Electrodes 2 off. Since up to 2q 2 subtractions due to charge migration in one time step are carried out using a corresponding number of potential wells, is the operating frequency highly limited. A basic charge operation is not possible.

The object of the present invention is, inter alia, for the output circuit of Multi-Level-Storage-Charge Transport Storage (MLS-CCD) an analog-digital converter to provide the information content of the charge packets stored in the analogue recovered in digital form.

To solve this problem, an analog-to-digital converter is according to the invention designed such that a predetermined charge by means of a first Clock in a first charge divider into a smaller basic charge and a larger one Comparative charge-split and separated between first and second storage electrodes The basic charge is then stored by means of a second cycle from the first storage electrode via a second storage electrode into a third Storage electrode is pushed that at the same time the comparison charge from the second storage electrode by means of a second symmetrical charge divider in two equal partial charges are split and under fourth and fifth storage electrodes is stored separately that then by means of a third clock the reason charge from the third storage electrode in a further intermediate storage electrode is mixed with a partial charge from the fourth storage electrode and as Reference charge in one via a conductive diffusion area with the non-inverting one Receipt of a first Evaluation circuit connected sixth storage electrode is kept ready that at the same time the other partial charge from the fifth storage electrode by means of a third symmetrical charge divider into two equal partial charges is split up and stored separately under seventh and eighth storage electrodes is that at the same time via a further intermediate storage electrode from one with its coupled charge transport storage loop the information charge to be evaluated is taken over and in one via a conductive diffusion area with the inverting one Ninth storage electrode connected to the input of a first evaluation circuit is that then in the pause between the third measure and a fourth Clock the first potential comparison between those with the sixth storage electrode and diffusion regions connected to the ninth storage electrode from the first The evaluation circuit is carried out and the result is given as a display to the outside world, that then during the fourth cycle, the displacement electrodes of the seventh and eighth storage electrodes corresponding to the following intermediate storage electrodes the result of the potential comparison with the potential of the clock or with zero potential are acted upon dass.demnach by means of the fourth measure in preparation for a second potential comparison, the reference charge from the sixth storage electrode in a further intermediate storage electrode either with the one partial charge the seventh storage electrode is mixed or remains unchanged and in any case as a pure reference charge in one via a conductive diffusion area with the non-inverting one Tenth storage electrode connected to the input of a second evaluation circuit held ready that at the same time the partial charge from the seventh storage electrode in the second case by means of a fourth symmetric charge divider into two equal Partial charges are split up and under eleventh and twelfth storage electrodes is stored separately that at the same time the partial charge from the eighth storage electrode either by means of the fourth symmetrical charge divider into two equal partial charges is split up and stored separately under eleventh and twelfth storage electrodes is or unchanged in a further intermediate storage electrode as an additional charge is mixed with the information charge from the ninth storage electrode and as a new information load in one over one. conductive diffusion area with the thirteenth storage electrode connected to the inverting input of a second evaluation circuit is kept ready that at the same time the information charge from the ninth storage electrode remains unchanged in the first case and via the intermediate storage electrode in said thirteenth storage electrode is pushed, and that this process changes accordingly the number of bit positions to be evaluated is repeated progressively.

Only the usual ones are used to operate the relevant CCD arrangements Operating cycles used as they are for e.g.

a 2-phase or a 1-phase CCD are necessary. It can also be graduated Charge quantities are assessed, e.g.

also below the charge storage capacity Q of the unit cells Charge transport storage of minimal dimensions remain.

The arrangement according to the invention is - apart from one in the MLS-CCD application each electrode required once to provide a reference charge QQ - ~ is advantageous not subject to the conditions of minimum geometry as they are in charge transport storage rule yourself.

The procedure, however, is not limited to the processing of minimal charges limited With a correspondingly large design, charges of any size can be used are processed.

No charge subtractions are carried out that would lead to undesired Can lead to scattering and occur only slowly in charge transport arrangements.

Except for a split-off preceding all divisions, one in each Charge transport arrangement required small basic charge QFZ (Fat Zero), which is not precisely defined, but must be reproducible, all subdivisions run advantageously in a ratio of 1: 1, which is achieved by symmetrically arranged CCD channels can be reached easily and precisely. All shifts happen under the influence of the applied clocks in a known way in one direction. Each of information-determined Electrode that is in contact with charges contains at least the basic charge at all times QFZ (complete basic charge operation!).

The translator works in a pipeline process, adding the loads one at a time completely identical - i.e. also geometrically the same size - steps through. The width q of the bit pattern corresponds to the number q processed in each time step Charge quantities. Accordingly, the data rate is (here the product of the clock frequency and width of the bit pattern) is comparatively high.

No reference voltage is required in the analog-digital converter Es is instead exactly once per time step and therefore per charge quantity to be processed a reference charge Qr is provided, the one to be stored in the minimum electrode Charge amount Q can correspond.

The evaluation circuits belonging to the analog-digital converter must be able to detect a voltage difference as they are not destructive corresponds to a charge difference of Q / 2 q + 1 if q is the width of the bit pattern (a1a2 ... aq) is.

Another advantage of the converter described is by wiring from the outside the width q of the bit pattern of one - corresponding to the expansion of the arrangement - To be able to reduce the maximum value step by step. If e.g.

the sensitivity of the evaluation circuit is insufficient or the If the interference level is too high, the necessary sensitivity can be achieved for each bit position that is withdrawn can be reduced by a factor of 2.

In particular, the analog-to-digital converter can be designed in such a way that that he has seven rows of parallel chain-shaped one behind the other Storage electrodes contains that with a bit pattern width of q bits the first, fifth, sixth and seventh rows of (q + 1) storage electrodes and the second to fourth row consists of (q + 2) storage electrodes that the storage electrodes of the odd-numbered rows with a first voltage source which is a DC voltage supplies, and the storage electrodes of the even-numbered rows with a second voltage source, which supplies a clock voltage, are connected to the charges of the storage electrodes of the individual rows via externally controllable displacement electrodes between the storage electrodes of the individual rows lie, corresponding to a predetermined Clock program can be moved to the storage electrodes of the adjacent rows, that each storage electrode of the first row can be influenced by two displacement electrodes is, the respective first displacement electrodes with the first voltage source and the respective second displacement electrodes with the second voltage source are connected that the respective first associated displacement electrodes of the storage electrodes of the first row of the same size displacement channels to the first (q + 1) storage electrodes of the second row produce that the second associated displacement electrodes of the first row charge transfer channels to the last (q + 1) storage electrodes of the second row establish that the q last storage electrodes of the first row also have conductive diffusion areas with floating potential, which with first input node of q evaluation circuits that are connected between storage electrodes the second and third rows also have displacement electrodes, that each displacement electrode has an equally large charge displacement channel between releases the respective adjacent storage electrodes of the second and third row, that the shift electrodes between the first two and the last storage electrodes the second and third row with the second voltage source and the displacement electrodes between the remaining storage electrodes of the second and third row with the non-inverting ones Outputs of the first (q-1) evaluation circuits are connected to the last storage electrode the second row via a displacement electrode connected to the first voltage source is connected, is coupled to a first charge sink that between the third and first shift electrodes are arranged in the fourth row of the storage electrodes, which are connected to the first voltage source, the charge transfer channels of all storage electrodes of the third row to all storage electrodes of the fourth Affect row, with the charge transfer channel between the first two Storage electrodes of these rows is much smaller than between all the others Electrodes, that with the exception of the first two and the last storage electrodes the third row and the first two storage electrodes of the fourth row between the Storage electrodes of these two rows arranged further displacement electrodes are those to the inverting outputs of the first (q-1) evaluator circuits are connected that between the first two storage electrodes of the fourth and fifth row of storage electrodes, a displacement electrode that corresponds to the first Voltage source is connected, with a larger charge transfer channel than between all other storage electrodes lies between the second and third storage electrodes the fourth row and the first two storage electrodes of the fifth row as well Displacement electrodes are arranged, which are connected to the second voltage source are that from the second storage electrode to the penultimate storage electrode the fourth row and from the second storage electrode of the fifth row between the storage electrodes of these rows are shifting electrodes that correspond to the first Voltage source are connected, the charge transfer channels between the corresponding Storage electrodes control that also starting with the fourth storage electrode the fourth and third storage electrodes of the fifth row between the storage electrodes further displacement electrodes are arranged, which are connected to the non-inverting outputs of the first (q-1) evaluator circuits are connected that between the storage electrodes of the fifth and sixth row starting with the third storage electrode of the fifth and the second storage electrode of the sixth row and ending with the last Storage electrode of the fifth and the penultimate storage electrode of the sixth Row displacement electrodes are arranged, which are connected to the inverting outputs of the first (q-1) evaluator circuits are connected to the storage electrodes the sixth row are also associated with displacement electrodes that are associated with the first Voltage source are connected and the Charge channels to the storage electrodes control of the seventh row, the last storage electrode being the sixth row a charge transfer channel to a second charge sink that the storage electrodes the sixth row are assigned further displacement electrodes, which are associated with the second Voltage source are connected, the displacement electrodes of this type charge displacement channels to affect the storage electrodes of the seventh row, and that the storage electrodes the seventh row with the exception of the first storage electrode of this row as well Have conductive diffusion areas with floating potential, which with the second Input nodes of the q evaluation circuits are connected, and that the first storage electrode the seventh row via a displacement electrode connected to the first voltage source is connected to a charge transport storage arrangement which is used to input the Information charge is used, is coupled.

The evaluation circuit can be designed as a flip-flop, its Signal inputs form the gate electrodes of the load transistors, the gate electrodes are designed as "floating belts", which are connected to the "floating diffusion" which are influenced by the information or comparison charges The invention is explained in more detail in the exemplary embodiments according to FIGS. 1 to 4. They show: FIG. 1 the schematic circuit diagram of the analog-digital converter, FIG. 2 an evaluation circuit for the analog-digital converter, Fig.3 the timing diagram for the evaluation circuit, FIG. 4 details of a memory cell with floating gate.

In the following schematic representations the electrodes of the charge transport electrodes shown in symbolic form. Big rectangles mean storage electrodes that can store at least the amount of charge Q. Q is minimal due to the charge storage capacity of a charge transport store Geometry given.

Small rectangles mean displacement electrodes. They give a load transfer path in the direction of the storage electrode connected to it free With externally controllable displacement electrodes the path is released exactly when adjacent storage electrodes and displacement electrodes are simultaneously acted upon with the same potential.

A 1-phase mode of operation is used as a basis for illustration. o means an average DC voltage is a voltage pulse, the values between 0 and around 2o. While 01 is applied, charges under the 1 connected electrodes. If switched off, the charges are over the shift electrodes connected to the storage electrodes connected to pushed. If 1 rises again, the charges from the storage electrodes connected to O become taken over into the storage electrodes connected to 1, if the intermediate ones Shift electrodes are also connected to 1 or at the same time from the outside be applied with an equally large potential. Shift electrodes on Zero potential block the displacement path.

The method is described below using an arrangement according to FIG. As can be seen from the periodic structure of the arrangement, however, the method is not restricted to this bit pattern width (q = 4). A larger bit pattern width can be processed by lengthening the arrangement and a smaller one by shortening it. In addition, each arrangement can also be operated with a width po q which is less than that corresponding to the configuration, in that only the desired permanent-digit bits are taken into account.

From a charge registration level of the usual type, which is not specifically is shown, the storage electrode 10 connected to 1 takes over in a first Switching on the cycle 1 an amount of charge Qr (1) = Q.

If the analog-to-digital converter described here is at the output of a Charge transport storage loop is arranged, at the entrance of which there is a in the Patent application P ....... described digital-to-analog converter is located, Qr corresponding to the shift losses when passing through this storage loop - opposite the input charge of the digital-to-analog converter by means of suitable charge splitting be reduced.

When cycle 1 is switched off, the charge Qr (1) has two paths into the electrodes 11 and 12 connected to it. These displacement paths are designed to be of different widths. Therefore only a fraction of Q (1) 4 Q (1) FZ r (eg QFZ Qr / 8) is transferred to electrode 11 (basic charge), while the main part (1) is pushed into electrode 12. After this first measure Q1, the following balance can be noted: The upper index identifies the order number of the cycle during which the amount of charge was measured, and the lower index on the brackets indicates the electrode under which the charges are located.During the increase to the next-second cycle 01, Q (1) remains unchanged of the electrode 11 taken over into the electrode 23. (1) also goes unchanged from 12 to 20. When switching off 1, Q§) continues unchanged to 25, while the charge Q5) from the electrode 20 flows in equal parts into the electrodes 21 and 22 on completely symmetrical displacement paths.

After the second cycle 1, the following balance can be noted for the charge Qr (1) entered into the arrangement in the first cycle: The charge Qr2) taken over by electrode 10 during this second cycle 1 can be noted - in accordance with what has been described above: During the rise to the third clock 1, Q (z) is taken from the electrode 25 and mixed in the electrode 33 with the charge QS (2) / 2 from the electrode 21, while the other charge Q (2) / 2 is transferred unchanged to the Electrode 30 passes over. At the same time, the electrode 34 takes over the information charge Q to be assessed from the charge transport storage loop connected there, which is only indicated here by its two last storage electrodes 24 and 26 symmetrically on the electrodes 31 and 32 at the same time the charges from 33 pass unchanged to 35 and those from 34 unchanged after 36 then applies: During the clock pause of 1 that now follows, the first evaluation is carried out, which decides on the first-digit bit a (3) (3) of the information load Q (3). For this purpose, conductive areas (floating diffusions) are connected to the charge transport channel under the O-electrodes 35 and 36 and are connected to the input nodes of a first flip-flop circuit FF1. The details of this circuit are explained in detail in FIGS. It is only used here that the circuit FF1 recognizes whether the charge under 36 is greater (a1 = 1) or less (a1 = 0) than that under 35, and that the lines A1 and A1 connected to FF1 during the following cycle 1 their state indicates to the outside whether a1 = 1 or a1 = 0, which tends towards A1 = H, A1 = L or A1 = L, A1 = H z.

After the third cycle 1, the following charges are compared: Electrode 35: Qref1 QFZ + QS / 2 Electrode 36: The difference formation 4 QX-Q ,, f1 Qs / 2 + (2 + i) / 2i 1/2) QXref1 - 5 ((a (3) - 1) / 2 + i = 2 a1 + 5 shows that QX is at least Qs / 25 greater than Qref1 when a1 = 1 and at least QS / 25 less than Qref1 when a1 = 0.

During the next - fourth rise of, the displacement electrodes connected to Al or A1 are acted upon with a potential corresponding to 1 in accordance with this decision, which, depending on the value a1 of the first bit position, increases the reference charge Qref1 by Q5 / 2² (a1 = 1) or an increase in the information charge by the additional charge Qzus2 = Q5 / 22 (a1 = O). The following balance can be written for the status after switching off the fourth cycle 1: In the following clock pause 1, the charges Qref2 in electrode a2 45 and QX + Qzus2 in electrode 46 are compared to determine the second bit position a24): The formation of the difference after the fourth measure, shows that QX + Qzus2 is at least Qs / 25 greater than Qref2 when a2 = 1 and Qs / 25 is less than Qref2 'when a2 = 0.

In the same way, after the fifth and sixth bar 1, the Bit positions a3 and a4 are determined. During the ascent to the sixth measure 1, the Charge Q55 / 24 by means of the clock at A3 or A3 from the electrode 51 or 52 taken over into the electrode 60, but then completely after switching off the cycle 1 moved to electrode 61. A following seventh bar is only necessary to the reference charge Qref4 4 from electrode 65 and the remaining charge QS / 24 from electrode 61 to electrode 73 and the sum of information charge Qx and additional charge plus 4 to take over from electrode 66 to electrode 74, from which they then switch off flow from 1 into the charge sinks 75 and 76, respectively.

After completion of the evaluation process there is no charge with the information content the input charge QX is longer available. To rewrite the information in a Any existing charge transport loops must be attached to the lines A. and A. pending-1 1 the signals are used. It is noteworthy that all Portions of the reference charge Reif4 and the additional charge add4 from one and the same Comparison charge Qr originate and from this - except for the splitting off of QFZ - obtained by symmetrical charge sharing alone. With the necessary difference formations these parts of the load are therefore not burdened by different scattering.

The individual bit positions of the information load Qx were each after bars 01 with ordinal numbers 3 to 6 won what the time sequence when entering the associated charge proportions corresponds if there is at the input of the charge transport storage loop, a digital-to-analog converter described in the patent application is located. After each individual cycle 1 are in each case in the four evaluation circuits FF1 to FF4 four comparisons on four different loads from four different ones Consecutive input charges carried out in parallel in charge transport directions ("Pipe lining").

Suitable as an evaluator for the analog-digital converter described a difference evaluator. FIG. 2 advantageously shows a flip-flop FF with inputs on the states of the load transistors M1 and M2. Such FF evaluators are state of the Technology for CCD memories with reference generation using a dummy CCD.

However, there are some special features in the selection and dimensioning Please note: Since the charges to be compared in the following stages of the Converter are needed again, the evaluation need not be destructive. this is possible by using "floating gates" (FG) or "floating diffusions" (FD).

The timing of the analog-to-digital converter is such that in the Cycle pauses of 1 is evaluated and that the result of this evaluation before completion the pause must be available because the displacement electrodes Ai and A7 (cf. Fig. 1) must be set correctly with increasing cycle.

The period "# 1 on H" during which the electrodes to be sensed contain no charge, is therefore short (Fig. 3).

FG evaluators need precharge transistors during this time must be clocked Such a pre-charging clock is at the usual operating frequencies the CCD memory is difficult to accommodate in the clock program. It is therefore here by means of "floating diffusion" Such a diffusion region FD is possible at low capacitance conductively connected to the storage electrode to be sensed (Fig 4).

When using an FD in conjunction with a flip-flop it is important Make sure that the setting and resetting of the following levels (FF nodes and evaluator output stages) no repercussions on the particularly sensitive because of their small capacity Has FD territories. The circuit shown in Figure 2 meets this requirement. she will operated by the clocks 1 '2' T3 and T5, the timing of which is shown in FIG are. Without a charge, a potential is established at FD under electrode G, which by a threshold voltage below that of electrode G (see Fig. 4). The potential O of the electrode G is advantageously constant at approximately half the clock voltage 01 (approx. 5V) held (1-phase operation). This results in the potential at FD a value of around 1.8 V. When charges below G arrive, this value increases lowered. In order for the connected FF 'to react sufficiently quickly, for the transistors Ml and M2 "normally-on types" can be selected. The exit Ai is a bit more powerful than output A. Dimen-1 1 sioniert, so that an output amplifier is attached to it can be connected (Fig. 2).

These are the special features of the evaluation circuit for the analog-digital converter describe. The rest of the layout of the circuit (Fig. 2) is state of the art.

Fig. 4 shows again a memory cell of the analog-to-digital converter, wherein the memory cells are formed with a floating diffusion region FD. These Diffusion regions are connected to the gate of the load transistors M of the evaluation circuit tied together. In addition to the storage electrode G, which is connected to the first voltage source o is, the two displacement electrodes V1, V2 are also shown, V1 with the first voltage source O and V2 is connected to the second voltage source 1 is. In the analog-to-digital converter, these memory cells are in the first and last Row, as already described, arranged.

8 claims 4 figures L e r s e i t e

Claims (8)

Claims Converter Converter for converting analog to digital signals, in the case of the reference charges generated by means of charge dividers with the respective information charge or with the information charge increased by reference charge parts in evaluation circuits be compared, d u r c h e k e n n n n z e i c h n e-t, that a given Charge (Q r) by means of a first clock (# 1 (1)) in a first charge splitter (10,11,12) divided into a smaller basic charge (QFZ) and a larger comparison charge (QS) and is stored separately under first and second storage electrodes (11, 12), that then by means of a second clock ((2)) the basic charge (QFZ) from the first storage electrode (11) via a further intermediate storage electrode (23) in a third storage electrode (25) is pushed that simultaneously the comparison charge (QS) from the second storage electrode (12) by means of a second symmetrical one Charge divider (20,21,22) is split into two equal partial charges (% / 2)) and is stored separately under fourth and fifth storage electrodes (21,22), that then by means of a third cycle, the basic charge (QFZ) from the third Storage electrode (25) in a further intermediate storage electrode (33) with the a partial charge from the fourth storage electrode (21) is mixed and used as a reference charge (Qref1) in one via a conductive diffusion area with the non-inverting one Input of a first evaluation circuit (FF1) connected sixth storage electrode (35) is kept ready that at the same time the other partial load from the fifth Storage electrode (22) by means of a third symmetrical charge storage (30,31,32) is split into two equal partial charges (Q / 4) and under seventh and respect, think highly of Storage electrodes (31,32) is stored separately that at the same time via a further intermediate storage electrode (34) from a charge transport storage loop coupled to it (24,26) the information load (D) to be assessed is taken over and in an over a conductive diffusion region with the inverting input of a first evaluation circuit (FF1) connected ninth storage electrode (36) is kept ready r that then in the pause between the third measure ((3)) and a fourth measure (0 (4)) the first potential comparison between those with the sixth storage electrode (35) and the ninth storage electrode (36) connected diffusion regions from the first Evaluation circuit (FF1) is carried out and the result is issued to the outside world as a display is that then during the fourth clock () the shift electrodes of the seventh and eighth storage electrodes (31,32) to the following intermediate storage electrodes (43,40; 40,44) corresponding to the result of the potential comparison with the potential of the clock or applied to zero potential (4) that accordingly by means of the fourth cycle ((4)) in preparation for a second potential comparison, the reference charge (Qref1) from the sixth storage electrode (35) in a further intermediate storage electrode (43) either mixed with a partial charge from the seventh storage electrode (31) becomes or remains unchanged and in any case as a new reference charge (Qref2) in a via a conductive diffusion area with the non-inverting input of a second Evaluation circuit (FF2) connected tenth storage electrode (45) held ready is that at the same time the partial charge from the seventh storage electrode (31) in second case by means of a fourth symmetrical charge splitter (40,41,42) in two equal partial charges (9s / 8) are split and under eleventh and twelfth storage electrodes (41.42) is stored separately that at the same time the partial charge from the eighth storage electrode (32) either by means of the fourth symmetrical one Charge divider (40, 41, 42) is split into two equal partial charges (Q / 8) and stored separately under eleventh and twelfth storage electrodes (41, -42) or unchanged in a further intermediate storage electrode (44) as an additional charge (Qzus2) mixed with the information charge (x) from the ninth storage electrode (36) and as a new information charge (CAx + Qzus2) in a via a conductive diffusion area connected to the inverting input of a second evaluation circuit (FF2) three tenth storage electrode (46) is kept ready that at the same time the information charge (ix) from the ninth storage electrode (36) remains unchanged in the first case and via the intermediate storage electrode (44) into said thirteenth storage electrode (46) is pushed and that this process corresponds to the number of to be assessed Bit positions repeated progressively. 2. Converter according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that the analog-to-digital converter has seven rows of parallel chains storage electrodes lying one behind the other contains that with a bit pattern width of q bits the first, fifth, sixth and seventh rows of (q + 1) storage electrodes and the second through fourth rows consist of (q + 2) storage electrodes that are the storage electrodes of the odd-numbered rows with a first voltage source, which is a DC voltage # 0 supplies, and the storage electrodes of the even-numbered rows with a second Voltage source that supplies a clock voltage 1 between zero and closed are that the charges of the storage electrodes of the individual rows from outside controllable displacement electrodes r between the Storage electrodes of the individual rows are, according to a predetermined clock program to the Storage electrodes of the adjacent rows are displaceable that each storage electrode (25,35r45,55,65) of the first row can be influenced by two displacement electrodes is, the respective first displacement electrodes with the first voltage source and the respective second displacement electrodes are connected to the second voltage source are that the respective first associated displacement electrodes of the storage electrodes (25, 35,45,55,65) of the first row each have the same size charge transfer channels to the first (q + 1) storage electrodes (23, 33,43,53,63) of the second row, that the second associated displacement electrodes of the storage electrodes (25, 35, 45, 55, 65) of the first row charge transfer channels to the last (q + 1) Make storage electrodes of the second row that the q last storage electrodes the first row also have conductive diffusion regions with floating potential, which are connected to the first input node of q evaluation circuits that between Storage electrodes of the second and third rows also shift electrodes are arranged so that each displacement electrode has an equally large charge displacement channel between the respective adjacent storage electrodes of the second and third row releases the shift electrodes between the first two and the last Storage electrodes (23, 11; 33,21; 73,61) of the second and third rows with the second voltage source and the displacement electrodes between the remaining storage electrodes (43.31; 53.41; 63.51) of the second and third rows with the non-inverting ones Outputs (A1, A2, A3) of the first (q-1) evaluation circuits are connected that the last storage electrode (73) of the second row via a displacement electrode ' which is connected to the first voltage source, with a first Charge sink (95) is gekoppel.t that between the third and fourth row of Storage electrodes (11, 21, 31, 41, 51, 61; 10, 20, 30, 40, 50, 60) first displacement electrodes are arranged, which are connected to the first voltage source, the charge transfer channels from all storage electrodes (11 r21 31,41,51,61) of the third row to all storage electrodes (10,20,30,40,50,60) affect the fourth row, being the charge transfer channel between the first two storage electrodes (11, 10) of these rows is essential is smaller than that between all the other electrodes, with the exception of the first two and the last storage electrodes (11,21,61) of the third row and of the first two storage electrodes of the fourth row (10, 20) between the storage electrodes (31.40; 41.50; 51.60) of these two rows further displacement electrodes are arranged are those to the inverting outputs of the first (q-1) evaluator circuits are connected that between the first two storage electrodes (10,12) of the fourth and fifth row of storage electrodes, a shift electrode that is connected to the first Voltage source is connected, with a larger charge transfer channel than between all other storage electrodes lies between the second and third storage electrodes (20,30) of the fourth row and the first two storage electrodes (12,22) of the fifth Row are also arranged displacement electrodes, which are connected to the second voltage source are connected that from the second storage electrode (30) to the penultimate storage electrode (50) of the fourth row and from the second storage electrode (22) of the fifth row between the storage electrodes (20,22; 30,32; 40,42 ;, 50,52) of these rows of displacement electrodes which are connected to the first voltage source, the charge transfer channels control between the corresponding storage electrodes (20,30,40,50; 22,32,42ü52), that also beginning with the fourth storage electrode (40) of fourth row and the third storage electrode (32) of the fifth row between the storage electrodes (40, 32; 50, 42; 60, 52) are arranged further displacement electrodes are those with the non-inverting outputs of the first (q-1) evaluator circuits are connected that between the storage electrodes of the fifth and sixth rows beginning with the third storage electrode (32) of the fifth and the second storage electrode (44) of the sixth row and ending with the last storage electrode (52) of the fifth and the penultimate storage electrode (64) of the sixth row of displacement electrodes are arranged, which are connected to the inverting outputs of the first evaluation circuits are connected that the storage electrodes of the sixth row also shift electrodes are assigned, which are connected to the first voltage source and the charge channels to control the storage electrodes of the seventh row, the last storage electrode (74) of the sixth row a charge transfer channel to a second charge sink (76) has that the storage electrodes (34,44,54,64,74) of the sixth row further Shift electrodes are assigned, which are connected to the second voltage source are, the displacement electrodes of this type charge transfer channels to the storage electrodes (26,36,46,56,66) affect the seventh row, and that the storage electrodes (36,46, 56,66) of the seventh row with the exception of the first storage electrode (26) this row also have conductive diffusion areas with floating potential, which are connected to the second input node of the q evaluation circuits, and that the first storage electrode of the seventh row has a shift electrode, which is connected to the first voltage source, with a charge transport storage arrangement (24), which is used to enter the information load, is coupled 3. Converter according to one of the preceding claims, d a d u r c h. g e k e n n g e I. n e t that the evaluation circuit is designed as a flip-flop (FF), the sen Signal inputs form the gate electrodes of the load transistors, the gate electrodes are designed as "floating gates" .. 4. Converter according to one of the preceding claims, d a -d u r c h e k e k e n n n e i c h n e t that the generation of the reference charge components alone happens through symmetrical connection. 5. Converter according to one of the preceding claims, d a -d u r c it is noted that the charges to be compared solely by addition of reference charge proportions or by adding reference charge proportions to the Information charge can be generated. 6. Converter according to one of the preceding claims, d a -d u r c h e k e n n n n e i n e t that all of reference or information loads touched electrodes contain at least one basic charge. 7. Converter according to the preceding claims, d a d u r ch g e k e n g e i c h. n e t that all charges after completion of the comparison process can be removed from the arrangement by means of charge sinks provided for this purpose. 8. Converter according to the preceding claims, d a d u r ch g e k It is noted that it is used to convert analog signals in the form of amounts of charge no reference voltage in parallel pending digital signals in the form of potentials needed