DE3222389C2 - - Google Patents

Description

The invention relates to an interface Circuit arrangement according to the preamble of claim 1.

Known interface circuits that one Connect processor to a message channel used only as a buffer. They store data messages, that occur on the news channel and generate each time an interruption when a data message arrives. A problem with this arrangement is that the Processor too much real time in the operation of the Interface circuit outgoing interruptions only for storing the data in its allocated memory consumed. A substantial part of this real time is spent at Decoding the header field of the data message is spent to determine whether the data message for the associated Processor is determined and - if applicable - where the Data message is to be stored in the processor memory. Known Interface circuits speed up this decoding process not and have little built-in intelligence. they serve only as a simple buffer, so that the assigned Processor for decoding and storing the message is required. So far this has not been a major problem since the processors are not real time limited or in one Work in block mode. In business communication systems this waste of real time is significant Obstacle to asset quality improvement.

The invention is accordingly based on the object the processor in storing and decoding Data messages of a message channel in the processor  to relieve allocated memory. Starting from the Circuit arrangement according to the preamble of claim 1 characterized the solution in claim 1.

Developments of the invention are the subject of Subclaims.

The interface circuit according to the invention works accordingly as a message processing device, the one High speed interface between one Processor memory and a data message channel represents. The news channel carries data messages with one head, that specifies a virtual address. The canal Interface circuitry according to the invention is programmable and dynamically translates the header section of the received one Data message from a virtual address to a component Memory address used to activate a specified Storage location in processor memory is used. The The data part of the message is then directly, i.e. H. in direct Memory access (DMA) entered into this memory location, and the respective buffer information signs are reset. Such direct memory access is known per se (US-PS 41 63 280). Only if a complete data message recorded and stored in the processor memory, generates the Channel interface circuit a processor interrupt to the  To inform the processor that a complete The data message is now stored in its memory is. Accordingly, the channel interface circuit performs according to the invention include all data reception tasks message storage and chaining through, without the involvement of the associated processor is required. This turns processor real time on saves and the speed of data transmission between the message channel and the processor increased because no delay occurs due to the processor each data message must address and they either in store its memory or address information far where the data message should be stored.

The invention is based on the drawing gene described. It shows

Figures 1 and 2, the connection interface scarf device according to the invention;

Fig. 3 shows the structure of a read-write queue used in the invention;

Fig. 4 the togetherness of Figures 1 and 2.

Fig. 5 shows the connection of the channel interface circuit with the processor and the processor memory.

The present channel interface circuit 100 is used to connect a message channel 120 to a processor 101 and a processor memory 102 via the address, data and control bus lines of the processor 101 as shown in Fig. 5. It is assumed that the message channel 120 data after align with a head that specifies the processor destination address and a virtual channel number. The channel interface circuit 100 monitors the message channel 120 to determine if any of these data messages are for the processor memory 102 . If this is the case, the channel interface circuit 100 stores the data messages received by the message channel 120 directly in the processor memory 102 without the involvement of the processor 101 being necessary.

In a corresponding manner, proceed from the processor 101 de messages that are played on the communication channel 120 to be stored in the processor memory 102, and the channel interface circuit 101 directly accesses the data messages in the processor memory 102 and passes it on the news channel 120., without involvement of the processor 101 is required.

Read-write queues

An essential component of the data transmission used in the present application is the read / write queue, an example of which is shown in FIG. 3. This queue is simply a portion of processor memory 102 that has been designated by processor 101 as a location for data messages to be received or sent. In the present exemplary embodiment, who creates the read / write queues for messages coming from the transmission channel 120 and read / write queues for data messages which are to be sent out via the message channel 120 . The basic structure of these queues is, as shown in FIG. 3, uniform for these application cases, and it is expedient to explain the structure of the read-write queue now. The basic read-write queue is described by a set of queue data that includes four pointers and a semaphore. Two of these pointers define the limit of the queue. It is the base pointer that indicates the memory address location at which the queue begins and the boundary pointer that indicates the memory address location at which the queue ends. The other two pointers are the write pointer and the read pointer. These indicate whether messages should be written to the queue or read from it. For the purposes of the present description, the read pointer indicates the memory address location at which the first byte of the next data message is stored, which is to be transmitted to either processor 101 or message channel 120 . The write pointer indicates the memory address location into which the first byte of the next received data message is to be written by either the processor 101 or the channel interface circuit 100 .

With reference to FIG. 3, it can be seen that these pointers change each time a circuit accesses the respective queue. Accordingly, before the processor 101 or the channel interface circuit 100 accesses a queue, all corresponding pointers are read by the requesting circuit so that updated pointer information is available to the requesting circuit. To avoid possible problems in connection with a queue conflict, the information symbol is used and generally comprises a specific bit pattern which is stored in the memory address location which immediately follows the address location identified by the boundary pointer. The information sign is essentially a flag that indicates an access to the queue-seeking circuit, whether the queue is empty or whether another circuit is currently accessing it. In this way, the flag prevents competing access to a queue with the associated confusion due to the volatile nature of the read and write pointers during simultaneous read and write operations.

Another problem with using the reading Write queues is the overwriting of a wait queuing at which new data is completely filled Queue to be enrolled before that stored data messages have been read out. The warning sign can be used to prevent such processes are used, with a flag being set to indicates that the queue is full so that new arrives Data messages are not queued be written. An alternative protective device  may be a location or data cell left between the read and write pointers will when the queue is full and the read and Align write pointers when the queue is empty is. This allows a requesting circuit to determine whether the queue is full or completely empty. A The third, commonly used option is there rin that the accessing circuit controls the pro processor manifolds when the queue takes over becomes full so that another circuit has no access to the memory for the purpose of writing further data messages can win.

Selection of a virtual channel number

In order to facilitate the understanding of the circuit, the output of a typical data message is described. As mentioned above, data messages transmitted on message channel 120 have a header field that contains both the processor address and a virtual channel number. indicates. The obvious question now is:
"How are data transmitted between two processors assigned to virtual channel numbers?" The answer to this is that there is a common intermediate processor initial transmission arrangement that defines virtual channel numbers. Processor 101 connects to another processor (not shown) connected to message channel 120 by accessing that other processor and selecting a virtual channel number to be used for this message connection. The access is exercised by the processor 101 exerting a data message on the transmission channel 120 , which contains the address of the destination processor and a virtual channel number zero, which indicates to the destination processor that this is an initial setup message intended for the destination processor . The determination processor responds to the initial message from processor 101 in a similar manner by transmitting a data message over message channel 120 with a header containing the address of processor 101 and a virtual channel number zero. By exchanging such messages, processor 101 and the destination processor do the necessary collaboration to identify a shared virtual channel number and the respective programs in their systems that request that connection.

After a virtual channel number is then selected for a particular processor-to-processor connection, this information is entered in the header of the data message and the complete data message is stored in processor memory 102 in the read-write queue used for outgoing data message . Since all outgoing data messages have a common destination, namely message channel 120 , there is only one read / write queue for outgoing data messages, and all outgoing data messages are stored there.

Transmitter - Fig. 1

The outgoing or transmitting part of the channel interface circuit 100 is shown in FIG. 1 and is controlled by the output state control device 103 . This control device 103 can be implemented in many ways. The present circuit arrangement uses a microprocessor for this function. The microprocessor is programmed in a known manner to provide the control and timing signals necessary for the common operation of the channel interface circuit 100 .

The transmit section of the channel interface circuit 100 includes a number of registers that are loaded with the various pointers associated with the outgoing read-write queue. This loading of the registers is carried out by means of the control device 103 , which requests access to the outgoing read / write queue in the processor memory 102 via the control, address and data bus lines of the processor. When the processor 101 grants access, the outbound controller 103 sequentially performs the following through an actuation wire (not shown):

• 1) loading the base pointer into the base pointer register 111 ,
• 2) loading the read pointer via the selector 112 into the read pointer register 110 ,
• 3) loading the boundary pointer into the boundary pointer register 108 ,
• 4) Load the write pointer into the write pointer register 106 .

Depending on a comparison operation carried out by a comparison circuit 107 , the control device 103 outputs a data message to the transmission channel 120 if such a data message is stored in the outgoing read / write queue. The comparison circuit 107 makes this determination by comparing the content of the read pointer register 110 with the content of the write pointer register 106 . If the values differ, the comparison circuit 107 outputs a logic signal on the RWC wire to the control device 103 , which indicates that the two pointers are not the same and accordingly the outgoing read-write queue contains a data message to be sent. The control device 103 responds to this logic signal on the RWC wire by activating the DMA REQUEST wire. The corre sponding signal is fed to the control bus of the processor to request access to the bus of the processor, so that the channel interface circuit 100 can access the processor memory 102 .

Memory access

Processor 101 indicates to channel interface circuit 100 that the processor bus lines are available by providing the appropriate logic signal on the DMA CRANT wire. Veran basis of this signal triggers the control unit 103 via the wires ENABLE and READOUT the read pointer register 110, its contents to the DMA address buffer output 104, which then passes this address on the address bus of the processor. This provides access to the memory address location in processor memory 102 that contains the first byte of the next data message to be sent. It is assumed in this system that all data messages have a fixed length. Therefore, the word counter 105 is then reset by the control unit 103 , which gives an actuation signal to the LOAD wire. In the present embodiment, the word counter 105 is a hard-wired down counter with a fixed count range that is equal to the length of the standard data message. Accordingly, when the controller 103 is a count signal on the line leading to word counter 105 artery CD, thereby the counter 105 is caused to decrease its count by the first This process continues until the count value reaches zero. This then indicates that a complete data message has been transmitted. Each time the count in the word counter 105 is decreased, the control unit 103 outputs an address increment signal on the ADVANCE wire to the read pointer register 110 . In this way, the address stored in the read pointer register 110 , which is passed from the DMA address buffer 104 to the address bus of the processor, is increased by one memory location until a complete data message has been output. This is indicated by the word counter 105 transmitting a display signal zero to the control unit 103 via the wire ZERO .

When each component address is applied to the address line of the processor, the content of the corresponding memory location in processor memory 102 is output by processor memory 102 onto the data line of the processor. The data is entered into the data connection interface 119 when the control device 103 gives an actuation signal to the LOADT wire. The data are then output in the usual way from the data connection interface 119 to the message channel 120 , again under the control of the control device 103 via the wire TRANSMIT . When the complete data message is transmitted, the controller 103 resets itself and in turn reads the various pointers in the outgoing read-write queue to determine whether there is another message stored there that is transmitted over the message channel 120 should.

The structure and mode of operation of the data connection interfaces 119 are known. Specifically, an article entitled "Data Communications: Part 3" by Alan J. Weissberger, pp. 98-104, appeared in "Electronic Design Magazine" on June 7, 1979, in which a typical channel interface circuit is described. The receiver-transmitter circuit described in the aforementioned publication is a known circuit arrangement with the aid of which the data connection interface 119 can be implemented. The circuit arrangement operates in a known manner, receives the serial digital data signals which appear on the message channel 101 , converts these signals for use in the channel interface circuit 100 and takes a clock signal from them. Correspondingly, signals to be transmitted are formatted via the message channel 120 , and the data connection interface 115 provides the time control.

Queue circulation

If the read pointer reaches the end of the queue in the present system, it must be brought back to the beginning of the queue, since this is a circular queue in which messages are processed on the principle that the first entered messages are also processed be issued first. This new beginning is achieved by the comparison circuit 109 comparing the content of the limit pointer register 108 and the content of the read pointer register 110 . If the content of these two registers is identical, the comparison circuit 109 outputs a signal on the wire READ = LIMIT to the control unit 103 . Based on this signal, the control unit 103 causes the selector 112 via the SELECTION wire to transfer the content of the base pointer register 111 into the read pointer register 110 which has been actuated via the LOADP wire. This will bring the read pointer back to the beginning of the queue.

Incoming Data Message Circuit - Fig. 2

The incoming part of the channel interface circuit 100 is shown in FIG. 2. It receives data messages from message channel 120 , interprets the header section of the data message and stores the data messages intended for processor 101 in processor memory 102 . This part of the channel interface circuit 100 is controlled by the input state control unit 201 , which - like the output state control unit 103 - can be a microprocessor. In fact, both control units 201 and 103 can consist of the same circuits, which are equipped with two programs, namely one for the control of incoming data messages and another for the control of outgoing data messages.

As discussed above, the data message format includes a header containing the address of a destination processor and a virtual channel number, as well as the data itself. A typical processor-to-processor connection is established as described above and for the explanation of FIG Fig. 2, it is assumed that the virtual channel numbers for a number of pro cessor-to-processor connections are already established and data messages are transmitted on the communication channel 120 to the processor 101. When a processor-to-processor connection is initiated, the processor 101 writes the associated information relating to this connection into the channel control memory 212 . Specifically, a read-write queue such as the queue shown in FIG. 3 is created for each processor-to-processor connection to be executed. Accordingly, for a 32 channel transmission system, the channel control memory 212 can be implemented by a 32xn random access memory ( RAM ), where n indicates the number of bits required to identify all the properties of these connections.

As discussed above, a typical read-write queue includes a read pointer, a write pointer, a base pointer, and a boundary pointer. Besides the additional information is it conducive for each compound, for example an interruption vector information, the program the address of a Bedienungsunterpro in the processor 101 includes, which is then called when the channel interface circuit 100 send a data or a number n of data messages be taken and has stored in processor memory 102 . Further information regarding the channel properties falls under the heading "State", which is a general expression for all maintenance or identification information which the processor 101 wants to assign to the respective processor-to-processor connection using this special virtual channel . Typical status information is a count for the number of transmission errors, an identification of the transmission type (block transmission, simple message, etc.) and the state of the channel, namely whether it is open or closed for transmission. Accordingly, in a 32-channel system, processor 101 creates 32 read-write queues in processor memory 102 and writes the above information regarding each of these read-write queues to channel control memory 212 via memory access multiplexer 213 . The processor 101 accesses the information stored in the channel control memory 212 via the data buffer 211 , the access being monitored by the input state control unit 201 .

To further describe the incoming part of the channel interface circuit 100 , the recording of a typical data message from the transmission channel 120 is expediently described. When a data message appears on the message channel 120 , the data link interface 119 picks up the transmitted bits and decodes the header portion of the data message to the extent that it can determine if the header processor is processor 101 . If the data message is intended for the processor 101 , the data connection interface 119 notifies the input state control unit 201 of this via the wire PA . The control device 201 then stores the virtual channel number contained in the header in the register 204 for virtual channel numbers by means of an actuation signal on the LOADR wire. The control unit 201 activates the channel control memory 212 via the bus ENABLE , and the address stored in the register 204 is fed to the address wires of the channel memory 212 via the wires ADDRESS and the memory access multiplexer 213 B. The application of the virtual channel number to these address wires causes all relevant information relating to this virtual channel, which are stored in the channel control memory 212 , to be output to the memory bus shown in FIG. 2, which contains the data buffers 211 , the multiplexers 209 , 210 and connect the channel control memory 212 .

The input state control unit 201 undergoes a sequence of operations when the data is received from the data connection interface 119 and is stored in the processor memory 102 . One of the first steps in this is to compare the read and write pointers to determine - as discussed above - whether the associated read-write queue is full. This is achieved by means of the input state control unit 201 , which leads the read pointer and write pointer information from the channel control memory 212 via the A multiplexer 210 and the B multiplexer 209 to the arithmetic logic unit 208 . Unit 208 performs a common comparison operation to determine if the read and write pointers are equal. If they are not the same, there is still space in the queue for additional data messages. This is indicated by the corresponding logic signal on the COMPARE wire. The controller 201 , depending on the signal on the COMPARE wire, issues a DMA request signal on the DMA REQUEST wire of the processor control bus to request access to the processor bus. The processor 101 indicates the response to the request by a logic signal on the DMA GRANT wire, causing the controller 201 to activate the address buffer 206 over the ENABLE line. Since the read pointer information output by the channel control memory 212 is transmitted via the arithmetic logic unit 208 and the address buffer 206 to the address common line of the processor. In the meantime, the data received by the data connection interface 119 are stored in the data buffer 205 and output byte by byte onto the data bus of the processor when the input state control device 201 causes the word counter 207 to advance the component address stored in the address memory 206 . So who the data is stored in the read-write queue assigned to the virtual channel, and the write pointer is switched on until the complete data message is stored in the queue. This is indicated by the word counter 207 returning a zero display via the ZERO 2 line to the control unit 201 . At this point, controller 201 returns to its initial state and waits to receive another data message on transmission channel 120 . In addition, since the input state controller 201 is a microprocessor, it can perform a number of maintenance subroutines and / or programmed interruptions to take advantage of the data stored in the state part of the channel control memory 212 , as described above. In this way, the channel interface circuit 100 takes over complete control for the reception and transmission of data messages on the message channel 120 .

Claims (6)

1.Interface circuit arrangement for connecting a processor which has a data bus, an address bus and a control bus, and its associated memory with a message channel on which data messages are transmitted in circular operation, which header field with a destination address for a processor and a virtual channel number, as well as a data field, characterized in that
that the interface circuit arrangement ( 100 ) has:

• a) a connection interface ( 100 ) to the message channel ( 120 ), a data buffer ( 205 ) and a virtual channel register ( 204 ) which, in response to a data message appearing on the message channel ( 120 ) decode the header field and provide the virtual channel number when the processor ( 101 ) is the processor specified in the destination address of the header field;
• b) a channel control memory ( 212 ) and a memory access multiplexer ( 213 ) which are connected to the interface circuit ( 119, 204, 205 ) and convert the virtual channel number into a memory address of the memory ( 102 ) assigned to the processor ( 101 );
• c) an address buffer ( 206 ) which is connected to the channel control memory ( 212 ), the memory access multiplexer ( 213 ) and the address bus of the processor ( 101 ) and, in response to the memory address, passes it onto the address bus by the one identified by the virtual channel number Activate memory location in memory ( 102 ); and
• d) a DMA circuit ( 201, 207 ) for connecting the interface circuit ( 119, 204, 205 ) to the data bus of the processor ( 101 ) in order to store the data field via the data bus directly into the activated memory location when the data message is received.

2. Interface circuit arrangement according to claim 1, characterized in that the channel control memory ( 212 ) and the memory access multiplexer ( 213 ) respond to the virtual channel number and output and output stored queue data for data messages to be transmitted, and that comparison circuits ( 208 to 219 ) are provided which connect the channel control memory ( 212 ) and the memory access multiplexer ( 213 ) to the address buffer ( 206 ) and in response to the queue data give a hardware or device memory address to the address buffer ( 206 ) when the queue data indicates that there is sufficient space is available in the processor memory ( 102 ) for receiving the data message. 3. Interface circuit arrangement according to claim 1 or 2, characterized in that the interface circuit arrangement ( 100 ) has input control circuits ( 201, 207 ) which are connected to the address buffer ( 206 ) and a connection interface ( 119 ) and upon receipt of the data message advance the hardware or component memory address stored in the address buffer ( 206 ) in synchronism with the receipt of the data message. 4. Interface circuit arrangement according to claim 3, characterized in that the input control circuits ( 201, 207 ) contain a word count register ( 207 ), upon receipt of the data message generates an end-of-word display when the entire data message has been received by the connection interface ( 119 ) . 5. Interface circuit arrangement according to claim 4, characterized in that the channel control memory ( 212 ) and the memory access multiplexer ( 213 ) is connected to the data, address and control bus lines, and that the input control circuits ( 201, 207 ) in response to the end of the word - Update the information stored in the channel control memory ( 212 ) about the data, address and control bus lines of the processor ( 101 ). 6. Interface circuit arrangement according to claim 1, characterized in that a data buffer ( 205 ) is connected to the input control circuits ( 201, 207 ) and under whose control stores the received data message and outputs byte by byte on the data bus of the processor ( 101 ).