DE3202495A1 - Process and device for monitoring a critical number of erase and/or write cycles of an electrically erasable, programmable read-only memory - Google Patents

Abstract

In a data processing system, a read-only memory (1) which is electrically programmable is used. The number of programming cycles is limited. If a critical number of programming cycles is exceeded, the memory cells may be destroyed. Apart from the read-only memory, a monitoring read-only memory (4), which is likewise electrically programmable, is also used. The monitoring read-only memory (4) is programmed together with the read-only memory (1). Preferably, program cycles of the read-only memory (1) are combined in such a way that program cycles of the read-only memory which activate different memory cells activate only one memory cell in the monitoring read-only memory. Therefore, the critical number of programming cycles is exceeded first in this cell. The destruction of memory cells in the monitoring read-only memory is monitored on the basis of a criterion and signalled. <IMAGE>

Description

L i c e η t i a

Patent Administration GhibH

6000 Frankfurt / M 70, Theodor-Stern-Kai 1

F 81/32

Eb / pae

January 18, 1982

Method and device for monitoring a critical number of Erase and / or write cycles of an electrically erasable, programmable Read-only memory

The invention relates to a method and an apparatus for Monitoring of a critical number of erase and / or write cycles of an electrically erasable, programmable read-only memory.

Read-only memories are known which have been electrically erased and re-created can be programmed. The deletion and reprogramming can be done byte by byte. However, it is also a simultaneous deletion of the entire content of the read-only memory is possible. Such read-only memories are implemented in MOS technology. With these read-only memories A flexibility similar to that achieved with random access memory was achieved. At the same time, however, the permanent one remains Preserved the character of read-only memory.

However, the total number of erase-write cycles is not arbitrary great. If a critical number of erase and / or write cycles is exceeded, no more data is transferred from the respective memory cell of read-only memory. Care must therefore be taken when using the electrically erasable, programmable read-only memory ensure that the permitted number of read-write cycles is not exceeded

ORIGINAL INSPECTED

The invention is based on the object of developing a method with which a critical number of erase and / or write cycles of an electrical erasable, programmable read-only memory can be monitored.

The object is achieved in that at the same time with each Erase and / or write cycle for information from a data processing device certain read-only memory into a structurally identical monitoring read-only memory predetermined test data are stored, which are when the critical number of deletion and / or Change write cycles to error data and that in a read cycle of the read-only memory containing the information for the data processing device the monitoring read-only memory can be checked for the presence of error data.

The error data can be used to determine whether the monitored read-only memory still works flawlessly. Only the data read from a faultless read-only memory are then processed further. In data processing devices in which electrically erasable, programmable Read-only memories are used, the method explained above enables the determination of an inadmissible number of erasure, Errors based on write cycles. If such errors exist, their further processing can be prevented. The reliability of with Data processing devices equipped with electrically erasable, programmable read-only memories are improved as a result. When exceeded The critical number of erase and write cycles can make the read-only memory unusable be replaced with a new one.

In a preferred embodiment it is provided that deletion and / or Write cycles, which are each assigned to a plurality of addresses in the read-only memory intended for the data of the data processing device, in the monitoring read-only memory are assigned to only one address as erase and / or write cycles. This measure makes the monitoring read-only memory the critical number of erase and write cycles is reached earlier than with the read-only memory, which stores the data for the data processing device contains. The monitoring read-only memory is therefore already in an unusable state when the other read-only memory still works flawlessly. When determining error data in the general

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Monitoring read-only memories can store the data from the other read-only memory therefore still be processed further. The error message from the supervisory read-only memory but can be used to either replace both read-only memories with new read-only memories or the one for to no longer delete and reprogram the data of the data processing device specific read-only memory.

Preferably, the number of read-only memory addresses is one shared address of the supervisory read-only memory is assigned to occurring with electrically erasable, programmable read-only memories Tolerances of the critical number of erase and write cycles matched. For example, four digits of the address of the read-only memory are used for addressing one cell of the supervisory read-only memory is used, then is there is a high probability that the monitor read-only memory in the case of a number of erase, write cycles occurs, 1/16 of the erase and write cycles of the cells of the assigned address range of read-only memory is.

There is an apparatus for carrying out the method explained above according to the invention in that the read-only memory programmed for the data processing device and the monitoring read-only memory address signals that come from the same addressing circuit can be controlled and that the outputs of the monitoring read-only memory on the one hand via resistors to a driver circuit charged by the erase and storage signal and on the other hand to the inputs of a NOR gate are connected, which is followed by a flip-flop.

In addition to the monitoring read-only memory, there is only a small amount of circuitry Effort necessary for the recording of errors. Appropriate configurations of the measures described above are set out in the claims 5 to 9 explained.

The invention is illustrated below with reference to a drawing Embodiment explained in more detail, from which further features and advantages result.

ORIGINAL INSPECTED - 7 -

Show it:

1 shows a circuit arrangement for monitoring a critical number of erase and write cycles of an electrically erasable, programmable read-only memory,

2 shows another embodiment of a monitoring circuit for an electrically erasable, programmable read-only memory.

An arrangement for monitoring a critical number of extinguishing and / or Write cycles contains a first read-only memory 1, which is used for recording is determined by information in the context of a data processing device. This data processing device is shown in the drawing only one addressing circuit and one control signal source 3 are shown.

The addressing circuit feeds the address inputs of the read-only memory The read-only memory 1 is an electrically erasable, programmable read-only memory, for example that of the Type 28 16 manufactured by INTEL CORPORATION.

A second read-only memory 4, identical in construction to the read-only memory 1 is used to monitor the critical number of erase and / or write cycles. The read-only memories 1, 4 each have an input 5,. Der von the control signal source 3 with a ready signal of z. B. 5 volts is applied. Another input 6 each of the read-only memory 1, 4 is via the control signal source 3 with a cancel signal of z. B. 8 volts can be applied. When this signal is present, all memory cells are together reset to binary 1 signals. Both read-only memories each have an input 7 for an erase, write pulse of z. B. 21 volts. The inputs 7 are connected to the control signal source 3.

The outputs of the monitoring read-only memory 4 each have inputs a NOR gate 8, the output of which is connected to the D input of a D flip-flop 9. The clock input of the D flip-flop is connected to inputs 6 connected. Furthermore, the outputs of the read-only memory 4 are each connected to a driver circuit 11 via resistors 10, which is fed by the control signal source 3.

In each case, several outputs of the address list; Ljng 2 are connected in OR-Ver ^ n:.;: - ^f ung via gate 12 to address inputs 13, 14 of the monitoring read-only memory 4.

When a specific byte in read-only memory 1 is reprogrammed should, the content of the address under which the byte is stored is initially turned off. This is done by connecting to the outputs of the read-only memory, which at the same time represent programming inputs, have a high potential is applied while the addressing circuit 2 outputs the respective address. The input 5 is held at low potential. The entrance 7 is applied with an extinguishing pulse. At the same time there is one at entrance 6 high potential. The byte configuration to be stored is then applied to the outputs of the read-only memory 1, during the inputs 5, 6 and 7 the same signals are given as during the deletion process.

The address of the byte to be reprogrammed is applied via the gate 12 also the address inputs 13, 14 of the monitoring read-only memory 4. At the inputs 5, 6, 7 of the monitoring read-only memory are during of an erase cycle the same signals as at the inputs of the read-only memory 1 at. The outputs of the monitoring read-only memory 4 are supplied with high potential via the driver circuit 11 during erasure.

During the subsequent write cycle, the signals at inputs 5, 6 are correct and 7 match again in both read-only memories 1, 4. However, the driver stage 11 acts on the outputs of the monitoring read-only memory 4 Via the resistors 1Ö with low potentials, the binary 0 signals assigned. In the write cycle, the content is accordingly in the read-only memory 4 addressed memory cell is set to the binary value "0".

It has been shown that those memory cells in which the critical Number of erase and write cycles has been exceeded, are no longer able to receive binary O signals. All those memory cells that are after an erase, write cycle in the monitoring read-only memory 4 is unusable therefore send binary 1 signals to the outputs.

BAD ORIOiMAL ° ^RIG ' ^{NAL INSPECTED}

Beit: Reader: des memory ·· 1 we i <! -; · I '-. ^ Qt: ·· 6 with never-> ι ^ - Pc ie ··· ¹ : rfl l · «- opens while the Adressenschal Lung 2 outputs the memory addresses. If the addressed cell in the monitoring read-only memory 4 has become unusable, the binary 1 signal arrives at the output of the NOR element 9, at the output of which a binary 1 occurs again. This binary 1 is taken over with the signal at the inputs 6 in the D flip-flop 9, which thus emits an error message at its output. This error message can be evaluated to the effect that the data processing device interrupts its operation until the read-only memories 1, 4 have been replaced or have responded in some other way.

As at least some of the memory cells of the supervisory read-only memory 4 are subjected to more erase, write cycles than the memory cells of the read-only memory 1, these memory cells of the read-only memory reach 4 the critical number of erase, write cycles before the other memory cells. These memory cells are therefore ahead of the other memory cells unusable.

With each read operation in the read-only memory 1, the flip-flop 9 is queried at the same time as to whether there are memory cells in the monitoring read-only memory 4 are unusable. Since the most frequently subjected to erase and write cycles Memory cells of the monitoring read-only memory 4 are the first to be unusable are at the time the error message occurs the other memory cells, in particular those of the read-only memory 1, are not yet unusable. This means that those from the Read-only memory 1 at the same time with the detection of an error in the monitoring read-only memory 4 read out data are not faulty and can be further processed. The error message can also do this can be used to block the further programming of the read-only memories 1, 4.

In Fig. 1, the outputs of the OR gates 12 each occupy a plurality of address inputs of the monitoring read-only memory 4. To save storage capacity, it is advantageous to use OR gates 12 to address only one memory cell. Since the remaining memory cells are not required, a monitoring read-only memory 4 can also be used a capacity corresponding to the number of the number of storage locations addressed by the OR gates 12 can be used. Monitoring will here more cost-effective.

In the preferred embodiment shown in Fig. 2, there are sixteen read-only memories 1A to 1P, of which only three memories 1A, 1B and 1P are shown. All read-only memories 1A to 1P have the same storage capacity of 2048 bytes. The total memory therefore has a capacity of 32768 bytes. The memories 1A to 1P are each equipped with eleven address inputs, which are labeled _{A Q} to A _{10 in FIG.} The address inputs Aq, A ₁ , A ₂ , A ₃ , A, A ₅ , A _ß , A ₇ , Ag, Ag, A _{10 of} all memories 1A to 1P are common to the outputs of an addressing circuit not shown in FIG placed. The output lines of this circuit are also designated A _n to A _1n in FIG. 2. The output lines A _n to A _1n correspond as well as the address inputs A _n to A _1n the binary point values 2,2, 2 ^2, 2 ^3, 2 ^4, 2 ^5, 2 ^6, 2 ^7, 2 ^8, 2 ^9, and 2 ¹⁰ .

There are further address lines A ₁₁ , A ₁₇ , a ^, A ,,, available,

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which proceed from the addressing circuit (not shown) and correspond to the binary address position values 2, 2, 2 and 2, respectively. The address lines A ₁₁ to A .. are connected to a decoder 13, which performs 1 out of 16 decoding. The sixteen output signals of the decoder 13 are each fed to an input 14 of the read-only memories 1A to 1P; the read-only memories 1A to 1P for the address signals A _Q to A _{10 are} activated via these inputs 14.

A selection signal is also sent via a line 15 to an input 16a of the decoder 13 and one input of an AND gate 16, the second input of which is connected to a line 17 on which during the Duration of the programming a signal with the binary value "0" is present. The output of the AND element 16 is connected to an input 18 of a monitoring read-only memory 19, which has a storage capacity of 2048 bytes. The function of input 18 corresponds to the inputs 14th

A further line 20 becomes inputs 21 of the read-only memory 1A to 1P and the monitoring read-only memory 19 activated with a binary 0 signal for the read cycle. The line 21 is also with the Clock input of a D flip-flop 22 connected, the D input of which is connected to the output of a NOR gate 23, with the inputs of the eight outputs of the supervisory read-only memory 19 are connected.

ORIGINAL WQPECTED

320249b

The outputs of the monitoring read-only memory 19 are still on a resistor 24 is connected. The resistors are controlled jointly by a driver stage 25, which is connected to a line 26 on the input side is laid. A binary "1" is present on line 26 during the read or erase cycle for the monitoring read-only memory 19. While writing of the monitoring read-only memory 19, the line 26 outputs a binary "0".

The monitoring read-only memory 19, like the memories 1A to 1P, has eleven address inputs Aq to A, q. The address inputs A _Q to A ₃ are connected to the address lines A ₁₄ to A ... The address inputs A. to A ₁₀ are fed by the address lines A. to A ₁₀ . This address assignment achieves a favorable assignment of individual memory locations of the monitoring read-only memory 19 to memory areas of the read-only memories 1A to 1P.

The programming of the read-only memories IA to 1P assumes that first a deletion cycle runs in which to the not shown Binary "1" signals must be present at the outputs of the memory cells addressed in the read-only memories 1A to 1P. The read signal on the line 26 ensures that via the driver stage 25 and the resistors 24 at all outputs of the monitoring read-only memory 19 binary "1" signals available. A write cycle then runs. During the write cycle, the outputs are those in read-only memories 1A through 1P addressed memory cells acted upon by the binary values to be stored. A negated write signal on line 26 causes over the driver stage 25 and the resistors 24 binary "0" signals at the outputs of the monitoring read-only memory 19. The memory cells addressed in the monitoring read-only memory 19 therefore receive binary zeros, which change to binary ones when the critical number of programs is exceeded.

The supervisory read-only memory 19 becomes the read-only memory on every read cycle 1A to 1P are also addressed and outputs data via the NOR gate 23 to the flip-flop 22. If with one or more outputs of the monitoring read-only memory 19 is a binary "1" during the read cycle, there is a binary "0" at the beginning of the flip-flop 22, which can be evaluated as an error message.

BATH ORIGINAL

Claims (9)

120 L ice η tia
Patent-Verwaltungs-GmbH 6000 Frankfurt / Main 70, Theodor-Stern-Kai 1 F 81/32 Eb / pae January 18, 1982 Method and device for monitoring a critical number of erase and / or write cycles of an electrically erasable, programmable read-only memory Claims (Y) Method for monitoring a critical number of erase and / or write cycles of an electrically erasable, programmable read-only memory,
characterized in that at the same time with each erase and / or write cycle of a read-only memory (1, 1A to 1P) intended for information from a data processing device, predetermined test data are stored in an identical monitoring read-only memory (4, 19) which change to error data when the critical number of erase and / or write cycles is exceeded, and that during a read cycle of the read-only memory (1, 1A to 1P) containing the information for the data processing device, the monitoring read-only memory Memory (4, 19) can be checked for the presence of error data. 2. The method according to claim 1, characterized in that erase and / or write cycles that occur in the for the data of the COPY Data processing device specific read-only memories (V, 1A to 1P) are each assigned several addresses in the monitoring read-only memory (4, 19) are assigned to only one address as erase and / or write cycles. 3. The method according to claim 2, characterized in that the number of addresses of the read-only memory (1, 1A to 1P), which is assigned to a common address of the monitoring read-only memory (1, 1A to 1P) to which electrically erasable, programmable read-only memories occurring tolerances of the critical number of erase and / or storage cycles is coordinated. 4. Device for performing the method according to claim 1, characterized in that that the read-only memory (1, 1A to 1P) programmed for the data processing device and the monitoring read-only memory (4) can be controlled by address signals that come from the same addressing circuit (2) and that the outputs of the monitoring read-only memory (4, 19) on the one hand Via resistors (10, 24) to a driver circuit (11, 25) charged by the erase and storage signal and on the other hand Inputs of a NOR element (8, 23) are connected, which is followed by a flip-flop (9, 22). 5. Apparatus according to claim 3,
characterized in that a plurality of address signals of the addressing circuit (2) are combined in an OR link to form an address signal for the monitoring read-only memory (4). 6. Apparatus according to claim 4,
characterized in that the monitoring read-only memory (4), corresponding to the combination of the address signals of the addressing circuit (2), has less storage capacity than the read-only memory (1) programmed for the data processing device. 7. Apparatus according to claim 3 or one of the following claims, characterized in that the clock input of the flip-flop (9, 22) to the control input ^p (6, 21) of the read-only memory (1, 4, 1A to 1P, 19 ) connected. 8. Device according to claim 3 or one of the following claims, characterized in that with each write cycle in the monitoring read-only memory (4) binary O-signals are stored, which in the case of faulty memory cells lead to binary "1" signals. 9. Device according to claim 4 or one of the following claims, characterized, that the read-only memory programmed for the data processing device (1A to 1P) have a storage capacity of 32,768 bytes and the supervisory read-only memory (19) a storage capacity of 2048 Byte has and that the four address positions (A .. to A ..) with the highest values of the read-only memory (1) to the address positions (A _Q to A ₃ ) with the four lowest values of the monitoring read-only memory ( 4) are placed, while the address positions (A. to A, _Q ) from the binary place values four to ten in the read-only memory (17 and the monitoring read-only memory (4) match.