DE3164093D1 - Device interfacing a microprocessor bus and a synchronous periphery of sensors and drivers - Google Patents

Device interfacing a microprocessor bus and a synchronous periphery of sensors and drivers

Info

Publication number
DE3164093D1
DE3164093D1 DE8181102117T DE3164093T DE3164093D1 DE 3164093 D1 DE3164093 D1 DE 3164093D1 DE 8181102117 T DE8181102117 T DE 8181102117T DE 3164093 T DE3164093 T DE 3164093T DE 3164093 D1 DE3164093 D1 DE 3164093D1
Authority
DE
Germany
Prior art keywords
drivers
sensors
microprocessor bus
device interfacing
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181102117T
Other languages
English (en)
Inventor
Luciano Rosboch
Paolo Tiribelli
Silvano Giorcelli
Veen Wouter M D Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Original Assignee
CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSELT Centro Studi e Laboratori Telecomunicazioni SpA filed Critical CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Application granted granted Critical
Publication of DE3164093D1 publication Critical patent/DE3164093D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
DE8181102117T 1980-03-27 1981-03-23 Device interfacing a microprocessor bus and a synchronous periphery of sensors and drivers Expired DE3164093D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67468/80A IT1128078B (it) 1980-03-27 1980-03-27 Sistema di interfacciamento tra un bus di microcalcolatore e una periferia sincrona di sensori e attuatori

Publications (1)

Publication Number Publication Date
DE3164093D1 true DE3164093D1 (en) 1984-07-19

Family

ID=11302646

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181102117T Expired DE3164093D1 (en) 1980-03-27 1981-03-23 Device interfacing a microprocessor bus and a synchronous periphery of sensors and drivers

Country Status (3)

Country Link
EP (1) EP0037499B1 (de)
DE (1) DE3164093D1 (de)
IT (1) IT1128078B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3329228A1 (de) * 1983-08-12 1985-02-21 Siemens AG, 1000 Berlin und 8000 München Datenuebertragungsverfahren in einem digitalen uebertragungsnetzwerk und vorrichtung zur durchfuehrung des verfahrens

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1082532B (it) * 1977-03-14 1985-05-21 Cselt Centro Studi Lab Telecom Dispositivo di interfaccia tra complessi di organi sensori e distributori della segnalazione telefonica operanti in modo sincrono e un apparecchiatura di elaborazione di dati telefonici
FR2402990A1 (fr) * 1977-09-12 1979-04-06 Thomson Csf Dispositif d'exploration et de distribution destine notamment a un central telephonique

Also Published As

Publication number Publication date
IT1128078B (it) 1986-05-28
IT8067468A0 (it) 1980-03-27
EP0037499A3 (en) 1982-01-13
EP0037499A2 (de) 1981-10-14
EP0037499B1 (de) 1984-06-13

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee