DE3148397A1 - Electronic counter in 1-of-10 code - Google Patents

Abstract

(PUBLISHED WITHOUT ABSTRACT)

Description

Electronic counter in 1-out-of-10-ode

The subject of the invention is a special version of the electronic Counter from P 31 47 438.1. In the case of the electronic counters of the present patent application the decades do not consist of double flip-flopps, but of simple flip-flopps, those with a negation delay circuit or a special monoflop according to P 31 44 376.1 are combined, In Figure 1 is a decade of the electronic up counter Type A shown.

In Figure 2, one decade of the elextronic up-counter is type B.

In Figure 3, one decade of the electronic up counter is Type C.

In Figure 4, one decade of the electronic down counter is Type A.

In Figure 5, one decade of the electronic down counter is Type C.

In Figure 6 is a decade of the electronic up-down counter Type C 1 shown.

In Figure 7 there is a decade of the electronic up / down counter Type C 2 shown.

In Figure 8, the detail F of Figure 3 is shown.

In FIG. 9, the detail F, embodiment B from FIG. 1 is shown.

In FIG. 10, the detail F from FIG. 2 is shown.

FIG. 11 shows the detail F from FIG.

In FIG. 12, the detail F from FIGS. 6 and 7 is shown.

The display circuits E either consist of normal AND circuits or or from special and circuits corresponding to detail E a of FIG. 8 or from Spe special AND circuits corresponding to detail E b of FIG. 9.

The decade of the electronic up-counter type A (Figure 1) consists from the flip-flopps 1 to 5 and the special mono-flopps 11 to 15 and 10 input -Und circuits 16 and the AND circuits 17 to 19 and the decade transfer AND circuit 20 and the display and circuits 31 to 34 and 36 to 39e the AND circuits 18 and 19 are for the pre-control of the reversing flip-flop 5 and for the display the digits far from 0 and 5 are required. Part 46 is an additionally required one Negating circuit. The display outputs B of the display circuit E are associated with the Numerical values (digits 0 to 9). The counting pulse input has the designation Z and the decade carry output the designation Ue The total reset line has the designation S and its decade branch the designation t. The detail F is shown in FIGS. 9 and 11 in two different versions.

The decade of the electronic up counter type B (Figure 2) consists from the flip-flopps 1 to 5 and the negate delay circuits 41 to 45 and 10 input AND circuits 16 and the negation circuits 46 to 49 and the AND circuits 17 to 19 and the negating circuit 21 and the negating circuit 27 and the display and circuits 31 to 34 and 36 to 39. The display outputs B of the display circuit E are also marked with the associated numerical values (digits 0 to 9). The counting pulse input also has the designation Z and the decade carry-over output the designation U.

The total reset line has the designation S and its decade branch the term t. The detail F is shown in FIG.

The decade of the electronic forward counter Type C (Figure 3) has In comparison with the decade shown in FIG. 2, the difference is that the Flip-flopps 1 to 4 can only be controlled on the left (with the exception of the reset control) and that the flip-flop 5 is combined with a special mono-flop 15, like that Blipp-Blopp 5 in i'igur 1. le The decade of the electronic up counter Type C 2 (not shown) shows in comparison with the decade shown in FIG the difference is that the reversing flip-loop 5 with a negate delay circuit is provided in accordance with FIG. The negation circuit 27 is also required here.

The decade of the electronic down counter type A (Figure 4) consists from the flip-flopps 1 to 5 and the special mono-blopps 11 to 15 and 10 input and circuits 16 and the AND circuits 17 to 19 and the decade current transfer AND circuit 20 and the negating circuit 23 and the display circuit E consisting of the AND circuits 31 to 34 and 36 to 39.

The digits 0 and 5 are also used by the AND circuits 18 and 19 displayed. The display outputs B of the display circuit E are also associated with the Numerical values (digits 0 to 9). The count input also has the Designation Z and the decade carry output the designation U. The control inputs A of the setting circuit 60 are also assigned the associated numerical values (digits 1 to 9) marked.

The setting of the digit 0 (zero) is not required here, because before the setting the entire counting circuit consisting of a number of decades is reset to 0 (zero) every decade. The overall reset line has the designation S and its decade branch the designation t.

The decade of the electronic down counter type B (Figure 5) has the difference in comparison with the backward counting decade shown in FIG that the flip-flopps 1 to 4 are only controlled on the left side (with the exception of the reset control) and that instead of the special mono-flopps 11 to 14 negier delay circuits 41 to 44 are arranged.

The decade of the electronic up / down counter type C 1 (Figure 6) also consists of 5 flip-flopps 1 to 5 and 4 negier delay circuits 41 to 44 and a special mono-flop 15. The flip-flopps 1 to 4 are each with an input circuit 57, which consists of 2 AND circuits with 2 inputs each The reversing flip-flopp 5 is provided with an input circuit 58, those made up of 2 OR circuits with 2 inputs each and 4 AND circuits with 2 inputs each In other parts, this decade also consists of the AND circuit 17 and the AND circuits 18 and 19 and the negate circuit 21 and the display circuit E, consisting of the AND circuits 31 to 34 and 36 to 39. The AND circuits 18 and 19 are for the pre-control of the reversing flip-flop 5 when counting up and required for the display of the digits O and 5. The decade carry circuit 50 consists of the AND circuits 51 and 52 and the OR circuit 53 and the AND circuit 54. The up-counting pulse line e is pre-activated via the AND circuit 55 and the backward number pulse line f via the AND circuit 56. The count pulse input has the designation Z and the decade transfer output has the designation U. The total reset line has the designation S and its decade branch the designation t. The setting up counting is done by applying H potential to the control line V, the control line R being connected to L potential via a negating circuit Setting to counting down is done by applying L potential to the control line V, the control line R being connected to H "potential via the already mentioned negating circuit lies. The display outputs B of the display circuit E are also associated with the Numerical values (digits O to 9) marked.

The decade of the electronic up / down counter type C 2 (FIG. 7) shows in comparison with the up / down counting decade shown in FIG the difference is that the reversing flip-flop 5 is not with a EinsP special mono-flopp is combined, but with a negate delay circuit, like the flip-flopps 1 to 4. An additional negation circuit 27 is also required here.

This also applies to the decades shown and described here a corresponding counter usually from several decades or a larger one Number of decades.

The decades of the electronic up-down counters type C 1 B and Type C 2 B have Or-circuit-free input tag circuits throughout Range of decades. The input circuits of the reversing flip-flopps 5 exist in this case only from 4 AND circuits, each of which has 2 outputs with each other are connected. These input Uad circuits also consist of transistors accordingly Figure 12.

The operability of these delay circuit counters is of this depends on the fact that the duration of the counting pulses is shorter than the time Delay duration of the delay circuits.

The delay circuits used in these electronic counters (Special mono-floppy and negating delay circuit) are also in P 31 44 376.1 shown and described (Figure 2 and Figure 10) In Figures 8 to 11 is the Line r not shown.

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Claims (1)

Patent claim Electronic Modulo-IO up-counter or electronic Modulo-10 backward counter or electronic Modulo-I 0 forward-backward counter, which consist of one or two or more decades and their decades of one Reversal flip flop (5) and 4 number flip flop (1 to 4) exist, and where d that the reversing flip-flopp (5) pre-controls the display of two digits, thereby that the flip-flopps are not double flip-flopps (master-slave flip-flopps or simplified master-slave flip-flopps), but rather simple flip-flopps, which are combined with a delay circuit of some kind, or the combined with a delay circuit of some kind and a negating circuit are.