DE3147680A1 - Frame structure suitable for multiplexing signals having a very different bit rate - Google Patents

Abstract

The invention creates a frame structure suitable for multiplexing signals having a very different bit rate by means of an additional information of 16 bits at the beginning of the frame, which is used both for synchronisation and for signalling clock deviations, and a division of the subsequent information into eight equally large blocks. To multiplex a fast bit stream 01 of approximately 68734 to 68750 kbit/s with a slow bit stream 02 of 2048 kbit/s to form a multiplex bit stream of 71040 kbit/s, the eight blocks in each case contain 537 bits of the fast bit stream 01 and in each case 16 bits of the slow bit stream 02. Within each block, 1 bit each of the slow bit stream is multiplexed with 33 bits each of the fast bit stream and in in each case 16 sectors after 9 bits of the fast bit stream. One of the first 9 bits of the fast bit stream and the first bit in each case of the slow bit stream are provided as possible dummy bits. The 16 bits of the additional information have the following tasks: bits 1....4: fixed alignment pattern, bits 5....9 and 11...15: two clock adaptation commands, each for the fast bit stream 01 and, respectively, slow bit stream 02 which are transmitted alternately in the synchronous case, and bits 10 and 16 respectively: transfer of the significance of a bit transmitted in the fast bit stream and, respectively, slow bit stream in the case of a positive clock deviation or signalling of alarm in the case of a negative clock deviation of the respective bit stream 01 and 02. <IMAGE>

Description

10th or 16th bits Acceptance of the value of one in the high-speed bit stream or bits transmitted in the slow bit stream in the case of a positive clock deviation respectively.

Signaling of alarms in the event of a negative clock deviation of the respective bit stream 1 or 02, 2nd frame structure according to claim 1, thereby characterized in that at a clock speed of 68 736 kbit / s for the fast Bit stream # 1 with a permissible clock deviation of # 1 # 10-6 and a permissible Clock deviation for the slow bit stream # 2 from # 65 # 10-6 the absolute clock deviation of the multiplex signal may be + 8.195 kHz, 3. Frame structure according to claim 1, characterized in that at a clock speed of 68 734.375 kbit / s for the fast bitstream # 1, clock tolerances retained and only more positive Clock adjustment the absolute clock deviation of the multiplex signal # 1.608 kHz allowed.

4. Frame structure according to claim 1, characterized in that at a clock speed of 68,750 kbit / s for the fast bit stream Clock tolerances and frequent negative clock adjustments the absolute clock deviation of the multiplex signal 9 may be 19995 kHz.

DE-PS 25 27 481 is a frame structure for a non-hierarchical Multiplexer known, which is used to combine plesiochronously operated digital time division multiplex subsystems with different bit rates that cannot be derived from one another by division target. For this purpose, the distance between two sync words with 16 bits each, always 8. k bit chosen, being in the middle of the frame formed in this way according to 4. k bit a time channel of 8 bit for recognizing the Clock adjustment information from a maximum of two subsystems with a comparatively high Bit rate is kept free, and when wired with subsystems different and / or lower bit rate are 6 more at equidistant intervals of k bit each Time channels with different depending on the number of za unifying subsystems Bit number provided.

With an output bit rate of approx. 69,000 kbit / s and a frame length from 8. k = 8,368 bits can either be 8 subsystems, each with 8 448 kbit / s or 4 subsystems with 8 448 kbit / s and one subsystem with 34 368 kbit / s or 2 subsystems with 34 368 kbit / s each to form a secondary time division multiplex system be united. The bit rates of the signals to be combined are the worst Fall in a ratio of 34 to 8, so from a little over 4. In the invention on the other hand, the bit rates of the signals to be combined differ by about Factor 68 to 2, i.e. about 34, as shown in the following task of Invention emerges0 Such a large ratio of the bit rates to be merged can only be achieved insufficiently with the known frame structure comes9 that the signals to be combined not only have a different bit rate, but also have a very different clock tolerance.

Task: The invention is based on the task of two signals different bit rate (68 736 kbit / s and 2 048 kbit / s) with different relative clock tolerance (+ 1 # 10-6 for the fast bit stream of 68 736 kbit / s, or + 65, 10 6 with a slow bit stream of 2 048 kbit / s) to a multiplex signal if possible to summarize low clock frequency, with the multiplex clock to be complied with Cycle tolerance is to be determined. The fast in the clock speed at 68 736 kbit / s input signal should either be a TV program or two Audio broadcast multiplex signals of 34 368 kbit / s each, which are synchronous with each other and can therefore also be nested synchronously. Solution: This task is achieved by the frame structure specified in claim 1, which in claim 1, the solution to the above-mentioned problem is derived from the following considerations from: 1, Determination of the clock frequency of the multiplex bit stream: The multiplex clock frequency should be divisible by 64 kHz without a remainder and at least the sum of two 34 568 kbit / s signals and a 2 048 kbit / s signal, for synchronization and clock adjustment tasks 256 kbit / s are additionally provided. This results in a nominal frequency for the clock rate of the multiplex signal of 71 040 kHz. This value is likely with regard to the requirements of fiber optic transmission technology in particular are the utmost minimum in view of the sum of the given input signals, 2, structure of the Impulse frame: The impulse frame should be chosen so that a later possible synchronous operation Simplifications in the signaling allowed by clock adjustment can then be dispensed with. However, this means that initially the use of a positive-negative clock adjustment a plesiochronous operation of the network.

The invention is explained with reference to FIGS.

1 shows the frame structure, FIG. 2 shows the nesting, and FIG 3 shows a circuit arrangement for clock recovery in the demultiplexer.

In Fig. 1 is the structure of the pulse frame for a multiplex signal, consisting of two bit streams 1 = 68 736 and # 2 = = 2 048 kbit / s, shown. A Frame is 4,440 bits and repeats after 62.5 µs, i.e. the frame rate is 16 kHz, 3. Use of the additional bits: To synchronize the lemultiplexer the first 9 bits are used in each frame. The first 4 bits a defined synchronization pattern, e.g. 1010. The next 5 bits change, depending according to the conditions that the clock adjustment requires for the fast bit stream 01, between two possible patterns, e.g. 10111 and 01000.

This method is known (see Review of the Electrical Com. Laib. Vol. 19, 9-10, 1971, pages 1055 to 1059) and does not require a large additional Circuit effort in the receiver. The tenth bit is used in the event of positive clock deviations the fast bit stream from the setpoint to carry additional bits (negative clock adjustment), or in the case of negative clock discrepancies in the fast bit stream for signaling Alarms, as is known from DE-OS 28 14 351. The remaining 6 additional bits are used exclusively for clock adjustment signaling for the slow bit stream 2 is used, with bits 11 to 15 for signaling clock adjustments that have been carried out and the 16th bit is the value of a bit taken from the bit stream for takes over the case that the clock deviation of the slow bit stream is positive (negative Uakt adjustment) O Here, too, the last (16th) bit is used to signal alarms free if the slow bit stream delivers too little data relative to the multiplex clock (positive clock adjustment). The clock matching circuits for both Input signals signal the synchronous state by changing the pattern for positive and negative clock adjustment are sent alternately. In these cases can be used to transfer data bits in the positions provided (10, and 16th bit), as well as the insertion of bits without meaning at the agreed point must be transmitted in the impulse frame can be dispensed with.

4. Distribution of the bits from the two input signals in the frame: Off Fig. 1 shows that a sequence of 537 bits originating in the fast Bit stream p1, and the 16 bits, which the slow bit stream 2 delivers, a block represent, which follows the 16 additional bits described above and a total of 8 times lined up results in the entire frame, in Fig. 2 is the Distribution of the bits of the two bist streams shown in the multiplex frame.

First 9 bits of the fast bit stream are used for interleaving 1 is sent and then 16 sectors (1 + 33) bits are sent, with 1 bit each of the slow bit stream 2 are interleaved with 33 bits of the fast bit stream 1. One of the first 9 bits of the fast bit stream can be used as a possible blind bit immediately after the 16 additional bits and the 1st bit of the slow bit stream (i.e. the bit with position 10 in the frame).

Further features of the invention: 1. Clock tolerance for the multiplex clock: Under the conditions already mentioned above for the permissible clock deviations the bin to be nested streams from + 1. 1016 for 68 736 kbit / s and from + 65 + io6 for 2 048 kbit / s as well as from the described pulse frame, the maximum one Allows clock correction in every 2nd frame, i.e.

has a maximum clock adjustment rate of + 8 kbit / s, results themselves a value of + 115.57 for the relative clock tolerance of the multiplex bit stream. 106. This value is essentially determined by the clock tolerance of the television signal and is so uncritical that it can be adhered to without difficulty, the absolute Clock deviation can then amount to + 8.195 kRz.

2. Changes in the clock frequency for the television signal Simplifications when implementing the nultiplex system are possible if the clock frequency for the television signal to be multiplexed is only 68 734.375 kbit / s. Without change of the proposed pulse frame can then dispense with the negative clock adjustment and the adaptation in alternation between the full use of the designated spaces for the television signal and the insertion of dummy bits (positive clock adjustment). Since here too the clock of the television signal has an accuracy of + 1 k 10-6 should have, the clock rate of the multiplex signal would have to be relative + 22.6 s 10'6, that is, absolute to + 1.608 kHz are maintained.

It is also possible to use a clock frequency of 68,750 kbit / s for the television signal. However, the one in the additional bits must then be used relatively often designated space (additional bit no. 1 o) occupied with information from the television signal (negative clock adjustment) and only rarely does this 10, additional bit for the Transmission of alarms will be available, on the possibility of signaling positive clock adjustments must be dispensed with for reasons of time, i.e. the synchronous operation can also be ruled out here.

Assuming a relative timing accuracy for the television signal from + 1 e 10-6 the multiplex clock must be relatively + 28 S 10 6, i.e., absolutely to + 1.995 kHz are adhered to.

3 shows a circuit arrangement for clock recovery in the demultiplexer. The multiplex clock with a clock frequency of 71 040 kHz is in a first divider stage divided by 5 and in a second division by 37. In one Phase comparator PK, this cycle is compared with a cycle that is determined by a divider (179/1) is obtained, the clock coming from a voltage-controlled oscillator VCO divides from 68 736 kHz by 179, the phase comparator is followed by a low-pass filter, via which the voltage-controlled oscillator VCO is set. The one at that Output available clock frequency has nominal due to this phase-locked loop a value of 68 736 kHz, but has a fixed frequency ratio to the multiplex clock of 71 040 kHz and also follows its clock deviations.

By receiving clock adjustment signals, the demultiplexer the correction signals required for clock recovery (K1 + or X1 - for the Clock of the fast bit stream # 1 and K # 2 + or K # 2 - for the clock of the slow one Bitstream 2) determined.

With the help of devices referred to as pulse adapters PA from a regular cycle when the corresponding correction signals (K # 1 + or K # 1 - and K2 + or K # 2 -) individual clock pulses are faded out, which means on average a decrease in the clock speed is achieved. If a Clock adjustment made by adding a dummy bit at an agreed point in the pulse frame (i.e. one bit without meaning) is inserted, this is done with 5 bits each (i.e. redundant) in two consecutive frames for bit streams 1 and 2 signaled independently to the demultiplexer, this becomes the correction signal for bit stream # 1 gal + won, the clock rate reduced in speed in the pulse adapter PA is fed to a second phase comparator Px, at the second input of which the from a second voltage-controlled oscillator VCO coming clock of 68 736 kHz The output of the second phase comparator PK supplies signals via a second Low pass to the control input of the second voltage controlled oscillator VCO, The clock frequency available at the output of the second voltage-controlled oscillator VCO is increased in this second phase-locked loop when correction signals Ep1- using of the second pulse adapter PA clock pulses from the second entry the clock supplied to the second phase comparator PK, this must then be done if a clock adjustment has been made in the multiplexer, in the 10th position the additional bits a data bit of bit stream 1 was transmitted (negative actual adjustment), For the clock recovery of the slow bit stream # 2, the one from the divider is through 37 is fed to a further divider, which divides by 3. This through 3-divided clock is fed to a third phase comparator PK, to its second Input the clock divided by 16 from a third, oscillating at 2 048 kHz voltage controlled oscillator VCO is performed. This third phase-locked loop consists of the third phase comparator PK, a third low-pass filter, the third voltage controlled oscillator VCO for 2 048 kHz and the clock divider 16/1 in the Return.

At its output there is a clock rate of 2048 kHz, which is also the is in a fixed frequency ratio to the multiplex clock of 71 040 kHz and its Clock deviation follows, similar to that for the fast bit stream 1 is in a fourth Phase locked loop with the help of the correction signals E2 + or ga2- for the other Processing in the demultiplexer recovered the necessary clock for bit stream # 2. Two pulse adapters PA, a fourth phase comparator PK and a fourth are used for this purpose Low pass and another voltage-controlled oscillator oscillating at 2 048 kHz VCO.

Achievable advantages: With the help of the proposed multiplex frame two signals with very different bit rates can be interleaved without that the two signals to the clock of the multiplex system in a rigid frequency relationship must stand, so that a national long-distance network can be operated without the problems of a synchronous network have to be solved right from the start.

L e r s e i t e

Claims (1)

Suitable for multiplexing signals with very different bit rates Frame structure (4) Claims for the multiple formation of very different signals Frame structure suitable for bitrate, with one of both the synchronization and the the signaling of clock discrepancies serving additional information of 16 bit am Start of the frame and a breakdown of the following information into 8 equally large Blocks d a d u r c h e Ir e n n z e i c h n e t, d a ß a) for multiplexing a fast bit stream # 1 of approx. 68 734 to 68 750 kbit / s with a slow one Bit stream 2 of 2 048 kbit / s to a multiplex bit stream of 71 040 kbit / s the 8th Blocks each 537 bits of the fast bit stream 1 and each 16 bits of the slow one Bitstream 2 contain (Fig. 1), where b) within each block after 9 bits of the fast one Bit stream 1 in 16 sectors each 1 bit of the slow bit stream # 2 with 33 each bits of the fast bit stream 1 are interleaved (Fig. 2), c) as possible dummy bits one of the first 9 bits of the fast bit stream 1 and the first bit of the slow one Bit stream 2 are provided (Fig. 2) and that d) the 16 bits of the additional information have the following tasks: 1st to 4th bit: fixed synchronization pattern, 5th to 9th or 11th to 15th bit: two act adaptation commands each for the fast bit stream 1 or slow bit stream 2, which are transmitted alternately in a synchronous bounce, and the For multiplexing signals with very different bit rates Suitable frame structure Area of application: When connecting subscribers via fiber optic cables (LWL) at control centers or network nodes, television and audio broadcast programs, video telephony signals, Telephone and data signals are transmitted in a common multiplex bit stream. The invention seeks to provide a time division multiplexed framework for what is initially presented Case of a plesiochronously operated digital network in which the telephone and data signals neither synchronous with the image signals transmitted by the television services, nor to the video telephony signals. Purpose: With such multiplex bit streams, the possible tolerance ranges are for the clocks of the signal flows to be transmitted with the help of clock adaptation methods to be balanced in such a way that trouble-free operation is possible in any case, Several such signal flows can then be used in a synchronous multiplexer summarized and transmitted to the subscriber via fiber optic cables. State of the art: In previously known multiplexing methods several (n) normally equally high signal flows to a bit stream approximately n-fold Clock speed combined with a few additional bits for transmission of synchronization and timing adjustment signals can be inserted. This multiplex method relate to input signals with the same bit rate and clock accuracy. The number the input signal n is constant for each multiplex system and amounts to 3 to 30 in multiplexing for standardized systems, the Uakt adjustment method are positive, positive-negative or positive-zero-negative clock adjustment into consideration,