DE3141451A1 - Data processing system - Google Patents

Abstract

A data processing system having a virtually addressable central memory contains an access manager with a buffer memory (PSP), the cells of which in each case have a position for a bit, which position is cleared with a program change. After a buffer memory cell with a cleared valid-bit position (GB) has been accessed, the virtual page address (VSE) is used as subaddress for accessing the translator table contained in the central memory (HSP), and the content of the addressed central memory cell is transferred into the buffer memory cell and the valid-bit position is set. When a buffer memory cell with a set valid-bit position is accessed, the page number (SNR) and the location number (PLN) contained in this buffer memory cell is used for forming a real central memory address. The main application is the virtual addressing in process computers. <IMAGE>

Description

Data processing system

The invention relates to a data processing system with a processor, a virtually addressable central memory and an access manager consisting of virtual page addresses and place numbers existing addresses in real addresses converts it and feeds it to the central store, which contains a buffer store, in which one of several, contained in the central memory, each a program or Translation tables assigned to the program section can be saved, whose Address input the virtual page addresses are supplied and the after supply a page base address of a virtual page address from the addressed memory cell outputs which, together with the location number, is the real address for the central memory forms.

Such data processing systems that z. B. in magazines ~ Electronics ", August 11, 1981, pages 119-127 and" Computer Design ", July 1981, Pages 151 to 156 are described have the disadvantage that with a program change the entire translation table assigned to the following program in the buffer memory must be transferred, although often the entire translation table is not needed will. In the case of process computers, this means that process switchovers take a long time to take.

The present invention is based on the object of the data processing system to improve according to the preamble of claim 1 to the effect that the middle Access time to the main memory is shortened and the program switching speed is higher is achieved.

According to the invention, this task with the in the characterizing part of claim 1 specified measures solved.

So after a program change, only the respective The required line of the translation table is transferred to the buffer memory so that processing of the new program started immediately after a program switch can be. Used once while editing a program Line of the translator board needs a second or more time, it can be done immediately can be taken from the buffer tank. So it will be from the translator boards only transfer as many lines into the buffer memory as for the respective processing of the programs is necessary.

Based on the drawing, in which an embodiment of the invention is shown, the invention and other advantages and additions are shown below described and explained in more detail.

PR denotes a processor that outputs virtual addresses, which are converted by an access manager into real addresses for a main memory HSP will.

The access manager is not indicated separately in the drawing; With the exception of the processor PR and the main memory HSP, it consists of the in of the figure drawn structural units. The virtual ones issued by the processor PR Addresses consist of a virtual page address VSE and a location number PLN. They are entered in a register VAR for virtual addresses. From this register the virtual page numbers VSE are a register or a driver unit UAR supplied for the translator table addresses, with a base address BUT for the Translator panels is added. Furthermore, the virtual page numbers arrive VSE to the address input of a buffer memory PSP, which is dimensioned so that one of the over- setter boards can be completely transferred to a 13 area. The buffer storage PSI> also has an area GB in which the individual lines of the a valid bit can be added to the saved translation table. With the start of a program or a program change, all valid bits are set to log. "O" set.

Furthermore, the processor PR in the register or the driver unit UAR entered the base address of the translator table valid for the program. I3 for example this base address should be b The first virtual address issued by the processor contain the virtual page i. This is used as the address for a read process Buffer memory PSP supplied. Since all valid bits are on log. "O" are set a valid bit control GBS log. HOMO This then switches a multiplexer MUX in the position in which it connects the output of the register UAR with the address input of the main memory HSP connects. The address "b + i" is therefore supplied to this, which refers to line i of the translation table in area UT2.

This line is read out and is sent to a DMX demultiplexer, which log because of the valid bit. "O" switched in this way by the valid bit control GBS is that the data read out from the main memory HSP is transferred to the buffer memory PSP arrive, the address input of which is still supplied with address i. Of the The contents of the main memory cell "b + i" are thus transferred to cell i of the buffer memory PSP accepted. At the same time, the valid bit of line i is set to log. "1" is set. It the signal state shown in the figure is thus set. Now is again made a read attempt in which, since the valid bit was log. "1" is the multiplexer MUX connects a driver RAR to the address input of the main memory HSP. In the driver RAR is read out from the cell i of the buffer memory PSP Real page number SNR added to place number PLN and the result as real Address supplied to the main memory HSP. Since the demultiplexer DMX because of the valid bit log. ~ 1 "is toggled the content of the so addressed Main memory cell to processor PR. In this way you can gradually the required lines of the translation tables contained in the main memory area UT2 be transferred to the PSP buffer memory. Used during a program accessed the same line for the second time, e.g. B. on a line i so receives the valid bit control GBS the signal log. "1" so that the RAR in the driver immediately The real address formed is switched through to the main memory HSP and the thereby read out Data are transmitted to the processor PR.

The next time the program is changed, all valid bits will be in the buffer memory again PSP on log. "O" is set and a new base address for the one assigned to the new program Translation board entered in the UAR register. A program luxury switch that in the case of a process computer, a process switchover can therefore be carried out in the shortest possible time Time to be carried out.

3 claims 1 figure

Claims (3)

Patent claims data processing system with a processor virtually addressable central storage and an access manager consisting of virtual Page addresses and location numbers converts existing virtual addresses into real addresses, this supplies the central memory and which contains a buffer memory in which a of several, contained in the central memory, one program or one program section each assigned translation tables can be saved, whose address input the virtual page addresses are supplied and the after supply of a virtual Page address outputs a page base address from the addressed memory cell, which, together with the Platzriummer, forms the real address for the central storage facility, characterized by a) the buffer memory cells each have one valid bit position which is deleted when changing programs; b) after access to a buffer memory cell with a deleted valid bit position takes place with the virtual page address as Partial address access to the translation table contained in the central memory (ZSP), and the content of the addressed central memory cell is stored in the buffer memory cell transmitted with the valid bit position being set; c) when accessing a buffer memory cell with a set valid bit position becomes with that in this buffer memory cell The page base address and the location number contain a real central memory address formed 2 data processing system according to claim 1 d a d u r c h g e k e n n z e i c h n e t that a multiplexer (MUX) is available, which depends on the Valid bits is controlled in such a way that when the valid bit is set, the bits from the buffer memory (PSP) read-out page base addresses (SNR) and formed from the location numbers (PLN) real central memory addresses to the address input of the central memory (HSP) switches through and there he is when the valid bit is deleted from the virtual page addresses (VSE) and base addresses (BUT) for the converter tables for address input of the central memory (HSP). 3. Data processing system according to claim 1 or 2, d a d u r c h it is not indicated that a demultiplexer (DMX) is available which is used in Dependency of the valid bit is controlled in such a way that when the valid bit is set the data read out from the central memory (HSP) to an outside of the access manager located unit (PR) and that he switches off the valid bit when the valid bit is cleared data read out from the central memory (HSP) to the buffer memory (PSP).