DE3138974C2 - Circuit arrangement for processing memory operands - Google Patents

Abstract

The output register (REG A. aligns longer memory operands depending on the type of instruction to the left or right double word boundary of the processor-memory interface. In addition, a bank selection / sign generator (BSVZG) is provided downstream of the byte alignment shift network, which replaces bytes 0 and 1 with sign bits and non-relevant bytes of half-word and longer memory operands with zeros in half-word operands.

Description

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Form the arithmetic unit in such a way that the opera- In normal case, the desired byte group, the

The alignment can be carried out depending on the command type with a processing step in the 8 byte wide Re- and that any after alignment not relevant and processing AL t / is to be processed with a read so that redundant byte positions can be easily decoded from the addressed buffer block. ₅ can be taken. If the one requested by the processor

With a byte block circuit arrangement with 2 to 8 bytes, this task is made up of 2 in the working order initially mentioned type comes according to the invention with the memory adjacent 16 byte blocks, d. H. in the characterizing part of claim 1, a 16 byte limit is exceeded, a double to be given Features solved Accessed in the buffer memory or working memory necessary,

An advantageous further development of the invention is io, the following variants being possible: Claim 2 stated.

The following is an embodiment of the invention - two read access in the buffer memory Training explained in more detail with reference to the drawing - first access in the buffer memory, second access in

The block diagram shown in the figure includes main memory

for the understanding of the subject matter of the application 15 - first access in the main memory, second access necessary functional units of a data processing in the buffer memory

processing system, in particular a circuit arrangement - two read access to the main memory for preparing memory operands. She shows im

individual one integrated in the preparation processor To avoid this double read access,

Address buffers with the address registers P, PFA and PFjB, in FIG. 20, are between the buffer memory A output registers to which the REG A ... D necessary for command read-out and the bank selection multiplexer BAM addresses are provided. These Adrp.8register each byte alignment shifting units BAR A ... D are switched on via an address bus ADR-BUS with a memory, which connects the memory operand command type checker address register MAR , in which the align for pending so that in each case only one only the next access to the working or buffer memory 25 data transfer is temporarily stored via the address required for the buffer memory processor. Since the interface is required and thus the micropro data processing systems with virtual addressing program in the processor does not have to be branched. The so-called page address mii bits 8 to 20 to-control Byteausricht-displacement units BAR next in virtual form is present, a memory access via the address bits 28 to 31 as well as a but only with a physical address carried out 30 type of command signal BTYP, wherein in can be as follows, the virtual address component must first be considered in command types: a real, physical address must be translated. to

for this purpose sin partially associative address translation register register commands RR

Zungsspeicher ATM provided for virtual register memory commands with

Addresses the corresponding physical page 35 indexing option RX

address part provides With the now in all parts register storage commands RS

The real address can now be used both for the buffer memory and direct memory operand commands SI

CA and the main memory ASP can be accessed memory memory commands SS

the. The memory access usually works like this

in front of you that with the low-order bits of the address provided in the memory 40 The abbreviations: cher address register MAR, ie

with the so-called class address, in an address R: the register address of an operand, senpuffer ADRM a page address is selected, X: the index register address of an operand with the higher-order bits of the direct operand register MAR contained in the instruction Address is compared. 45 S: the memory address of an operander. This address comparison takes place in a comparison circuit connected downstream of the ADRM address memory. With RX, RS, SI and logical SS commands, COM takes place, which controls the alignment of the addressed byte block to the internal HIT A .. if both addresses are the same. . D delivers indicating that the ke double word boundary, so that the addressed byte in the addressed data in a data buffer banks Bk byte position 50 appears to 0, and the remaining bytes of the buffer memory is available CA a ... D. Connect on the right if necessary. If there are decimal SS commands that do not have the same address, there is a read access to the ASP memory operand at the right double word boundary. In order to keep the access time short so that the addressed byte in byte position 7 is running, the processes appear and the associated bytes are followed on the left by "address translation," and "read access to buffer memory." Finally, in the case of AX half-word commands, the 1-byte operand addressed with the address bits 8 to is aligned in such a way that the one line in the address translation memory A TMgele addressed byte in byte position 2 and the corresponding while the associated byte appears in position 3 with address bits 18 to 27, related entries from the address memory ADRM and after expiry of the "read access" to the buffer memory and from the buffer memory databases Bk-A ... D - 60 of the time required for the Ryte alignment are these. Comparison circuit COM control signals HITA ... Dan The read data are sent via a buffer each from the bank selection multiplexer BAM , so that the out-of -memory output register REG A ... D is sent to a specific memory operand for byte selection / sign bank selection. Multiplex BAM, which can be switched through depending on the BSVZG chen generator. Control signal HITA ... D the respectively responsible bank 65 With the help of this generator RSVZG the memory selects and the requested data for the arithmetic operand fills unused bytes with zeros stored ALU of the instruction processing processor. In addition, switching is provided for half-word operands. that in bytes 0 and 1 sign bits with the respectively

most significant bit position of byte 2 (bit 16) must be entered.

An address adder SRADD is also provided in the instruction processing processor, which, depending on the respective instruction type, adds the memory operand length OPL to the memory address in the case of left alignment or subtracts it from the memory address in the case of right alignment and temporarily stores the new address in a subsequent address register NEA . If this address adder SRADD reports at the transition from bit position 28 to bit position 27 a carry of value = 1 with left alignment and a carry with value = 0 with right alignment, then the signal SRO indicates that the memory operand has exceeded the 16 byte limit Has. At the same time, a second read cycle is initiated in the buffer memory or working memory. The bytes from the first and second read processes are then combined in the bank selection multiplexer BAM .

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Memory operand length OPL and, depending on the command type, a total of 8 bytes select control signals RYSEL O ... 7 formed. Each control signal is assigned to a byte position of the processor buffer memory interface and, if necessary, causes the relevant byte to be masked out by inserting zeros in the byte selection / sign generator BSVZG. In addition, in the case of a half-operand that has the sign bit in the most significant bit (bit 16), bytes 0 and 1 in the BSVZC generator are padded with this sign. With a plus sign (bit 16 = 0) this means that the zeros generated via the byte selection control signals BYSEL O = 0 and BYSEL 1 = 0 are retained, while with a minus sign (bit 16 = 1) be inverted.

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Claims (2)

1 2 directions known In addition to processors with purely patent claims: sequential command processing, processors with overlapping command processing are also known 1. Circuit arrangement for processing The second group includes so-called assembly line memory operands for commands with different processors, whose structure z. B. in the magazine chem Format, in a data processing system "Electronic Computing Systems", 1973, pages 60 to 65, with an instruction processing processor for reading and reading in the article "Possibilities of accelerating eifehlslesen, address calculation and memory operands of the central unit through structural measures" an instruction execution processor for writing iit in a pipelined arithmetic unit is the actual instruction execution, as well as a PUF 10 execution of instructions in a plurality of ^INHERIT: tungsferspeicher wide with an associated address buffer and steps disassembled, in specialized Fließbandstatiomit one in η equal size, each 16 bytes be executed. In this way, data buffers subdivided into several banks and the commands on the output side can be processed in a temporally overlapping manner. The multiple throughput of a bank or the main memory now depends essentially on whether it is possible to succeed in the execution of the commands in such processing cycles, with the data transfer between the buffers being broken down approximately the same amount of time consuming memory and the double-word-wide arithmetic unit. Bottleneck is the last assembly line station, which is responsible for the command execution processor over the respective command execution. Due to output registers, downstream byte outputs of the relatively different commands are usually required more straight-shift networks on the one hand and between 20 cycles than in the previous stations
see buffer memory and main memory of others- In addition, assembly line arithmetic units require on each side on β-byte-wide data paths, there is a cycle or a great deal of control information per microinstruction, characterized by the fact that the byte- tion. For this reason, in known assembly-line alignment-shifting networks (BAR-A, B, C, D) computers, a hard-wired embodiment using the four multi-valued bits (28-31) is preferred If computers require very wide microinstructions (e.g. 100 to 150 bits) instruction type signal (BTYP) identifying the wrong type , the number of microinstructions must be limited in such a way that halfwords are stored, because otherwise they are very fast and This means that expensive processor operands must be used in left alignment on bytes 2 and 3, and longer memory operands each type of instruction.30 Likewise, the number of dynamically loop-dependent microinstructions (cycles) per machine instruction must be used to display the procedural memory, depending on the left or right double word bounding the left or right double word -Interface aligned etz- the demand for as few cycles as possible in the last plant (BAR-A, B. C, U) in one direction to the banked assembly line stage should be kept small. selection and generation of certificates (BSVZG) 35 An essential measure to relieve the last is connected downstream, which, controlled by the assembly line station, consists of processing the type signal (BTYP) and one from the memory operand memory operand in a preceding, usual- the length (OPL) by- mode dependent on the command type in the penultimate assembly line station. Next to the te-select-control signal (BYSEL 0 ... 7), of course with half-time with a conveyor arithmetic unit word operands in bytes 0 and 1 each Chen bits and in non-relevant bytes of half-word preparation, the following measures must be taken:
and longer memory operands each have zeros puts. - Alignment of the memory operands with one another, 2. Circuit arrangement according to claim 1, because the same with memory memory commands to bedurch characterized that in the command preparation 45 byte limits in the main memory are processor an address adder (SRADD) can be provided so that a direct link is in the de, which, depending on the respective command type, the chenwerk is possible, Memory operand length with left alignment to - Alignment of the memory operand to the regi- the memory address is added up or, in the case of right out-of-order operands, for the same reason direction subtracted from the memory address, as well as 50 - assembling of 1 to 8 byte long blocks, evaluates the new address in such a way that an at if the bytes in working memory in neighboring Left-aligned carry with which 8 byte blocks are Value 1 or a right-hand alignment - replacement of the redundant bytes in the 8-byte block Carry over with the value 0 an exceeding of the through zeros 16-byte limit on the part of the memory operand - 55 - Special preparation of half-word operands
and another read cycle in the buffer or Working memory (CA or / ISP ^. DE-AS 28 06 452 already has a circuit arrangement for processing memory operands using a move network 60, in which the second operand is derived depending on one of the addresses of the two operands. The invention relates to a circuit-related offset code which determines both the interleaving for preparing memory operands for exercise size and the direction in which errors with different formats are aligned according to the first operands,
paint the preamble of claim 1. 65 The present invention is now based on the task for the central units of commercial data processing, a data processing system working in assembly line technology, depending on the performance class processing system with byte alignment shifting, different structures for the processing networks between Main or buffer storage and