DE3137620A1 - A method and apparatus for synchronizing a binary data signal - Google Patents

Description

Translation of the letter from Telefonaktiebolaget L M ERICSSON an

Patent-Och Registreringsverket, Stockholm which filed January 11, 1982 with new claims has been:

PCT application no.PCT / SE81 / 00075 - LM 4136

System:

new claims

Referring to the decision from the international Authority of December 4, 1981 regarding the above-mentioned case, we would like to comment as follows:

We agree that DE 28 36 422 shows an apparatus in which a data signal is first corrected with a phase Clock signal and then clocked with an uncorrected clock signal.

However, as can be seen from the claim, lines 3 to 4, reference is made here to a device for synchronous data transmission, ie the so-called external clock signal has the same frequency as the data signal.

In the device according to the present invention, however, it is assumed that there is a frequency difference between the data and clock signals which causes a mutual drift in the phase positions of the two signals. We have an asynchronous data transmission, see e.g. page 3, sentence 2.

According to the citation DE 28 36 422, an internal clock signal T4 is derived from the data signal,

3137S20

which clock signal has no equivalent in our device. Next is according to the German citation a conventional phase comparator with a low pass filter in the output, which means that the phase of the clock signal is not switched instantaneously can be if the phase condition is satisfied.

When it comes to the intervals of the phase differences, in which the clock signal is inverted or remains unchanged, there is another very clear difference compared to what is shown in DE 28 36 422. The phase angle interval in which we do not have any inversion must be greater than 90 with margin. In fact, it is the length of the output pulses from the Circuits 7 which determine the interval in which we have inversion. Here it is essential to have a good margin to have 90 to avoid swinging.

We would like to comment on JP 54-51710 as follows:

The device, like the German citation mentioned above, is evidently designed for synchronous data transmission. The two flip-flops are clocked at two different frequencies (the signals S6 and S1), one of which is a multiple of the other and not, as in our case, a phase-corrected version of the other.

In our opinion, the new claims define one Invention which is patentable with regard to the state of the art shown.

Telefonaktiebolaget LM ERICSSON
Patentavdelningen

Lars-Erik Johansson

35 640

Method and apparatus for synchronizing a binary data signal

Field of invention

The invention relates to a method and an apparatus

for synchronizing a binary data signal that reaches a receiver with a clock signal provided in the receiver.
15th

The binary data signal can be a so-called RZ signal (Return to zero) or a so-called NRZ signal (no return to zero).

State of the art

The synchronization problem occurs with rapid data transfers and, depending on the application, becomes a requirement for accuracy etc. solved in different ways. If z. B. synchronized on the transmitter and the receiver side ^ aktsignale are, if possible, compared to a common reference value, then of course ascertaining or locating of data on the receiving end is not a problem. The synchronization of a receiver clock signal can with done in a manner that the timing information is extracted from the transmitted data signal will, e.g. B. by determining the time of their zero crossings, whereupon a signal corresponding to the timing information can operate a controllable, receiver-side clock signal generator. Requirements regarding Transition time and permissible errors in data transmission naturally also influence the selection of the Synchronization procedure.

Statement of the invention

The technical problem in the present case lies in the correct finding of the message transmitted to the receiver with the aid of a signal that becomes the data signal is asynchronous, provided that the addition or removal of a binary character in the message does not have any Has an impact. This condition is e.g. B. met in a redundant system in which the same message a fixed number of bits is repeatedly sent one after the other and .the receiver records under the condition, that he can determine the same message a certain number of times during a given time. If the addition or removal of a binary sign occurs relatively infrequently in the data signal, then such occasional occurrence becomes the correct determination not affect the message on the receiving end.

The clock signal, which is asynchronous, need not necessarily indicate that too great a frequency deviation from the correct value is available. According to the invention, there is a frequency deviation on the order of 1/1000 Reason for adding or removing information in approximately every thousandth bit position, which in many Use cases can be accepted.

The solution to this problem proposed by the invention is in the appended claims characterized. The first advantage associated with the apparatus of the invention is its ultimate Simplicity and the very low power requirement.

Brief description of the drawing

The invention is now based on a few exemplary embodiments with reference to the / '■■ ichm- ■■■ · .: described in the

FIG. 1 is a block diagram of an apparatus of the

Invention represents. Fig. 2 is a phase reversing circuit included in the apparatus of Fig. 1. Fig. 3 is a first sampling circuit shown in Fig

Apparatus according to Fig. 1.
Fig. 4 shows the timing of several signals in the apparatus of Fig. 1; and

FIG. 5 shows the same signals as FIG. 4 for another embodiment example.

Best way for carrying out the invention

Figure 1 shows a block diagram of an inventive Apparatus. A first sampling circuit 1 is located between a data input 4 and a data output 6 and a second sampling circuit 2 connected in series. A phase reversing circuit 3 is between a clock signal feed 5 and the clock signal input to the first sampling circuit 1 are inserted. The second The sampling circuit 2 is acted upon directly by the clock signal feed 5. The data signal transmitted by the transmitter is fed to data input 4. It is assumed here that it is a binary-coded signal of the RZ or NRZ type acts as mentioned above. The data signal is transmitted to the clock feed 5 with the aid of the clock signal sampled, the clock signal being asynchronous with respect to the data signal according to the assumptions, so that on Data output results in a signal that is synchronous with the clock signal and that corresponds to the input data signal.

The phase reversing circuit 3, which will be described in more detail below, reverses the phase of the clock signal to the first Sampling circuit if as a result of the frequency difference 3 ^ between the data signal and the clock signal, positive and negative edges coincide in the corresponding signal strive.

In the preferred embodiment, the sampling circuits are 1 and 2 formed by ordinary D flip-flops triggered by positive edges. The clock signal assume a 50% pulse rate, and the input data should also be a signal of the NRZ type Act. In relation to these assumptions, FIG. 4 shows the time sequence for a large number of signals in the apparatus of Fig. 1.

Figure 2 shows an embodiment of the phase reversal circuit 3. The circuit has a data input 12, a clock signal input 11 and a clock signal output The exclusive OR gate 10 can be used as a controlled inverter circuit to be viewed as. If input 20 leads to zero, the clock signal from input 11 passes unaffected with the exception of a delay of no interest in this context. Two pulse shaper circuits 7 are with their inputs with the output of the exclusive OR gate or the data input 12 connected. They are designed so that they have a square pulse at their output of a certain duration when the input signal has a positive edge. The pulse length is low in relation to the digit time slot of the data signal in question. A coincidence detector in shape an AND gate 8, the inputs of which are connected to the outputs of the pulse shaping circuits, indicates its output from a pulse when the output signals of the circuits 7 overlap each other. One of those Coincidence pulse can be triggered by positive edges Clock D flip-flop 9, which is connected as a binary counter. The Q output of the flip-flop is connected to input 20 of the Exclusive-OR gate connected. This arrangement means that a small distance between a positive data edge and the edge of a positive clock signal the Reverses the phase in the signal at output 13 by 180 °.

In Fig. 4, the signal A shows the input data stream of NRZ type. This signal is thus using in the receiver of the receiver-side asynchronous clock signal B detected. The bit sequence for data is shown as constant, as well as the frequency of the clock signal. In general however, these quantities can also drift towards one another.

It is immediately apparent that it is not possible to do that Synchronize input data directly with the clock signal B. According to that described in connection with FIG According to the invention, positive pulses C are now generated when positive edges are detected in the input data A. will. Positive pulses D are formed in the same way when in the possibly out of phase Clock signal at the output of the exclusive OR gate 10 according to Fig. 2 positive edges are detected. For the positive edge that occurs first in the input data, if there is an overlap, coincidence is obtained between the positive pulses thus formed. This is through the pulse of the signal E is shown. As explained above, this pulse controls the phase reversal of the incoming clock signal which is fed to the input 11 according to FIG. Two more coincidences are in the signal E marked. The clock signal corrected by the phase reversal is represented by signal F. According to previous In embodiments, this signal represents the clock signal for the first sampling circuit 1. The output signal from this Sampling circuit is denoted by G.

According to the idea of the invention, this signal is now in the second sampling circuit 2 clocked with the aid of the unaffected clock signal in the receiver. That from the second sampling circuit originating output signal, which thus represents the synchronized data signal, has the designation H received. It can be seen that the second phase reversal of the clock signal leads to a deformation of the Data signal in such a way that one bit is added

becomes what is indicated by hatching in the figure. In fact, such a deformation occurs every second Phase shift of the clock signal. The asynchronous relationship is to explain the operation of the invention shown exaggerated, so that phase reversals follow one another very quickly. In actual use According to the invention, these phase inversions occur with a time interval that is several powers of ten is larger than shown.

In a second embodiment of the invention, the intended for input data in the form of a RZ type signal is, the first sampling circuit 1 is in the form of a simple D flip-flop by a circuit according to FIG Fig. 3 replaced. This circuit has a data input 17, a clock signal input 18 and an output '19, which leads to the second sampling circuit 2. The function of the circuit is described below with reference to FIG. 5, which shows simultaneous values of several signals in this apparatus.

The signal A in Fig. 5 showing the input signal to the first sampling circuit 1 is such an RZ-type input data signal. This signal is generated in the receiver with the aid of a synchronous clock signal B on the receiver side detected and converted into an NRZ signal synchronous with B.

The upper pulse shaper circuit 7 in Fig. 2 has, as before, for the purpose of generating a short positive pulse on the positive edge of signal A. Know the input signal is of the RZ type, one can perhaps judge that this pulse shaper circuit is not necessary, since the RZ signal consists of short pulses. In the event that the pulse sequence of the incoming RZ signal is extremely small or very large, however, this pulse shaper circuit is

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necessary. In the case described in FIG. 5, it is assumed for the sake of simplicity that the output signal from the pulse shaping circuit corresponds to the signal A, that is to say in this particular case the circuit is superfluous.

A delay circuit 14 is connected to the data input in the circuit of FIG. The delay is large compared to the delay of the D flip-flop 15, but small compared to the duration of the pulses from the circuit 7 in FIG. The delayed signal is shown at A ¹ . In the sequence shown in Fig. 5, the delay is irrelevant, so its function will be explained later.

The function block in FIG. 2 has already been described been. The signals D, E and F in FIG. 5 correspond to the signals with the same designation in FIG. 4.

20. When RZ pulses A 'at the clock input of D flip-flop 15 in Fig. 3 arrive, the flip-flop is in "ONE" state. Set, and the output signal at the Q output corresponds the signal T in Fig. 5. A fixed voltage corresponding to a logic value "ONE" is applied to the data input of the Flip-flop fed all the time. After some time, the flip-flop is activated by a signal at its R input reset, which comes from output 13 in Fig.2. This signal is denoted by F in FIG. 5. Detection and phase reversal in the event of coincidence between A and

^ O D prevent the flip-flop 15 immediately after or is reset at the same time as it is clocked. Coincidence occurs a sufficient time before the front Edges of signals D and A coincide, and coincidence produces signal E, which in turn Phase shift in signal D generated.

The signal D also has the purpose of clocking the flip-flop 16 in FIG. Since the time delay between the R and Q signals at flip-flop 15 is much greater than the time it takes for data to remain stable at the D input of flip-flop 16 , there is no problem in clocking data into flip-flop 16 before it disappears. This applies provided that the flip-flops 15 and 16 come from the same circuit family.

If there is no pulse in signal A, i. H. a logical "ZERO" has been sent, the Q input of the Flip-flops 16 to zero, with the result that a "ZERO" is clocked into this flip-flop. The signal G occurs at the output 19 of the flip-flop 16, and the signal H appears at the output of flip-flop 2 in FIG.

The notations P in the signal H in Fig. 5 indicate data errors. Both labels should have these Data to be "ONE". Regardless of which values signal A has in the corresponding times, the signal H for alternate pulses in signal E get a zero.

The identifier R in the signal H denotes an extra bit,

analogous to the hatched extra bit in FIG. 4. 25th

The necessity of a delay circuit 1 A ,, to use is clearly not immediately from the Fig. 5. The delay function is only required when the frequency of the clock signal B is lower than the bit frequency

of the data signal, d. H. for the opposite situation compared to FIG. 5.

Assume once that the clock frequency B is less than

is the bit frequency. It is further assumed that the Verge

delay circuit 14 is bypassed to start. The trailing edge of the pulses in signal D then gradually approaches the leading edge of the pulse in signal A.

In order to shift the phase of the signal D, the signals A and D must overlap somewhat so that the pulse E is sufficiently long. This situation immediately prepares the phase inversion problems because the D flip-flop is clocked while the signal at the R input. gear is "ONE".

By introducing the delay circuit 14 this problem is eliminated, since in this way a phase reversal is achieved before the positive edge of signal A 'and the negative edge of signal D match. A prerequisite is, of course, that the delay is long enough for the signal E to have the time Cause phase shift before the edges match.

Claims (5)

3137B20 35 640 PATENT CLAIMS 10 1. Procedure in a receiver for binary-coded Data signals for synchronizing an incoming data signal (A) with a receiver's own clock signal (B), characterized by the following steps: a) The data signal (A) is clocked with a phase-corrected clock signal (F), after which b) the resulting signal again with the un- corrected clock signal (B) is clocked. 20th 2. The method according to claim 1, characterized in that the receiver's own clock signal (B) is phase shifted by 180 ° to form the phase-corrected clock signal (F) when positive edges of the receiver's own clock signal (B) and the incoming data signal (A) due opposite drift come into agreement. 3. The method according to claim 1, characterized in that 30th that the receiver's own clock signal (B) phase-shifted by 180 ° is to form the corrected clock signal (F) when negative edges of the receiver's own clock signal (B) and the incoming data signal (A) seek to coincide due to mutual drift. 4. Device in a receiver for binary-coded data signals for synchronizing an incoming data signal (A) with a receiver's own clock signal (B), that is available in the receiver, marked by the following features: a) A first and a second sampling circuit (1,2), each with a data input, a data output and a Clock input, b) a phase reversal circuit (3) having a first and a second input and an output, the. The data input of the scanning circuit (1) represents the input (4) of the device and is intended to receive the data signal arriving at the receiver, and where 'its data output is connected to the data input of the scanning circuit (2), the data output of the scanning circuit (2) The output (6) of the device, and its clock input for receiving the receiver's own clock signal (B) and the first input of the phase reversing circuit (3) for receiving the clock signal (B), while the second input receives the data signal (A), and wherein its output is connected to the clock input of the sampling circuit (1) in order to supply it with a corrected clock signal (F) as a function of the relative position between the pulse edges of the data signal (A) and the clock signal (B). 5. Apparatus according to claim 4, characterized in that the first and the second sampling circuit by positive Edge triggered D flip-flops are.