DE3135136A1 - "CIRCUIT FOR MONITORING DMA CONTROL UNITS" - Google Patents

Description

Circuit arrangement for fault monitoring of

DMA control units

The invention relates to a circuit arrangement according to the preamble of claim 1.

DMA control units are known to be special LSI circuits, for the fast direct transfer of data according to the DMA (Direct Memory Access) principle between peripheral devices and storage units are used, for example, in one controlled by a commercially available microprocessor Telephone system. In such a system there is a problem that in the individual modular circuits errors that occur must be detected in good time so that they cannot reproduce. If z. B. the Microprocessor is provided for processing the coded fee criteria of the subscriber and during the processing If errors occur due to these criteria, the subscriber may receive an incorrect fee calculation. In which considered example, an error would propagate into the memory that contains the participants' calculation data contain.

The invention is therefore based on the object of providing a possible simple, inexpensive circuit arrangement to indicate the interference in one of the DMA control units notices and reports.

This object is achieved by the circuit arrangement characterized in claim 1. ' Since each of the DMA control units under consideration has both the data to be transmitted and the associated addresses managed, according to the invention, the parity bit of both the data and the addresses is checked. This can be reliable an alarm signal can be generated when the DMA control unit receives data information in the course of it performed read and write operation changed.

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The invention is explained in more detail below using a non-limiting exemplary embodiment. Show it:

FIG. 1 shows the circuit arrangement described here with the units provided for direct data transmission,

and

Figure 2 shows a preferred embodiment of a read-only memory ROM from Figure 1.

In FIG. 1, DMA ₁ DMA denotes a corresponding number of DMA control units which are used for the rapid direct exchange of data between the peripheral devices and the memory units. Each DMA control unit implements a route or channel for the transmission of data and is therefore permanently connected to a peripheral device or can be allocated to it on request. If the peripheral device wants to transmit data directly, it sends a signal dr to the DMA control unit connected to it, which in turn sends the microprocessor (not shown) a request character br for access to the data bus bd. The central processing unit (CPU) of the microprocessor allocates the data bus bd to the DMA control unit by generating a signal ba. Once it has been received, the priority or authorized DMA control unit can therefore begin direct data transmission.

Each DMA control unit carries out the data transfer (DMA cycle) in two successive phases. In the first phase it provides the address of the source in which the data to be transferred is stored. The data source identified by this address then sends the Data information stored by the DMA controller. In the second phase, the control unit sends the data and the address of the device for which the data is intended.

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Since a DMA control unit "manages" both the data and the addresses, the one described here performs Circuit arrangement a parity check of both the data. as well as the addresses. The data bus bd and the address bus bi are connected to the DMA control units. For the parity check is according to the invention in a first alarm circuit PM connected to the data bus bd first parity generator GP provided, whose output to the data input of a bistable circuit FF.

is performed by the D-type. The clock input of the circuit FF ₁ is connected to the output of a first gate circuit P. The signal r active during the read operation (the first phase of the DMA cycle) and a signal active during the implementation of a direct data transfer (DMA cycle) d is controlled. At the end of the first phase of the DMA cycle, FF is at the output of the circuit. the parity bit of the incoming data is stored. When the data are sent out during the second phase, the parity generator generates GP. again the parity bit that goes to the first input of a first exclusive OR circuit EO. whose second input is connected to the output of the circuit FF. connected is. If the data has been changed by the DMA control unit _{under test, the input signals of the circuit EO 1 are} not the same, so that a signal is generated at its output. The signal of the circuit EO ₁ reaches the data input of a second bistable D-circuit FF ~, to whose clock input the output of a second gate circuit P "is connected, which receives the already mentioned signal d and a signal w at the input; which is effective when a write operation (second phase of the DMA cycle) is performed. If the data have been changed at the end of the second DMA cycle, the circuit FF generates an alarm signal A ₁ at its output.

With regard to the parity check of the addresses, it is assumed in the circuit arrangement described that the Direct data transfer in consecutive storage

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zones that can be addressed by increasing the previous address. It is one second alarm circuit SM is provided, which one to the address bus bi. connected read-only memory ROM contains, the contains the associated parity bit for each address. The read-only memory ROM represents based on the DMA control unit supplied i-th address, the parity bit of the next address i + 1 is available at the output. The output of the read-only memory ROM is linked to the data

tene inputs of several bistable D-circuits Ff ₁ ,

.. Ff connected, the number of which is equal to that of the DMA control units, and whose clock inputs are connected to a corresponding number of outputs of a first multiplexer MX ₁ . The multiplexer MX ₁ transmits two pulses or control bits C ₁ and c depending on the binary value. a signal k to one of its outputs, by means of which one of the bistable circuits Ff is enabled to write. The outputs of the circuits Ff are led to a corresponding number of inputs of a second _{multiplexer MX-, also controlled by the bits C 1} , c ", the output of which is connected to the first input of a second exclusive-OR circuit EO". The second input of the circuit EO ₂ is connected to the output of a parity generator GP- connected to the address bus bi. The output of the circuit EO- leads to the data input of a further bistable D-circuit FF. ,, which receives the mentioned signal k at the clock input.

Before the direct data transfer begins, the operating program of the microprocessor programs the relevant DMA control unit and writes the parity bit of the address from where the transfer is to take place _{in the respective bistable circuit Ff 1.} If z. B. the data transfer from a peripheral device to the storage units of the system is required and the writing of the first data is to begin at the (binary) address 1000, the operating program writes in the bistable circuit FF, the parity

bit of the address 1000. By the binary value of the control bits C ₁ and C _{2 of} the multiplexer MX. In this case, the bistable circuit FF _{1 is} enabled for storage and the corresponding input of the multiplexer MX _{2 is} selected. In this way, the parity bit of address 1000 _{goes to the first input of the circuit EO 2} , and when this address appears on the address bus, the parity generator GP "generates the parity bit and applies it to the second input of the circuit EO ₂ . In the event of a fault, the parity bit stored in the bistable circuit Ff ₁ deviates from the parity bit generated when the address was sent out, so that the output of the circuit EO _{2 is} excited. When the bistable circuit Ff-. receives the signal k, it generates an alarm signal A ₂ at its output. At the same time, the signal k enables the storage of the parity bit of the address 1001 generated by the read-only memory ROM in the bistable circuit Ff .. If, therefore, the address 1001 appears on the address bus bi, the parity generator GP ₂ generates the parity bit corresponding to it, so that this can be compared with the correct parity bit in the manner described.

It must be taken into account that there are currently no simple storage units available for the read-only memory ROM whose storage capacity has the theoretically required size (64K χ 1). In Figure 2, however, a preferred embodiment of the read-only memory is shown, which is formed from commercially available memory units. _{When bits A Q} -A _{15 are} transmitted on address bus bi, bits Aq-A _{7 go} to the input of a first read-only memory RQM ₁ , while bits A _R -A ₁ , - go to the input of a second read-only memory ROM. The memories ROM ₁ and ROM ₂ have a storage capacity of 256 χ 2, and therefore each is considered to be divided into two columns of memory cells.

the parity bits of the address following the address represented by bits A ₀ -A ₇ are stored in the first column of the memory ROM _1. The second column will be

-ΙΟΙ on the other hand, bits with the binary value O are stored with the exception of the memory cell determined by the address 255, into which a bit with the binary value 1 is written. The output u ^ of the first column of the memory ROM. is connected to the first input of an exclusive-OR circuit EO ₁ , while the output U _{2 of} the second column reaches the control input of a multiplexer MX, the output of which is connected to the second input of the circuit EO-. connected is.

The parity bits of the address formed from bits Ag-A ₁₅ or the parity bits of the address that follows the address formed from these bits are stored in the second or first column of the memory ROM _2. The outputs u 'and U ₂ "of the first or second column of the memory ROM lead to the first or second input of the multiplexer MX ₃ .

With regard to the addresses between 0 and 254, the parity bit of the address that _{follows the address formed from bits Aq - A 15} is calculated by adding the exclusive logical sum of the parity bit of the respective future address and the parity bit of the respective existing address, namely the less significant part of the address (bits A "- A ^) or the most significant part (bits Aq - A ₁ , -) / is formed. If the address 255 appears at the input of the memory ROM ₁ , this corresponds to. Output U ₂ a bit with the binary value 1, which _{causes the output of the parity bit corresponding to the output U 1 of} the memory ROM ₂ by the multiplexer MX. In this way, the exclusive OR circuit EO ₃ calculates the parity bit of the address that follows the address formed from bits A "- A ₁₅ by adding the exclusive logical sum of the parity bit of the future address and the less significant part (bits A_ - A ₇ ) as well as the most significant part of the address (bits Ag - A ₁₅ ). At the following addresses this has the output U _{2 of} the memory ROM. corresponding parity bit the binary value 0, so that the multi

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1 plexer MX, at the output again that of the output u "'des Memory ROM «supplies the corresponding parity bits.

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Claims (4)

TELEPHONE 089/4 70 60 06 TELEX 522 636 TELEGRAM SOMBEZ Italian note no. 24 466 A / 80 from 5.9.1980 15th ITALTEL Societä Italiana Telecomunicazioni s.p.a. Piazzale Zavattari 12, Milan / Italy 20th Circuit arrangement for fault monitoring of DMA control units Claims 25th 1 Λ Circuit arrangement for fault monitoring of a number of DMA control units for the direct transmission of data between peripheral devices and memory units in a system controlled by a microprocessor, in particular a telephone system, with the data bus and address bus of which the DMA control units are connected, the data transmission in particular in successive Memory areas are carried out which can be addressed by increasing the previous address, characterized in that O- 1 O O I O U that a first alarm circuit (PM) is provided which _{generates an alarm signal (A 1} ) when the parity bit of the data to be transmitted in one of the DMA control units (DMA ... to DMA) is different from the parity bit of the same DMA control unit forwarded data deviates, and that a second alarm circuit (SM) is provided which _{generates an alarm signal (A 2} ) when the parity bit of a given (i-th) address which is available on the basis of the address (i -1) has been determined, deviates from the parity bit of the given (i-th) address supplied at the output of the unit together with the associated data information (d.).
15th 2.) Circuit arrangement according to claim 1, characterized in that the first alarm circuit (PM) a first parity generator (GP ₁ ) which generates the parity bit of the data transmitted on the data bus (bd); a first bistable circuit (FF ₁ ) of the D-type, the data input of which is connected to the output of the first parity generator (GP ₁ ); a first gate circuit (P ₁ ), the output of which is fed to the clock input of the first bistable circuit (FF ₁ ), and whose inputs are provided by a first signal (d), which is effective during direct data transmission, and by a second signal (r) controlled .sind, which is effective during the reading of the data by the control unit; 30th a first exclusive OR circuit (EO ₁ ), to whose inputs the output "of the first bistable circuit (FF ₁ ) and the output of the first parity generator (GP ₁ ) are connected; and a second bistable circuit (FF-) of the D-type, whose data input to the output of the first exclusive-OR circuit (EO ₁ ) and whose clock input to the 5 β O t, α Λ Pj 6 tf, * * Ö «* O U Λ (t Λ ί> ti 4t ·« A »Β OO ο * _ Ο - Output of a second gate circuit (P ₂ ) is connected, which receives at the input the first signal (d) and a third signal (w) which is effective while the data is being written by the control unit into the memory units. 5 3.) Circuit arrangement according to claim 1 or 2, characterized in that the second alarm circuit (SM)
a second parity generator (GP ₂ ) which generates the parity bit of the addresses present on the address bus (bi); a second exclusive OR circuit (EO „), to whose first input the output of the second parity generator (GP ₂ ) is connected; a read-only memory (ROM) with a storage capacity of 1 χ 2 ^m , where m is the number of address bits reaching the address bus (bi), which at the output supplies the parity bit of the address that follows the address present on the address bus (bi); a number η of bistable casings (Pf ₁ , ...., Ff) equal to that of the DMA control _{units (DMA 1} , ... DMA), their data inputs with the output of the read-only memory (ROM) and their clock inputs with one output each a first multiplexer (MX ₁ ) are connected, which emits a fourth signal (k) at one of its η outputs based on the binary state of two control signals (C ₁ -C ₂ ); a second multiplexer (MX ₂ ), to whose inputs one output of the η bistable circuits (Ff ₁ ... Ff) is routed and whose output is connected to the second input of the second exclusive OR circuit (EO ₂ ); and a further bistable circuit (FF_) of the D-type, whose data input is connected to the output of the second exclusive-OR circuit (EO ₂ ) and whose clock input receives the fourth signal (k). 4.) Circuit arrangement according to claim 3, characterized characterized in that the read-only memory (ROM) ■> -> I. is made up of the following elements: a first read-only memory (ROM.) with a storage capacity of 2x2 'bits, which stores the parity bit of the address in the first column of memory cells which follows the address formed from the less significant m / 2 bits of the address group, while it stores in the second column stores a bit with the binary value 1 in the memory cell identified by the address 2 and bits with the binary value 0 in the remaining memory cells; a second read-only memory (ROM ₂ ) with a storage capacity of 2x2 bits, which stores the parity bit of the address expressed by the m / 2 most significant bits of the address group or the parity bit of the address in the second or in the first column of memory cells address expressed by the most significant m / 2 bits follows; a third multiplexer (MX-,), whose first or second input is connected to the first or second column (outputs u 'and ut) of the cells of the second read-only memory (ROM ”) and at the output of which are connected to the first input Bits appear when a control bit from the output (u ~) of the second memory cell column of the first read-only memory (ROM ^) has the binary value 1; and a third exclusive OR circuit (EO-), the inputs of which are connected to the output (U ₁ ) of the first memory cell _{column of the first read-only memory (ROM 1} ) or to the output of the third multiplexer (MX-.).