DE3071216D1 - Shared memory computer apparatus - Google Patents

Shared memory computer apparatus

Info

Publication number
DE3071216D1
DE3071216D1 DE8080900220T DE3071216T DE3071216D1 DE 3071216 D1 DE3071216 D1 DE 3071216D1 DE 8080900220 T DE8080900220 T DE 8080900220T DE 3071216 T DE3071216 T DE 3071216T DE 3071216 D1 DE3071216 D1 DE 3071216D1
Authority
DE
Germany
Prior art keywords
memory
shared memory
computer apparatus
data items
memory computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080900220T
Other languages
German (de)
English (en)
Inventor
Herbert W Sullivan
Leonard Allen Cohn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SULLIVAN COMPUTER
Original Assignee
SULLIVAN COMPUTER
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SULLIVAN COMPUTER filed Critical SULLIVAN COMPUTER
Application granted granted Critical
Publication of DE3071216D1 publication Critical patent/DE3071216D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8080900220T 1979-01-09 1980-01-07 Shared memory computer apparatus Expired DE3071216D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US200479A 1979-01-09 1979-01-09
PCT/US1980/000007 WO1980001421A1 (en) 1979-01-09 1980-01-07 Shared memory computer method and apparatus

Publications (1)

Publication Number Publication Date
DE3071216D1 true DE3071216D1 (en) 1985-12-12

Family

ID=21698800

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080900220T Expired DE3071216D1 (en) 1979-01-09 1980-01-07 Shared memory computer apparatus

Country Status (6)

Country Link
EP (1) EP0023213B1 (https=)
JP (1) JPH048824B2 (https=)
AT (1) ATE16426T1 (https=)
CA (1) CA1138119A (https=)
DE (1) DE3071216D1 (https=)
WO (1) WO1980001421A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111530A (en) * 1988-11-04 1992-05-05 Sony Corporation Digital audio signal generating apparatus
US7054969B1 (en) 1998-09-18 2006-05-30 Clearspeed Technology Plc Apparatus for use in a computer system
US8234577B1 (en) 2005-05-23 2012-07-31 Glance Networks, Inc. Method and apparatus for the transmission of changed host display information
US8484291B1 (en) 2008-04-02 2013-07-09 Glance Networks, Inc. Method and apparatus for selecting commands for transmission from an updated queue
WO2013033882A1 (en) 2011-09-05 2013-03-14 Huawei Technologies Co., Ltd. A method and apparatus for storing data

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3449723A (en) * 1966-09-12 1969-06-10 Ibm Control system for interleave memory
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3670309A (en) * 1969-12-23 1972-06-13 Ibm Storage control system
US3678470A (en) * 1971-03-09 1972-07-18 Texas Instruments Inc Storage minimized optimum processor
NL7106491A (https=) * 1971-05-12 1972-11-14
US3723976A (en) * 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US3812473A (en) * 1972-11-24 1974-05-21 Ibm Storage system with conflict-free multiple simultaneous access
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US3845474A (en) * 1973-11-05 1974-10-29 Honeywell Inf Systems Cache store clearing operation for multiprocessor mode
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
US4084231A (en) * 1975-12-18 1978-04-11 International Business Machines Corporation System for facilitating the copying back of data in disc and tape units of a memory hierarchial system
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4070706A (en) * 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system

Also Published As

Publication number Publication date
EP0023213B1 (en) 1985-11-06
JPH048824B2 (https=) 1992-02-18
JPS56500153A (https=) 1981-02-12
WO1980001421A1 (en) 1980-07-10
EP0023213A1 (en) 1981-02-04
EP0023213A4 (en) 1981-08-31
ATE16426T1 (de) 1985-11-15
CA1138119A (en) 1982-12-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING. SCHUEBEL-HOPF, U., DIPL.-CHEM. DR.RER.NAT., PAT.-ANWAELTE, 8000 MUENCHEN