DE3071150D1 - Store-in-cache mode data processing apparatus - Google Patents

Store-in-cache mode data processing apparatus

Info

Publication number
DE3071150D1
DE3071150D1 DE8080106630T DE3071150T DE3071150D1 DE 3071150 D1 DE3071150 D1 DE 3071150D1 DE 8080106630 T DE8080106630 T DE 8080106630T DE 3071150 T DE3071150 T DE 3071150T DE 3071150 D1 DE3071150 D1 DE 3071150D1
Authority
DE
Germany
Prior art keywords
store
processing apparatus
data processing
mode data
cache mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080106630T
Other languages
German (de)
Inventor
Benedicto Umberto Messina
William Dean Silkman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3071150D1 publication Critical patent/DE3071150D1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8080106630T 1979-11-23 1980-10-29 Store-in-cache mode data processing apparatus Expired DE3071150D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/096,860 US4317168A (en) 1979-11-23 1979-11-23 Cache organization enabling concurrent line castout and line fetch transfers with main storage

Publications (1)

Publication Number Publication Date
DE3071150D1 true DE3071150D1 (en) 1985-11-07

Family

ID=22259433

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080106630T Expired DE3071150D1 (en) 1979-11-23 1980-10-29 Store-in-cache mode data processing apparatus

Country Status (5)

Country Link
US (1) US4317168A (en)
EP (1) EP0029517B1 (en)
JP (1) JPS5936350B2 (en)
CA (1) CA1143860A (en)
DE (1) DE3071150D1 (en)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493033A (en) * 1980-04-25 1985-01-08 Data General Corporation Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
US4382278A (en) * 1980-06-05 1983-05-03 Texas Instruments Incorporated Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache
US4399506A (en) * 1980-10-06 1983-08-16 International Business Machines Corporation Store-in-cache processor means for clearing main storage
US4523275A (en) * 1980-11-14 1985-06-11 Sperry Corporation Cache/disk subsystem with floating entry
US4433374A (en) * 1980-11-14 1984-02-21 Sperry Corporation Cache/disk subsystem with cache bypass
US5146572A (en) * 1980-11-17 1992-09-08 International Business Machines Corporation Multiple data format interface
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
US4513367A (en) * 1981-03-23 1985-04-23 International Business Machines Corporation Cache locking controls in a multiprocessor
US4476524A (en) * 1981-07-02 1984-10-09 International Business Machines Corporation Page storage control methods and means
JPS58133696A (en) * 1982-02-03 1983-08-09 Hitachi Ltd Storage control system
US4463420A (en) * 1982-02-23 1984-07-31 International Business Machines Corporation Multiprocessor cache replacement under task control
US4636946A (en) * 1982-02-24 1987-01-13 International Business Machines Corporation Method and apparatus for grouping asynchronous recording operations
US4489381A (en) * 1982-08-06 1984-12-18 International Business Machines Corporation Hierarchical memories having two ports at each subordinate memory level
JPS59100964A (en) * 1982-12-01 1984-06-11 Hitachi Ltd Parallel transfer type director device
US4633387A (en) * 1983-02-25 1986-12-30 International Business Machines Corporation Load balancing in a multiunit system
US4707784A (en) * 1983-02-28 1987-11-17 Honeywell Bull Inc. Prioritized secondary use of a cache with simultaneous access
US4625273A (en) * 1983-08-30 1986-11-25 Amdahl Corporation Apparatus for fast data storage with deferred error reporting
BR8406089A (en) * 1983-11-30 1985-09-24 Fujitsu Ltd PROCESS TO CONTROL INTERMEDIATE MEMORY IN DATA PROCESSING DEVICE
GB8401804D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Data storage apparatus
US4736293A (en) * 1984-04-11 1988-04-05 American Telephone And Telegraph Company, At&T Bell Laboratories Interleaved set-associative memory
JPS618785A (en) * 1984-06-21 1986-01-16 Fujitsu Ltd Access control system for storage device
JPH0616272B2 (en) * 1984-06-27 1994-03-02 株式会社日立製作所 Memory access control method
JPH0670787B2 (en) * 1984-06-29 1994-09-07 富士通株式会社 Command transfer control system between processors
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4783736A (en) * 1985-07-22 1988-11-08 Alliant Computer Systems Corporation Digital computer with multisection cache
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
US4766535A (en) * 1985-12-20 1988-08-23 International Business Machines Corporation High-performance multiple port memory
EP0228745A3 (en) * 1985-12-30 1990-03-28 Koninklijke Philips Electronics N.V. Raster scan video controller provided with an update cache, update cache for use in such video controller, and crt display station comprising such controller
JPS62194563A (en) * 1986-02-21 1987-08-27 Hitachi Ltd Buffer storage device
US5001665A (en) * 1986-06-26 1991-03-19 Motorola, Inc. Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs
US4785395A (en) * 1986-06-27 1988-11-15 Honeywell Bull Inc. Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
US4780809A (en) * 1986-08-08 1988-10-25 Amdahl Corporation Apparatus for storing data with deferred uncorrectable error reporting
JPH0661066B2 (en) * 1986-10-20 1994-08-10 株式会社日立製作所 Storage controller
ATE63011T1 (en) * 1987-02-16 1991-05-15 Siemens Ag METHOD FOR CONTROLLING THE DATA EXCHANGE BETWEEN PROCESSING UNITS AND A STORAGE SYSTEM WITH CACHE MEMORY IN DATA PROCESSING EQUIPMENT, AND A CORRESPONDENTLY WORKING CACHE MEMORY.
US4965764A (en) * 1987-03-04 1990-10-23 Nec Corporation Memory access control system
US4851993A (en) * 1987-04-20 1989-07-25 Amdahl Corporation Cache move-in bypass
JPH0740244B2 (en) * 1987-08-05 1995-05-01 三菱電機株式会社 Micro Processor
JPH01163852A (en) * 1987-10-02 1989-06-28 Computer Consoles Inc Subsystem in data processing system and its operation method
US4912631A (en) * 1987-12-16 1990-03-27 Intel Corporation Burst mode cache with wrap-around fill
EP0330425B1 (en) * 1988-02-23 1995-12-06 Digital Equipment Corporation Symmetric multi-processing control arrangement
US4953079A (en) * 1988-03-24 1990-08-28 Gould Inc. Cache memory address modifier for dynamic alteration of cache block fetch sequence
US5032985A (en) * 1988-07-21 1991-07-16 International Business Machines Corporation Multiprocessor system with memory fetch buffer invoked during cross-interrogation
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
JPH0687232B2 (en) * 1988-12-19 1994-11-02 三菱電機株式会社 Data processing device
US5019965A (en) * 1989-02-03 1991-05-28 Digital Equipment Corporation Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width
US5148537A (en) * 1989-05-02 1992-09-15 Belsan Jay S Method and apparatus for effecting an intra-cache data transfer
GB9008145D0 (en) * 1989-05-31 1990-06-06 Ibm Microcomputer system employing address offset mechanism to increase the supported cache memory capacity
US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
US5014195A (en) * 1990-05-10 1991-05-07 Digital Equipment Corporation, Inc. Configurable set associative cache with decoded data element enable lines
EP0473804A1 (en) * 1990-09-03 1992-03-11 International Business Machines Corporation Alignment of line elements for memory to cache data transfer
US5493668A (en) * 1990-12-14 1996-02-20 International Business Machines Corporation Multiple processor system having software for selecting shared cache entries of an associated castout class for transfer to a DASD with one I/O operation
JPH05210974A (en) * 1991-10-03 1993-08-20 Smc Standard Microsyst Corp Coupling system of static cash memory and dynamic main memory on same chip
JP3614428B2 (en) * 1992-02-28 2005-01-26 沖電気工業株式会社 Cache memory device
JP2788836B2 (en) * 1992-05-15 1998-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション Digital computer system
US5566324A (en) * 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
JPH0756815A (en) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> Cache operating method and cache
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
JPH07105128A (en) * 1993-10-07 1995-04-21 Mitsubishi Electric Corp Data transfer device
US5752264A (en) * 1995-03-31 1998-05-12 International Business Machines Corporation Computer architecture incorporating processor clusters and hierarchical cache memories
US6076150A (en) * 1995-08-10 2000-06-13 Lsi Logic Corporation Cache controller with improved instruction and data forwarding during refill operation
GB2308903B (en) * 1996-01-05 2000-01-26 Advanced Risc Mach Ltd Cache memory circuit
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
US6484230B1 (en) 1998-09-28 2002-11-19 International Business Machines Corporation Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction
US7283991B1 (en) * 1999-03-11 2007-10-16 Microsoft Corporation Caching system for path search optimization
US6542861B1 (en) * 1999-03-31 2003-04-01 International Business Machines Corporation Simulation environment cache model apparatus and method therefor
GB2372848B (en) * 2001-02-20 2004-10-27 Advanced Risc Mach Ltd Data processing using a coprocessor
US8683139B2 (en) 2006-10-31 2014-03-25 Hewlett-Packard Development Company, L.P. Cache and method for cache bypass functionality
US10140219B2 (en) 2012-11-02 2018-11-27 Blackberry Limited Multi-port shared cache apparatus

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3670309A (en) * 1969-12-23 1972-06-13 Ibm Storage control system
US3670307A (en) * 1969-12-23 1972-06-13 Ibm Interstorage transfer mechanism
US3820078A (en) * 1972-10-05 1974-06-25 Honeywell Inf Systems Multi-level storage system having a buffer store with variable mapping modes
DE2261586C3 (en) * 1972-12-15 1979-08-09 Siemens Ag, 1000 Berlin Und 8000 Muenchen Storage facility
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US4169284A (en) * 1978-03-07 1979-09-25 International Business Machines Corporation Cache control for concurrent access
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations

Also Published As

Publication number Publication date
EP0029517B1 (en) 1985-10-02
CA1143860A (en) 1983-03-29
EP0029517A3 (en) 1983-03-16
JPS5936350B2 (en) 1984-09-03
JPS5687284A (en) 1981-07-15
US4317168A (en) 1982-02-23
EP0029517A2 (en) 1981-06-03

Similar Documents

Publication Publication Date Title
DE3071150D1 (en) Store-in-cache mode data processing apparatus
GB2011673B (en) Data processing apparatus
GB2015217B (en) Data processing apparatus
GB2079997B (en) Data processing apparatus
DE3169741D1 (en) Data processing apparatus
GB2072902B (en) Data processing apparatus
GB2017984B (en) Data processing apparatus
GB2015216B (en) Data processing apparatus
DE3176513D1 (en) Data processing apparatus
JPS56101235A (en) Data processing system
GB1555300A (en) Data processing apparatus
JPS55102056A (en) Data processing system
GB1539356A (en) Data processing apparatus
GB1547746A (en) Data processing apparatus
DE3067401D1 (en) Data processing system
GB1550042A (en) Data processing apparatus
GB2018478B (en) Data processing apparatus
GB1552574A (en) Data processing apparatus
GB2011672A (en) Data processing apparatus
GB2009981B (en) Data processing apparatus
DE2965202D1 (en) Data processing apparatus
GB1539872A (en) Data processing apparatus
MY8500449A (en) Data processing apparatus
GB1549968A (en) Data processing apparatus
GB1550794A (en) Data processing apparatus

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee