DE3065715D1 - Process for aligning photogravures with respect to region-isolating walls in integrated circuits - Google Patents

Process for aligning photogravures with respect to region-isolating walls in integrated circuits

Info

Publication number
DE3065715D1
DE3065715D1 DE8080401616T DE3065715T DE3065715D1 DE 3065715 D1 DE3065715 D1 DE 3065715D1 DE 8080401616 T DE8080401616 T DE 8080401616T DE 3065715 T DE3065715 T DE 3065715T DE 3065715 D1 DE3065715 D1 DE 3065715D1
Authority
DE
Germany
Prior art keywords
photogravures
aligning
region
respect
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080401616T
Other languages
German (de)
English (en)
Inventor
Eugene Tonnel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE3065715D1 publication Critical patent/DE3065715D1/de
Expired legal-status Critical Current

Links

Classifications

    • H10P90/191—
    • H10P50/00—
    • H10W10/031—
    • H10W10/181—
    • H10W10/30—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
DE8080401616T 1979-12-21 1980-11-12 Process for aligning photogravures with respect to region-isolating walls in integrated circuits Expired DE3065715D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7931483A FR2472268A1 (fr) 1979-12-21 1979-12-21 Procede de formation de caisson dans des circuits integres

Publications (1)

Publication Number Publication Date
DE3065715D1 true DE3065715D1 (en) 1983-12-29

Family

ID=9233091

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080401616T Expired DE3065715D1 (en) 1979-12-21 1980-11-12 Process for aligning photogravures with respect to region-isolating walls in integrated circuits

Country Status (4)

Country Link
US (1) US4369561A (enExample)
EP (1) EP0031260B1 (enExample)
DE (1) DE3065715D1 (enExample)
FR (1) FR2472268A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532700A (en) * 1984-04-27 1985-08-06 International Business Machines Corporation Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer
US4627883A (en) * 1985-04-01 1986-12-09 Gte Laboratories Incorporated Method of forming an isolated semiconductor structure
JPH01179342A (ja) * 1988-01-05 1989-07-17 Toshiba Corp 複合半導体結晶体

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3713908A (en) * 1970-05-15 1973-01-30 Ibm Method of fabricating lateral transistors and complementary transistors
DE2044863A1 (de) * 1970-09-10 1972-03-23 Siemens Ag Verfahren zur Herstellung von Schottkydioden
GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
US3919060A (en) * 1974-06-14 1975-11-11 Ibm Method of fabricating semiconductor device embodying dielectric isolation
US3954523A (en) * 1975-04-14 1976-05-04 International Business Machines Corporation Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
GB1503223A (en) * 1975-07-26 1978-03-08 Int Computers Ltd Formation of buried layers in a substrate
US4016017A (en) * 1975-11-28 1977-04-05 International Business Machines Corporation Integrated circuit isolation structure and method for producing the isolation structure

Also Published As

Publication number Publication date
FR2472268A1 (fr) 1981-06-26
EP0031260B1 (fr) 1983-11-23
EP0031260A3 (en) 1981-07-22
US4369561A (en) 1983-01-25
FR2472268B1 (enExample) 1983-10-14
EP0031260A2 (fr) 1981-07-01

Similar Documents

Publication Publication Date Title
DE3071203D1 (en) Improvements in or relating to apparatus for a reative plasma process
EP0023294A3 (en) Method for repairing integrated circuits
IL70075A0 (en) Improvements in or relating to 3-aryl-5-pyrazole derivatives
GB2058094B (en) Process for preparing terpolymers
ZA805453B (en) Integrated coal liquefaction process
GB2021763B (en) Aligning plane components
PT71097A (en) Process for obtaining reserve-effects in the tissue-printing
GB2089536B (en) Improvement in or relating to wafer scale integrated circuits
GB2081187B (en) Retro-etch process for integrated circuits
PH15678A (en) Improvements in or relating to pyrazinobenzodiazepines
PH16955A (en) Improvements in or relating to suppository manufacture
DE3065715D1 (en) Process for aligning photogravures with respect to region-isolating walls in integrated circuits
GB2122785B (en) Improvements in or relating to counter circuits
DE2862049D1 (en) Process for preparing linear trans-quinacridone in gamma-crystal modification
GB2120888B (en) Improvements in or relating to bistable multivibrator circuits
PL247098A1 (en) Process for preparing supiride in galenic form
DE2964315D1 (en) Process for producing steroid compounds having an oxogroup in the side chain
GB2052906B (en) Flip-flop circuits
GB2120861B (en) Process for manufacturing panels to be used in microelectronic systems
GB8332782D0 (en) Register marks to articles
GB2064176B (en) Setting arrangement in electronic timepiece
GB2131010B (en) Improvements in or relating to forming machines for glassware
JPS5352291A (en) Removal process for nox in sulfuric acid
GB2050050B (en) Basewidth variation compensation in integrated circuit transistors
JPS5337780A (en) Process for making panels