DE3049411A1 - Optional length character format row generator system - uses independent memory fields for generating optional and pre-defined data - Google Patents

Abstract

The method of generating rows of characters of optimal length and with optional and predefined data contents involves the use of independent memory fields for the generation of the optional and the predefined data. The method permits individual character row programming, more combinations than conventionally available, correct generation of specified test characters, removal of individual characters, longer durations of characters, and chaining of different formats. The character format generator contains three groups of components. The first group contains functional units such as sequential control logic, time control logic, a channel interface, a clear logic section, a deletion logic section, a clock generator, and a second microprogram memory. The second and third groups produce the optional and predefined data contents respectively and contain suitable control, addressing and memory elements.

Description

Method for generating character series

of any length and with any and predeterminable data content and arrangement of a character shape generator for carrying out the method The invention relates to a method and an arrangement for realizing a character shape generator for character series of any length with total content generation.

The character shape generator can also be used to generate any and predeterminable data content. It has a very wide range of uses on.

In the field of digital technology, there is often a need for logical networks to simulate even with the most complicated structure or to implement more functional ones exams Rows of characters each of different lengths and with to generate predetermined or any data content. With the constant Zunalune the complexity and intricacy of the test networks is the need in the lately Has come to the fore that the character shapes are predetermined or selectable or arbitrary Content can be generated in a row. As a known solution is on the attachment F XKE TRENDAR 3020 A pointed out. The character shape generator represents the technical level. It is hardware-based as far as its mode of operation and arrangement are concerned which allows it to create the following character shapes: fast and slow running pulses, high, medium and low speed data, fast, eight-phase and gray-coded clock signals as well as initial erasures.

The character shapes mentioned are created by llardware programming led to the output of the character shape generator, which is connected to the inputs of the test network connected is. These character shapes meet the test requirements of complicated networks nowhere near fair. The aforementioned solution has the following disadvantages on: - the individual, predetermined character series cannot be programmed individually - only relatively few combinations can be produced - the The character form required for the test network can, even with very simple networks, are only very rarely produced in accordance with regulations, - individual character shapes can neither be triggered nor switched off, as they are only built up continuously - the character forms only have short periods, i.e. they repeat themselves all too often - no single form can be linked to the other will.

The invention is based on the disadvantages of the known Eliminate solutions.

This object is achieved with a method with those specified in claim 1 Features and an arrangement with the features specified in claim 2 solved.

Expedient developments of the arrangement according to the invention result from claims 3 to 5.

The problem has been solved in such a way that the double requirement, i. the requirement of the arbitrary and the predetermined data content according to the same procedure and with the help of two. independent arrangement groups is fulfilled.

When generating any data content, the data content, which means the required output character shapes and the order of these generated by means of an external program. During the generation of the predeterminable The data content is the data content that has the required output character forms means, and the order of the same character forms based on mathematical algorithms built, taking the microprograms for their description (i.e. subroutines) be left in internal microprogram memories. For generating the output character shapes the data contents of these microprograms are used. Retrieval and order of Data items of the microprogram memory are determined by an external program.

Thus, the character shape generator has three separate components on: Component I contains the functional control units that component II generates Any data content and the component III generates predeterminable data content.

The method according to the invention is used to generate series of character shapes of any length with any and predetermined data content, whereby for generation the arbitrary and the pre-determinable data contents each have an independently usable one Memory field is available.

It is characterized in that the trigger, shutdown and clock pulses be used as functionally intervening, target-controlling impulses that both Storage fields in independently controllable and independently functional storage sectors be divided from each other during the execution of each functional operation operated separately, connected in parallel to each other and with the target-controlling impulses can be virtually chained. When generating any data content, proceed as follows: The sectors of the memory field are used to generate the required output character forms are loaded using the read-in program, whereby the intervention by the Zielsteuerm # sin # ulse in the functional operation of the Storage sectors is taken into account, i.e. it is taken into account with the independent triggering, the continuous Operation, the interruption of ongoing operation and the shutdown of operations expected. The procedure for the predeterminable data content is as follows: The sectors of the memory field are used to generate the required output character shapes charged by internal generation of the character shapes, with the help of the programs of the microprogram memory with the subroutines for describing the mathematical Algorithm and based on the predeterminable read-in program. While charging the intervention by the target control impulses -in-the-functional operation of the Memory sectors are taken into account: It is with the independent triggering, the continuous Operation, the interruption of ongoing operation and the shutdown of operations expected. In the further one goes both with the generation of the arbitrary and in the generation of the predeterminable data content in the same way. The memory fields are read with the help of the reading program, whereby the fields when charging the memory target controls used should be taken into account. Reading winds up in the case of each storage sector individually. Reading of the individual memory sectors the trigger pulses are started independently of each other, the continuous reading made with the clock pulses and the continuous reading of the individual memory sectors in the instant and for the duration determined by the reading program, interrupted. When the reading of the content of the individual memory sectors is finished, the operation of these memory sectors is stopped with the shutdown pulses. To the Generation of the required output character shapes will the individual storage sectors according to the reading program with the help of the release, shutdown and clock pulses for target control connected in parallel or virtually chained to one another. Due to the interruption controlled by the Taktim-Pulse at any point repeats the individual storage sectors either completely or as always predetermined loaded with new data content, which- content during the generation of new character shapes is read as described above.

The invention is based on an exemplary embodiment below the drawings explained in more detail. The drawings show: FIG. 1 a block diagram an arrangement of a character shape generator according to the invention and FIG. 2 is a block diagram a control circuit in the arrangement according to FIG. 1.

The structure of the suitable for carrying out the method according to the invention Character shape generator is described with reference to FIG.

The sequential control belongs to component I or to the functional control Control logic 1, i.e. a sequential network with any digital structure with an internal clock generator, which via a second microprogram memory 16 disposes. With control logic 1, all control impulses for the entire character shape generator are generated generates, namely the time setting pulses for controlling the charge reversals, the data for the memory field with changeable content, the logic for controlling the different functional states of the facility. Control logic connection points are microprogram inputs 101 and feedback input 108, transfer output 102, time setting output 103, data output 104, first function output 105, second function output 106 and third function output 107.

The time setting logic 2 is a sequential logic circuit with any digital structure that allows the time setting within the time range allowed for the output characters of the character shape generator. Your connection points are timing input 201, timing pulse outputs 202 and 203 as well Output 204 for exit time setting. The line adapter 12 can be used with any programmable logic level circuits consisting of n + m lines being constructed. Its output is with the output 1203 of the character shape generator identical. In addition to this output, it also has three inputs, namely inputs 1201 and 1202 for shaped data and input for output timing control 1204.

The trigger logic 13, the shutdown logic 14 and the clock logic 15 are made up of any digital circuits and are used to control the first and second memory controls 4 and 6 according to the chosen task The trip logic 13 has a first and a second output 1302 and 1303 for trigger pulses and a first function input 1301, the shutdown logic 14 a second function input 1401, a first and second output 1402 and 1403 for switch-off pulses, a first and a second input 1404 and 1405 for cycle end pulses and a feedback output 1406 on. The clock generator logic 15 has a third functional input 1501 and first and second outputs 1502 and 1503 for clock pulses.

The second microprogram memory 16 is used for storage and reading of the control logic 1 program is used.

It is made up of read-in and read-out storage elements.

The component II for generating any data content typically exhibits the following units: First, the first memory field 3 with variable Content with j independently controllable memory sectors with a capacity of up to n bits and with a variable memory length. This storage field is intended to be loaded by the control logic 1 with any memory content and using the appropriate control for the selected functional state the readability of the memory content for the output of the character shape generator Its connection points are data input 301, address and control input 303, data output 302 and output 304 for cycle end pulses.

Second, to control the first memory field 3 with variable Contents the first memory controller 4 uses. It is made up of digital circuits.

Their connection points are inputs 401 for trigger pulses, 402 for Stop pulses and 403 for clock pulses and output 404 for address and control pulses.

The third unit of component II is the first buffer register 10, which has a content of n bits, composed of quick register elements is.

The component III, which carries out the predeterminable data content generation, consists of the following units: First the second memory field 5 with internal content generation consisting of k independently controllable storage sectors is formed, and that has a capacity of up to m bits and variable memory length having. With it, the sequence and data content of the character forms can be determined according to a selected algorithm can be determined and generated in advance. Its connecting points inputs 501 are microprogram and 502 control pulses, outputs 503 data and 504 Cycle end pulse.

To control the second memory field 5 with internal content generation the second memory controller 6 is used. It is made up of digital circuits. Their connection points are inputs 601 trigger pulse, 602 stop pulse, 603 clock pulse and 606 comparator pulse and outputs 604 control pulse, 605 control and time setting pulses.

Another unit of component III is the second buffer register 11 with quick register elements and with a content of n bits.

The last unit of component III for generating the predeterminable The data content is the control circuit 7-8-9, which is shown in FIG. 2 in its embodiment is shown.

It has an address counter 7, a first micro-Slrograx memory 8 and a logic comparator 9. The control and timing inputs 701, 802 and 902 of these three units are connected to each other in parallel.

The microprogram data output 804 of the first microprogram memory 8 is with the microprogram data input 905 of the logical comparator 9, the intervention pulse exit 904 of the logical comparator 9 with the intervention pulse input 702 of the address counter 7 and the microprogram offset output 703 of the same unit with the microprogram offset input 801 of the first microprogram memory 8 coupled. The microprogram output 803 of the first microprogram memory 8 and the data input 901, the control and timing pulse input 902 and the comparator input 903 of the logical comparator 9 form connection points for the control circuit 7-8-9.

The first microprogram memory 8 consists of any read memory and from their control circuits. He instructs the program of the algorithm of the second Memory field 5 with internal content generation, which he based on the programs drives.

The logical comparator 9 is put together from any digital comparators. It compares the output data of the first microprogram memory 8 with those of the second memory field 5 with internal content generation and controls the result the address counter 7 according to the comparison. Its connection points are Inputs 901 data, 902 control and timing pulses, 903 microprogram data and output 904 intervention and comparison pulses.

The character shape generator for generating character series of any Length with any and predeterminable data content is characterized by that the component II to generate any data content, the following three Units contains: The first memory field 3 with variable content with a data input 301, a data output 302, an address and Control input 303, an output 304 for cycle end pulses, the first memory controller 4 with a Input 401 for trigger pulses, one input 402 for shutdown pulses, one input 403 for clock pulses and an output 404 for address and control pulses and that first buffer register 10 with a time pulse input 1001, a data input 1002, a transfer input 1003 and an output 1004 shaped data; further the component III for generating the predeterminable data content has the following three Units contains: The second memory field 5 for internal content generation with a Microprogram input 501, a control pulse input 502, a data output 503, an output 504 for Zvz'lusendimmulse, the second memory controller 6 with a Input 601 for trigger pulses, one input 602 for shutdown pulses, one input 603 for clock pulses, an output 604 for control pulses, an output 605 for Control and timing pulses and a comparator input 606 and the second buffer register 11 and also the control circuit 7-8-9, the first memory field 3 from j and the second memory field 5 with k independently controllable memory sectors each has a storage capacity of up to n bits or of up to m bits that the units in component II are connected to one another in such a way that the first memory field 3 via the data input 301 with the sequential control logic 1, via the data output 302 with the first buffer register 10, the inputs connected in parallel the memory sectors via the address and control input 303 with the same output 404 of the first memory controller 4, the parallel-connected outputs of the memories sectors via output 304 for cycle dimensions with the shutdown logic 14, the inputs 401, 402 and 403 of the first memory controller 4 with the trigger logic 13, the shutdown logic 14 and the clock logic 15, the input 1001 for time setting pulses of the first storage register 10 with one output 202 for timing pulses the time setting logic 2, the transfer input 1003 of the same register with the transfer output 102 of the sequential control logic 1 and its shaped data output 1004 with the Line adaptation 12 are connected that the units of component III such are interconnected that the second memory field 5 for internal content generation via the microprogram input 501 at the microprogram output 803 of the control circuit 7-8-9 r via the data output 503 on the one hand at the shaped data input 1102 of the second buffer register 11 and on the other hand at the data input 901 of the control circuit 7-8-9 is connected, the parallel-connected inputs of the memory sectors Via the input 502 control pulses at the output 604 control pulses of the second memory controller 6 and the parallel-connected outputs of the memory sectors via the output cycle end pulses the second input 1405 cycle end pulses of the shutdown logic 14 are connected, the inputs 601 for trigger pulses, 602 for shutdown pulses and 603 for clock pulses the second memory controller 6 each with the trigger logic 13, the shutdown logic 14 and the clock logic 15, its output 605 for control and triggering pulses as well as its Input 606 for comparator pulses expediently with the connection points of the control circuit 7-8-9 are connected, and that the input 1101 for timing pulses of the second Latch register 11 with the other output 203 for time setting pulses the Time setting logic 2, its reloading input 1103 with the reloading output 102 of the sequential control logic 1 and its shaped data output 1104 with the line matching 12 is connected.

The character shape generator according to the invention can also be used to generate only the arbitrary or predeterminable data content can be provided. In this In the character shape generator, in addition to component I, only component II is the case or only the component III installed.

The character shape generator according to the invention operates according to the following Operating mode: During the generation of any data content, the sequential Control logic 1, the time setting logic 2, the first memory controller 4, the triggering logic 13, the shutdown logic 14 and the clock logic 15 in the basic position.

The state of the first memory field 3 variable content and of the first buffer register 10 is indifferent. According to that in the second microprogram memory 16 left as well as that entered by any external data input unit Program will load the main memory of the sequential control logic 1 as well the charging of the first memory controller 4 started.

The individual memory sectors must be controlled separately in the program of the first memory field 3 change the contents, the respective states of the first memory controller 4, the program for their organization with their word length (n bits) as well as the parallel and series connection of the memory sectors will.

In addition, all program positions of the time setting logic are in the program 2 as well as all Procjrammstellung the trigger logic 13, the Abstelllogik 14 and the Clock logic 15 in the predetermined order, furthermore all programs of Working memory of the control logic controlling the entire character shape generator part 1 to be specified.

After the units required for control are in working condition are set, the loading of the first memory field 3 begins with variable content using the external program with the required data.

These are determined by the required output signal series; in the preparation of the program or the amount of data for loading n # 3 are taken into account that the trigger, shutdown and clock pulses as functionally intervening target control pulses are used that each Storage sector both during charging and reading individually drive.

After the program is loaded, the original character form will be in a word length of n bits via the first intermediate storage register 10.

Caused by the sequential control logic 1, this is done on the third functional output 107 characters to the third functional input 1501 out, where it controls the clock logic 15 that determines the reading rhythm Clock pulses generated.

The triggering is through the trigger logic 13 with the help of the Control logic 1 generates the received signal, taking it from the one placed in the program Address in the cycle of the clock pulse given by the clock logic 15 reading sets in motion. The effective control of the reading is provided by the first memory controller 4 taken over, with the necessary addresses, the command pulses for reading and generates the impulses for memory organization.

The memory output pulses appear on data output 302 and go on to the first buffer register 10. Another factor in character shaping is the output time setting, which is based on the program through the time setting logic 2 is accepted, and which is to be expected at output 202 for timing pulses. The conversion times of the routed into the first buffer register 10 Information is determined by the time setting logic 2, whereby it the actual output character shape for each channel (n bits) is generated separately from one another. Several synchronization options are available via lines 204-1004. One possibility of variation - the output character forms means the use of the Target control pulses of the shutdown logic 14 and the clock logic 15. In consequence of the Command pulse in the program, the clock logic 15 prevents the output of the clock pulse in the direction of the first memory controller 4.

This is called an interruption. The initial information is correct with the last read word (n bits) of the first memory field 3 variable Content. The program specifies during how many clock pulses the interrupted state should be maintained by changing the state of the output character shape remains unchanged.

According to the program, further reading can be carried out in any Storage sector independently, can be triggered. The last data item read of the memory sector has the consequence that each independent memory sector of the first Memory field 3 variable content a cycle end pulse at its output 304 outputs for cycle end pulses. Now the shutdown logic 14 comes into operation and stops the cycle from running. the end the program arises the possibility of changing the memory sectors of the first memory field 3 Reorganize the content or increase or increase the length and width of the memory Reduce. It becomes the virtual concatenation of the memory in the channel or in the channels with designation selected bit no. i enables which in the selected channels in principle, infinitely long storage capacity can be available. The content the remaining channels can either continue to be programmed or through the first Buffer register 10 to be maintained unchanged and indifferent.

The reload pulse of the first buffer register 10 is through the sequential control logic 1 set so that they can only be used by Program dependent, regardless of the content of the first memory field 3 changeable The content or the state of the time setting logic 2.

With the help of the external program, the target control guaranteed possibilities can also be used together. That way you can at any memory address in the first memory field 3 with variable content and the interruption can also be used there in the selected storage sector, which memory sector up to a predetermined, but arbitrary content or can also be completely recharged with new data, after which with the trigger pulse reading is started again.

When generating the predeterminable data content, the sequential Control logic 1, the time setting logic 2, the second memory control uw; 5 with internal Generation, the address counter 7, the trigger logic 13, the shutdown logic 14 and the clock logic 15 first in the initial position. It doesn't matter in which state the second memory field 5 with internal content generation and that second buffer register 11 are.

With the help of the left in the second microprogram memory 16 and program entered via any external data input unit the character generation can be set in motion. The required character shapes are prescribed by the required output character series. With the arrangement only the character series can be used to generate the predeterminable data content be realized, in whose data content resp.

to recognize any regularity in the order of the data contents is when this regularity is based on a mathematical algorithm can lead back.

The character generation is done with the help of the microprograms of the first Microprogram memory 8 through the second memory field 5 with internal content generation performed.

The second memory field 5 with internal content generation reads through the address counter 7 is controlled by offsetting the first microprogram memory 8 enters the character shapes called up by the program into its internal register. Data content and the order of these character shapes are determined by mathematical algorithms, where the program that maps these algorithms from each in the first microprogram memory 8 provided Unterprograiniflen is put together, so that on the basis of the program the sequential control logic 1 the uniform character series is built. Such a simple character series is e.g. the Gray code or any internationally accepted character form for memory checking, such as current "O", running "1", chessboard, etc.

In the programs written in the sequential control logic 1 are, so the programs for controlling the second memory field 5 with internal Content generation, the program for the independent control of the here k memory sectors, the program for calling up the first microprogram memory 8, the program for operating the comparator 9, the program for setting the Word length (n bits) of the second memory field 5 with internal content generation, all Program settings of the time setting logic 2 and in the appropriate order all program settings of the trigger logic, the shutdown logic and the clock logic, furthermore all programs of the main memory of the control logic 1 for the organization of the operation of the entire character shape generator part.

After the program has been loaded, the generation can be in a length of n bits the predeterminable character shape can be started via the line adapter 12.

On the basis of the command of the control logic 1, the clock logic delivers 15 the clock pulse that is used in the second Memory control 6 is directed.

Starting is through the trigger logic 13 with the help of the Control logic 1 supplied by the impulse the second microprogram memory 16 set address in the rhythm of the clock signal of the clock logic 15 given.

The actual control of the reading and the internal character shape generation has the task of the second memory controller 6, whereby it provides the necessary addresses, the control pulses for the second memory field with internal ncr content generation and for the control circuit 7-8-9 manufactures. It is important to aim for self Actuation, function interruption and shutdown of each storage sector achieved to have. When the subroutines accommodated in the first microprogram memory 8 arranged in the required order comes at the exit of the second Memory field 5 with internal content generation the output configuration with a Word length of n bits and goes on to do two buffer registers 11. The pulse produced by the time setting logic 2 for setting the output time is also passed to the second buffer register 11. The timing logic 2 represents the conversion times of the routed into the second buffer register 11 Information, which makes it the actual output character shape in all channels generated individually (m bits).

The combination of the functions of the trigger logic 13, the shutdown logic 14 and the clock logic 15 means a further possible variation for the output characters.

As described above, the output of the clock pulse, the interruption of the clock pulse and its abolition in the Yyklu send provided.

Ultimately, the function of the assemblies involved in the control is assumed the generating arrangement with predeterminable data content described how they second memory field 5 internal memory generation, the second memory controller 6, the address counter 7, the first microprogram memory 8 and the comparator 9 are. The external program that arrives from control logic 1 determines the programmed one Function of all units. If the trigger pulse of the trigger logic 13 is present, reads the second memory field 5 with internal content generation the content of the first Liqueur program memories 8 in the prescribed order in their own internal Register and outputs this in the cycle of the clock pulses of the clock generator logic 15. The same output data can also be obtained at the input of the comparator 9, the this data, caused by the clock pulse, with the pulses of the first microprogram memory 8 compares. If the two strings of characters are the same, i.e. if the whole selected one The cycle has expired, the comparator 9 controls the cycle counter 7 in the basic position and the X, reading of the first micropro <jrammpeicher 8 begins from the beginning It can also happen that the address counter 7 is the first microprogram memory 8 will be moved to another selected address, in which case the another cycle can be started. Signaled for the second memory controller 6 the comparator 9 reaches the end of the cycle and continues the generation of a new one cycle suitable for the program. The required character shape comes through Changing these cycles, through their programmed chaining and with the target control options conditions.

The character forms generated by the character creation @ steep Any and with predeterminable data content, the almost unlimited Allowing variations can be called complex character series.

The goals set are with the character shape generator according to the invention reached completely. These goals are: - to generate innumerable, so to speak, infinite to be suitable for many combinations of characters - any selected combination of characters or to generate a series of character combinations easily and programmed, by using functional target control characters and with a proportionate small memory field in principle to produce infinitely long data series - the Generation speed of the character forines can also be very high - even during the generation of an infinitely long storage volume is only provided by the speed of the storage area is an obstacle - to carry out very complicated tasks the result is a very low storage capacity requirement, - the generation of the character series can be interrupted, and other external interventions are also conceivable in the test network.

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Claims (1)

Process for generating character series of any length and with any and predeterminable data content and arrangement of a character shape generator for the implementation of the process claims: 1. Process for the production of Character series of any length with any and pre-determinable data content, whereby one independently for the generation of the arbitrary and the predeterminable data innaite usable memory field is available, d u r c h g e -k e n n n z e i c h n e t that the trigger, shutdown and clock pulses are functionally poorly intervening, Targeting pulses are used that both memory fields in independently controllable and independently functional memory sectors are divided that operated separately during the execution of each function in an operation, parallel to each other switched and with the target-controlling impulses that can be virtually chained when generating any data content The procedure is such that the sectors of the memory field to generate the required Output character forms are loaded using the read-in program, with the Intervention by the target control impulses in the functional operation of the storage sectors is taken into account, i.e. with the independent triggering, ongoing operation, the interruption of ongoing operations and the shutdown of operations is that when generating the pre-determinable data content is proceeded in such a way, that to generate the required output character shapes the sectors of the memory field are charged by internal generation of the character shapes, with the help of the programs of the microprogram memory with the lower erograms for description the mathematical algorithm as well as using the predetermined read-in program, and during the charging, the intervention by the target control pulses in the functional Operation of the storage sectors is taken into account, i. with the independent triggering, the continuous operation, the interruption the ongoing operation and the shutdown of the operation is expected that further both in the generation of the arbitrary and in the generation of the Predeterminable data content is similarly proceeded in such a way that the memory fields can be read with the help of the reading program, with the loading of the memory fields target controls used should be taken into account, the Able: #en of the individual Sc # J: toi # en separated from each other by led ## irt and with rni t Auslös @@@ mpulsen is set in motion, the continuous reading with the clock pulses made and the continuous reading of the individual memory sectors in the moments and is interrupted for the duration determined by the reading program, as well as after reading the content of the individual S? .wi.chersektorel of Operation of these safety sectors with the switch-off pulses is set so that the individual memory sectors to generate the required output character shapes according to the reading program with the help of the trigger, shutdown and clock pulses for target control are connected in parallel or virtually chained to each other, and that by the interruption controlled by the clock pulse at any point the individual Memory sectors completely or as always predetermined repeated with new data content loaded, which content is read during the creation of new character shapes will. Arrangement of a character shape generator for carrying out the method according to claim 1, which has three assemblies, namely a component I with the functional Units, i.e. a sequential control logic (1), a time setting logic (2), a line adapter (12), a trigger logic (13), a shutdown logic (14), a clock logic (15) and a second microprogram memory (16), a component II, which generates any data content, and a component III, which can be predefined Data content is generated, that is not shown in component I, in the control units of the arrangement, the trigger logic (13) has a first and a second output (1302, 1303) for output pulses and a first functional input (1301), the shutdown logic (14) a second functional input (14C1), a first and a second output (1402, 1403) for Abstellim # ulse, a first and a second entry (1404, 1405) for cycle end pulses as well as a feedback output (1406) and the clock logic (15) a third function input (1501) and a first and a second Output (1502, 1503) for clock pulses has that in component II for generating of any data content three units, namely a first memory field (3) ver; irxierlichXen content with a data input (301), a data output (3C2), an Aoressen- and Steuereingar.g (303) and an output (304) for cylinder end pulses, a first memory controller (4) with an input (401) for trigger pulses, a Input (402) for Abstelljinnulse, an input (403) for Taktiinpulse and one Output (404) for address and control pulses and a first buffer register (10) with a time pulse input (1001), a data input (1002), a transfer input (1003) and an output (1004) for shaped data are provided that in the component III for generating the predeterminable data content three units, namely one second memory field (5) for internal content generation with a microprogram input (501), a control pulse input (502), a data output (503) and an output (504) for cycle end pulses, a second memory control (6) with one input (601) for triggering pulses, one input (602) for stopping pulses, one input (603) for clock pulses, one output (604) for control pulses, one output (605) for control and time setting pulses and a Y # mparatoreingang (606) and a second Buffer register (11) with a time pulse input (1101), a data input (1102), a transfer input (1103) and an output (1104) for shaped data, and a control circuit (7-8-9) are provided that the first memory field (3) from j and the second Memory field (5) from k independently controllable Memory sectors each with a storage capacity of up to n bits or of up to m bits is constructed so that the units in component II are connected to one another in such a way that that the first memory field (3) variable content via the file input (301) with the sequential control logic (1), via the data output (302) with the first Buffer register (10), the parallel-connected inputs (1 ... j) of the Memory sectors via the address and control input (303) with the same output (404) of the first memory controller (4), the parallel-connected outputs (1 ... j) the memory sectors via the output (304) for cycle end pulses with the shutdown logic (14), the inputs (401, 402 and 403) of the first memory controller (4) with the trigger logic (13), the shutdown logic (14) and the clock logic (15), the input (1001) for timing pulses of the first storage register (10) with one output (202) for timing pulses the time setting logic (2), the transfer input (1003) of the same register with the Reloading output (102) of the sequential control logic (1) and its shaped data output (1004) are connected to the line adapter (12) that the units of the component III are interconnected in such a way that the second memory field (5) for i.nternal Content generation via the microprogram input (501) at the microprogram output (803) the control circuit (7-8-9) ~ via c ## Datenausganu (5C3) on the one hand on the shaped Data input (1102) of the second intermediate storage register (11) and, on the other hand at the data part (901) of the control circuit (7- ° -9) is connected, the parallel switched inputs (1 ... k) of the memory sectors via the input (502) for Control impulses on Output (604) for control pulses from the second memory controller (6) and the parallel-connected outputs (1 ... k) of the memory sectors via the Output for cycle end pulses at the second input (1405) for cycle end pulses of the Shutdown logic (14) are connected, the inputs (601) for trigger pulses, (6o2) for Stop pulses and (603) for clock pulses of the second memory controller (6) each with the trigger logic (13), the shutdown logic (14) and the clock logic (15), their output (605) for control and triggering pulses and their input (606) for comparator pulses are connected to the connection points of the control circuit (7-8-9), and that the Input (1101) for timing pulses from the second buffer register (11) with the other output (203) for time setting pulses of the time setting logic (2), its transfer input (1103) with the transfer output (102) of the sequential control logic (1) and its shaped data output (1104) connected to the line adapter (12) is. 3. Arrangement according to claim 2 for generating only any character shape Data content, that is, that they are the units and the connections of components I and II. 4. Arrangement according to claim 2 for generating only the character shape predeterminable # n Data contents3, that is, they denote the units and the connections of components I and III. 5. Arrangement according to claim 2 or 4, d a d u r c h y e k e n n z e i c h n e t that the control circuit (7-8-9) has an address counter (7), a first Microprogram memory (8) and a logic comparator (9), that the control and timing inputs (701, 802 and 902) of these three units are connected to each other in parallel that the microprogram data output (804) of the first microprogram memory (8) with the microprogram data input (905) of the logical Comparator (9), the intervention pulse output (904) of the logical comparator (9) with the intervention pulse input (702) of the address counter (7) and the microprogram offset output (703) of the same unit with the microprogram offset input (801) of the first microprogram memory (8) is coupled, and that the microprogram output (803) of the first microprogram memory (8), the data input (901), the control and timing pulse input (902) and the comparator input (903) of the logical comparator (9) the connection points for the control logic <7-8-9).