DE3042888A1 - Low voltage Zener diode prodn. - by etching substrate and epitaxial deposition of p-silicon through window on N-silicon body - Google Patents

Abstract

In the prodn. of Zener diodes with a Zener voltage of 2.4-3.3.V an n-Si body is provided with an insulating film having a window and a strongly p-doped Si layer is deposited on the exposed surface by selective (gas phase) epitaxy. Growth involves cleaning the exposed surface by etching at a first temp. and deposition at a second, lower temp. The n-Si body pref. has a specific surface resistance of 0.003-0.004 ohm.cm and an overall specific resistance in the same region. The epitaxial Si film is 5-20 micron thick, whilst the insulating film is an oxide and is 0.5-1.5 micron thick. It has a ring with a width of 0.002-0.004 cm and an inside window dia. of 0.002-0.035 cm. The p-conductive film has a specific resistance of 0.001-0.003 ohm.cm and is of such a thickness that the pn-junction on its underside is not influenced physically or electrically by a conductor electrode applied to the p-conductive film, a suitable thickness being in the 1.5-3.0 micron range. Diodes with a low voltage and excellent electrical properties are produced in a relatively simple process without special costs.

Description

Zener diode

The invention relates to a method for producing a Zener diode with a Zener voltage in the range from 2.4 to 3.3 V, i.e. with a Zener diode very low tension. Selective epitaxy is to be used in this process will.

Alloying processes have already been used to make PN junctions with Achieve breakdown voltages below 3.3 V. However, alloyed transitions are not uniform, and Zener diodes made by such processes tend to be to a breakthrough on the surface. To be linked to a surface breakthrough To overcome problems, thought was given to a diffused transition before the Forming the alloyed transition, this diffused transition to serve as a guard ring. The arrangement of a diffused transition includes However, a separate process step.

It is also common to make PN junctions for Zener diodes by diffusion (see U.S. Patent 3,723,832).

However, it is not possible to produce an abrupt PN transition through diffusion to obtain, which is necessary for low breakdown voltages.

Selective epitaxy is used to create PN junctions, which lead to Zener voltages that are smaller than those that can be obtained by diffusion Tensions are.

However, a conventional ettaxia does not lead to Zener- Diodes with very low Zener voltages, for example to Zener diodes in the range of 2.4 to 3.3 V at 5 mA.

It is therefore the object of the invention to provide a method for producing Zener diodes with low voltage and excellent electrical properties specify, whereby this method can be carried out relatively easily and without any special effort should be.

This task is achieved with a method according to the preamble of the patent claim 1 according to the invention by the features specified in its characterizing part solved.

In the invention, therefore, a PN junction is made by selective epitaxy of P-type silicon onto a previously oxidized N-type silicon body in formed an open area where the oxide was etched away. The N-type silicon body can be a uniform silicon body with a resistivity in the range from 0.003 to 0.004 ohm.cm or a low specific N-type silicon body Resistance, on which a 5 to 20 lum thick N-type silicon epitaxial layer deposited with a specific resistance in the range of 0.003 to 0.004 Ohm.cm is.

The selectively applied P-type layer can be a specific one Have a resistance of 0.001 to 0.003 ohm.cm and a thickness of 1.5 to 3 µm. The P-type layer is grown in a gas phase epitaxial reactor, in that the N-type silicon body is etched at a first temperature and then heavily doped silicon is deposited at a second, lower temperature.

It has been shown that very low breakdown voltages in the area of 2.4 to 3.3 V can be achieved if the etching is carried out at about 1150 ° C and epitaxial deposition at a second temperature in the range of 1050 to 1150 0C. In particular, the Zener voltage is the lower The lower the second temperature is.

The invention thus enables a method for producing a Zener diode with a Zener voltage in the range of 2.4 to 3.3 V. The PN junction is through selective epitaxy of P-type silicon on a previously oxidized N-type Silicon body produced in an open area in which the oxide is etched away became. The N-conductive silicon body can have a uniform silicon body a specific resistance in the range 0.003 to 0.004 Ohm.cm or an N-type Silicon body of low resistivity with a thickness of 5 to 20 lum N-type silicon epitaxial layer that has a specific resistance in the Range from 0.003 to 0.004 ohm-cm. The selectively applied P-type Layer can have a resistivity of 0.001 to 0.003 ohm.cm and a thickness from 1.5 to 3.0 / µm. The P-type layer grows in a gas phase epitaxial reactor in which first the W-conductive silicon body is etched at a first temperature and then deposited heavily doped silicon at a second, lower temperature will.

The invention is explained in more detail below with reference to the drawing. 1 to 8 show sections of a semiconductor body to explain the various Method steps for producing a Zener diode according to a preferred embodiment the invention, 9 shows a characteristic curve of one produced according to the invention Zener diode, and FIG. 10 is a graph showing the dependence of the Zener voltage on indicates the temperature of the epitaxial deposition.

A preferred embodiment of the invention is described below described in more detail with reference to FIGS. 1 to 8 are corresponding to one another Components are given the same reference numerals.

1. Starting grains: The starting bodies are N-conductive silicon bodies, their dopant being phosphorus, arsenic or antimony. The crystal orientation can be in the (100) or (110) direction, or 2 to 60 from the (111) direction differ or be any other crystal orientation necessary for an epitaxial Growth is appropriate. The body thickness is in particular 0.02 cm to 0.05 cm, however, any other suitable thickness can be used. The specific one Resistance of the body is preferably dependent on the desired Zener voltage between 0.003 and 0.004 ohm.cm. The selection of the appropriate resistivity for the substrate can be found in the following table: Table Approximate Zener - Approximately more specific.

Voltage (V) Resistance of the substrate tes (Ohm.cm) 3.3 0.0040 3.0 0.0035 2.7 0.0032 2.4 0.0030 Instead of an N-conducting body With a specific resistance that is the same everywhere, an N-type epitaxial Layer with the desired specific resistance for the Zener voltage (cf. the table above) can be applied to a substrate body. The substrate body can have any reasonably low resistivity, preferably is less than 0.020 ohm. cm. In this last-mentioned embodiment, the Zener voltage by the resistivity of the epitaxial layer and not determined by the resistivity of the substrate. The epitaxial Layer preferably has a thickness between 5 and 20 µm.

Fig. 1 shows a section of an N-conductive silicon body 11 with an N-type silicon epitaxial layer 12.

2. Oxidation: After preparing a starting body, one grows thermal oxide layer on the silicon surface. The growth of an oxide can be any conventional and suitable oxidation method used in processing used by high quality single crystal silicon devices. The oxide that forming an insulating layer is preferably 0.5 to 1.5 µm thick. When the thick the oxide layer is too thin, the insulation properties are impaired; if the thickness is too great, the oxidation creates (mechanical) stresses in the semiconductor structure due to thermal mismatch.

The thermal oxidation is preferably in the temperature range of 1000 to 1200 0C executed.

Fig. 2 shows a section of an output body 11 and 12 after an oxide layer 13 is grown on both sides.

3. Back side grinding: The oxide on the back side of the semiconductor body is put together with parts of silicon by mechanical grinding, lapping or conventional chemical abrasion removed. The amount of silicon to be removed is dictated by the final desired body thickness, that particular Is 0.02 cm to 0.025 cm.

Fig. 3 shows a section of the body after the ablation has been completed of oxide and silicon.

4. Gettering: A conventional getter treatment is used to unwanted foreign matter and voids from the oxide-silicon interface remove where the transition will then be carried out.

This getter treatment consists of a very doping of phosphorus high concentration on the Silicius back and the oxide front. This Tangle step provides a low resistance layer on the back of the body to facilitate good electrical contact.

Fig. 4 shows a section of the body after completion of the getter treatment with the layer 14, which has a low resistance value.

While the getter treatment is conventional, it differs the use of gettering in the invention differs from the usual purpose. The usual Use of gettering takes place after the PN-t # has been produced, while with of the invention, gettering before making the transition is carried out.

This difference in process flow is successful for any one Production of Zener diodes of a very low voltage is required. If that Gettering is performed after the junction has been made, as is usually the case If so, additional procedural steps are required to complete the transition protect from a high concentration of phosphorus.

Furthermore arise due to the additional high temperature treatment higher Zener voltages.

5. Etching the Oxide: Traditional photolithography and etching technologies are used to selectively remove the oxide on the front side of the semiconductor body to etch. 5 shows a section of the semiconductor body with an oxidized one Ring 16 surrounding an open window 15 through which the surface of the epitaxial layer 12 is exposed. The window opening can be of any reasonable size; in particular it is 0.05 cm for a square die, while the window diameter ranges from 0.002 to 0.03 cm. The width of the oxide ring 16 should be in the range between 0.002 and 0.004 cm for optimal subsequent epitaxial growth lie.

6. Epitaxial growth: a heavily doped P-type silicon layer grows on the exposed surface of the semiconductor body by selective epitaxial growth Deposition through the window 15.

Fig. 6 shows a section of the semiconductor body with the preferably grown layer 17. This growth is the decisive process step in which a PN junction with a very low breakdown voltage is formed.

To achieve an abrupt transition for low Zener voltages is required, heavily doped silicon must be on the exposed surface by epitaxial growth in the presence of a dopant at somewhat lower levels Temperatures are plotted as the temperature at which the exposed surface is cleaned by etching. When the temperature for epitaxial growth is too high, the diffusion of the dopants over the junction is greater, which is the adversely affects the abrupt course of the transition. If the temperature is for the epitaxial growth is too low, polysilicon (silicon from Microcrystals).

In particular, the following process steps are preferred for the epitaxial growth in the manufacture of Zener diodes with breakdown voltages down to 2.4 V advantageous: The semiconductor bodies are first placed in a gas-phase epitaxial reactor etched using 0.05 to 0.20% hydrogen chloride in hydrogen carrier gas. the The reactor temperature is preferably 1150 ° C. or higher in order to achieve good etching results guarantee. The etching is carried out for a period of 2 to 8 minutes and preferably for about 5 minutes, after which the reactor temperature is raised to a second temperature in Range changed from 1050 to 1150 0C depending on the desired Zener voltage.

When this second, lower temperature is reached, a Gas phase silicon source and a dopant are added to the reactor for 4 to 6 min. The source of silicon is preferably 0.1 to 3 9 (from silicon tetrachloride, trichlorosilane or silane. The actual proportion depends on the structure of the reactor.

Of these silicon sources, silicon tetrachloride is preferred. as 20 to 30 ppm of diborane are doped into the reactor along with the silicon source entered. In addition, up to 1 fi hydrogen chloride can also be introduced into the reactor, to control the growth of silicon on the insulating layer iu. The one with these Carrier gas used in materials is preferably hydrogen.

As an example, semiconductor bodies are used at a reactor temperature of 1150 ° C. etched in 0.10% hydrogen chloride in a hydrogen carrier gas for 5 min. the The real temperature is then lowered to 1075 ° C., at which temperature 0.3 ° C. Silicius tetrachloride, 0.1% hydrogen chloride and 24 ppm diborane into the reactor can be entered for 5 min. The chemical reaction leads to a heavily P-doped one Epitaxial layer that is 1.5 to 3 lum thick.

7. Passivation: A layer of glass such as silicon nitride (Si3N4) or any suitable passivation material that protects the device from ion contamination protects, is applied to the surface of the semiconductor body by a process, which leads to a satisfactory passivation layer of suitable thickness, wherein the deposition temperature does not exceed 900 ° C. for more than 10 st.

After the passivation material has been applied, a window is opened for the subsequent metallic contact for electrical connection is opened. Every Appropriate photolithography and etching techniques can be used to make the window to open.

7 shows a cross section of the semiconductor body, with a passivation material 18 is applied.

A window 19 is opened in the epitaxial layer 17.

8. Metallization, subdivision and nacking: any suitable metallization system, good physical adhesion to the silicon surface and good electrical adhesion Connection supplies can be used for electrical contact provided there is is compatible with packaging. A preferred system is palladium silicide the front window area, on which a thick layer of silver, especially 0.002 to 0.006 / µm thick, is applied by conventional electrodeposition.

8 shows a section of the semiconductor body with a palladium silicide layer 20, which is applied to the P-type epitaxial layer, and a thick silver layer 21 applied to the palladium silicide. A network layer 22 is also applied to the back of the semiconductor body.

The backside metallicization can be made up of the following combinations consist of metals, but these are not exclusive: a) chromium then silver, b) chrome then silver then gold, c) titanium then silver, d) gold then silver, and e) Nickel then gold.

After a suitable alignment or centering, the semiconductor bodies divided and packaged or provided with a housing.

9. Control of the Zener voltage: A typical characteristic of a Zener diode very low voltage is shown in Fig.

9 shown. In this figure, the curve 23 suddenly falls in the lower left quadrant, reaching 5 mA at 2.4 V. It has shown, that a Zener diode with this characteristic by means of a selective epitaxial Deposition can be established provided certain conditions are maintained Of primary importance is the temperature at which the preferably epitaxial Growing up is done. As indicated above, lower reactor temperatures must be used are maintained during epitaxial deposition than during etching, to create an abrupt transition.

Fig. 10 shows the relationship between the Zener voltage and the reactor temperature while the deposition is. At 1150 0C a Zener diode with 3.3 V.

When the reactor temperature is lowered, the Zener voltage drops correspondingly along a curve 24. At 1075 0C the Zener voltage is 2.4 V. The temperature can be lowered to around 1050 0C, but are below from this temperature the results are less reproducible. This is based on that at lower temperatures polysilicon grows instead of a single crystal. This leads to poorer electrical properties; for example, is the reverse leakage current at 1 V greater than 100, u1.

10 Figures 31 claims Blank page

Claims (31)

A method for producing a Zener diode with a Zener voltage in the range from 2.4 to 3.3 V, indicated by (a) Production of an N-conductive silicon body, (b) production of an insulating layer on the surface of the body with a window in which the surface is exposed, (c) Growing a heavily P-doped silicon layer on the exposed surface by selective epitaxial deposition through the window, with the growth comprises: (1) etching the exposed surface at a first temperature around the To clean the surface, (2) deposit heavily doped silicon on the exposed Surface by epitaxial growth in the presence of a dopant a second temperature that is less than the first temperature. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the N-conductive body has a specific resistance on its surface in the range of 0.003 to 0.004 ohm-cm. 3. The method according to claim 2, d a d u r c h g e -k e n n z e i c h n e t that the N-conducting body has a uniform specific resistance everywhere having. 4. The method according to claim 2, d a d u r c h g e -k e n n z e i c h n e t that the N-type body is an N-type silicon epitaxial layer with a specific Resistance in the range of 0.003 to 0.004 Ohm.cm an N-type substrate having a low resistivity. 5. The method according to claim 4, d a d u r c h g e -k e n n z e i c h n e t that the silicon epitaxial layer has a thickness in the range from 5 to 20 μm owns. 6. The method of claim 1, d a d u r c h g e -k e n n z e i c h n e t that the insulating layer is an oxide. 7. The method according to claim 6, d a d u r c h g e -k e n n z e i c h n e t that the insulating layer has a thickness in the range of 0.5 to 1.5 µm. 8. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the insulating layer is a ring with a width of 0.002 to 0.004 cm and has an inner window diameter of 0.002 to 0.035 cm. 9. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the P-type layer has a resistivity in the range of 0.001 to 0.003 ohm-cm. 10. The method of claim 1, d a d u r c h g e -k e n n z e i c h n e t that the P-type layer has such a thickness that that on the underside The PN junction formed by the P-conductive layer is neither physically nor electrically is influenced by a conductor electrode, which is then connected to the P-type Layer is applied. 11. The method according to claim 10, d a d u r c h g e k e n n z e i c Note that the P-type layer has a thickness in the range from 1.5 to 3.0 µm. 12. The method according to claim 1, d a d u r c h g e -k e n n z e i c It should be noted that process step (c) is carried out in a gas-phase epitaxial reactor will. 13. The method according to claim 12, d a d u r c h g e -k e n n z e i c Note that the first temperature is about 1150 ° C. 14. The method according to claim 13, d a d u r c h g e -k e n n z e i c It should be noted that step (c), (1) is an etching of the exposed surface with 0.05 to 02, ~ hydrogen chloride in a carrier gas for 2 to 8 min. 15. The method according to claim 14, d a d u r c h g e -k e n n z e i c h n e t,. that the carrier gas is hydrogen. 16. The method according to claim 12, d a d u r c h g e -k e n n z e i c It should be noted that the second temperature is in the range from 1050 to 1150 ° C. 17. The method according to claim 16, d a d u r c h g e -k e n n z e i c Note that method step (c), (1) introducing a gas phase silicon source and a dopant in the epitaxial reactor for 4 to 6 minutes. 18. The method according to claim 17, .d a d u r c h g e -k e n n z e i c h n e t that 0.1 to 3,960 of the silicon source consists of a material which is selected from the group consisting of silicon tetrachloride, trichlorosilane and silane. 19. The method according to claim 18, d a d u r c h g e -k e n n z e i c Note that the source of silicon is silicon tetrachloride. 20. The method according to claim 17, d a d u r c h g e -k e n n z e i c Note that the pollutant is 20 to 30 ppm of diborane. 21. The method according to claim 17, d a d u r c h g e -k e n n z e i c Note that up to 1, ~ hydrogen chloride is also introduced into the epitaxy reactor is used to control the growth of silicon on the insulating layer. 22. The method according to claim 17, d a d u r c h g e -k e n n z e i c Note that hydrogen gas is also introduced into the epitaxy reactor as a carrier gas will. 23. The method according to claim 1, g e k e n n z e i c h -n e t through a getter process step for the N-conductive body with the insulating layer before the production of a P! transition. 24. The method according to claim 23, d a d u r c h g e -k e n n z e i c Note that the gettering step comprises doping the body with phosphorus. 25. The method according to claim 1, g e k e n n n z e i c h -n e t through Applying a passivation layer made of a passivation material to the insulating layer and the P-type layer. 26. The method according to claim 25, d a d u r c h g e -k e n n z e i c That is, the passivation material is glass. 27. The method according to claim 25, d a d u r c h g e -k e n n z e i c Note that the passivation material is silicon nitride. 28. The method according to claim 25, g e k e n n n z e i c h -n e t through Opening a window through the passivation material to the P-type layer and Applying metallization to the P-type layer through the window in order to establish electrical contact. 29. The method according to claim 28, d a d u r c h g e -k e n n z e i c That is, the metallization is palladium silicide, followed by silver. 30. The method according to claim 28, g e k e n n n z e i c h -n e t through Applying a second metallization to the back of the body. 31. The method according to claim 28, d a du r c h g e -k e n n z e i c Note that the second metallization is chrome, followed by silver.