DE3035492C2 - Circuit arrangement for controlling the direct access of an observation computer to the central memory of a data processing system - Google Patents

Description

a) The address bus of the DVA (1) is coupled to an address comparator unit (7) which, when the respective address bus signals coincide with their inputable comparison addresses (VA _n ), which correspond to the end of each program or program part of the DVA that changes the data to be observed, the beginning of the access of the observation computer (5) to the central memory issues determining signals (DK _n ) ;

b) the signals (DK _n ) emitted by the address comparator unit act on an exclusion circuit (U), the output signal (BE) of which is accessed by the observation computer (S) via a memory coupling unit (12) connected to the address and data bus of the DVA (1). initializes, secures the exclusive occupancy of the central memory (3) by the monitoring computer until its freely programmable access, comprising one or more memory cycles, has been completed, and causes a timer (22) to transmit time information to the monitoring computer;

c) the output signal (BE) of the exclusion circuit is withdrawn by the observation computer after its access has ended.

2. Circuit arrangement according to claim!, Characterized through the following features:

a) The address comparison unit (7) can additionally enter η comparison addresses which each correspond to the start of programs or program parts which change the data to be observed from the DVA (1);

b) if these comparison addresses coincide with the respective signals on the lines of the address bus (AB) , the address comparator unit outputs the access-blocking signals (DI _n ) ;

c) each access-determining signal (DK _n ) remains stored until the arrival of the next following signal (DI _n ) blocking access;

d) the stored access signal (DK) is conjunctively linked with a time freely selectable trigger signal (ZA) of the observation computer (5) to the output signal (BE) of the exclusion circuit (11).

The present invention relates to a circuit arrangement for controlling the direct Access of an autonomously working observation computer to the central memory of a data processing system. Such a circuit arrangement can be used to measure the dynamic behavior of a data processing system and is from Edward Yourdon »Design of On-line Computer Systems» Prentice-Hall, Ina Englewood Cuffs, New Jersey, 1972, Pages 155 to 156 known and allows assessment the performance of data processing systems, in particular their behavior over time. It can be so the dynamic operating procedures on a data processing system and the resulting response times, Measure throughput rates, workloads, etc., ίο with which a targeted optimization of the operating behavior the data processing system becomes possible.

If one for the sake of minimizing the temporal repercussions on the observed Data processing system, the complete management of access to the central memory exclusively the If the observation computer transmits, then this is the case with complex data structures in the aforementioned Literature reference not dealt with problem: Complex data structures are characterized by the fact that several individual data in a certain structure are linked to create a certain to express the internal state of the data processing system, such as B. the occupancy of a certain Computer resources by a particular program.

When the DVA changes into a new internal state, a whole series of individual data must first be entered be changed by the central processor of the data processing system before the new internal state of the The data structure to be observed is consistently mapped and only one consistently mapped state can usefully be observed and subsequently evaluated. So it must be ensured that the monitoring computer has access to a complex data structure in the system to be monitored can only take place when this data structure is in a consistent state, and that the consistency of the data structure is not guaranteed during the access of the monitoring computer ■ »ο monitoring system canceled running programs will.

The solution to this new problem is achieved according to the invention by the in the characterizing part of the Main claim specified means. The basic idea of the present invention is therefore by means of a hardware circuit, d. H. the times without using the observation computer to record, to which a direct access of the observation computer to the data of the central memory To assess dynamic operational processes, it makes sense to set the requirements for this access create and the possibility of access while blocking the central processor of the data processing system, d. H. with the exclusive use of their central memory by the observation computer, as long as to be kept open until the observation computer has its freely programmable access to the data this store has completed. This makes for an extremely quick and yet permissive observation consistent data structures of the data processing system possible.

A further development of the invention with which not only the earliest possible point in time is detected which access to the central processor through the observation computer is possible, but the whole possible access period is characterized in the subclaim. This makes it possible to time the access operation of the observation computer

Respect to be carried out more freely.

The invention is to be illustrated in more detail below by way of example with the aid of the figures. In FIG. 1 shows the data processing system to be observed in the form of a process computer 1 in a block diagram. The process computer 1 comprises a central processor 2, a central memory 3 and input / output interfaces denoted by 4, to which peripheral devices (not shown) can be connected. Central processor, central memory and interfaces communicate with one another in the usual way via the address bus A θ, the data bus DB and the control lines ST. The observation computer 5 is in principle constructed in the same way as the process computer 1, however, with regard to its storage capacity according to the tasks to be performed by it, it is generally much smaller and is equipped with the usual standard peripherals 6

The circuit arrangement according to the invention consists of an address comparator unit 7, a memory coupling unit 12, an exclusion switch 11 and a timer 22. The address comparator unit 7 is connected to the address bus AS of the computer 1 to be monitored. It consists of a controller 8 for decoupling the memory address bus of the computer 1 to be monitored and the comparator 9. Decoupling device and comparator are circuits known per se. The address comparator unit 7 compares the addresses appearing on the address lines of the address bus AB with η preset, significant comparison addresses VA _n which can be entered externally, for example manually via a control panel 10, into the comparator 9. If one of the set comparison addresses VA _n coincides with an address occurring on the address bus AB of the computer 1, a signal DK _n appears at the output of the address comparison unit 9 . If the memory division is known, this coincidence signal should be used to determine when such operations which change the data structure to be observed have come to an end. The significant comparison addresses selected are therefore those which each mark the end of the programs or program parts that change the data to be observed. The individual coincidence signals DK _n can either be coded or fed to the observation computer via η different lines and there trigger a specific interruption reaction in the observation computer central unit. The coincidence signals DK _n are fed to an exclusion circuit 11, the output signal BE of which activates the memory coupling unit 12 and the timer 22 connected to the respective buses and control lines of the computer 1 to be observed and of the observation computer 5.

The memory coupling unit 12 contains a per se known DMA (Direct Memory Access) controller 13, which allows direct access to the central memory 3 and an address and data transmission device 14 coupled to the buses a, b and the control line st of the monitoring computer 5, which also is known per se. It also has an interface controller 15, which is now designed so that when the signal df is applied to its input, the "capture" of buses AB and DB of computer 1 is initialized and, once these buses have been captured, the exclusive use of the central memory of the computer 1 by the monitoring computer 5, that is, its sole access to the data in the central memory 3 is ensured as long as this signal lasts. With a signal ZB sent by the observation computer 5 to the closing circuit 11, its output signal BE is made to disappear, whereby the "bus conquering circuit" 15 is inactivated

ίο and the data and address buses of the computer 1 for its central processor are released again. With the output signal BE, which simultaneously with the respective end of a program measuring changing the data to be observed, marking

¹ S denzimpulses DK _n in the exclusion circuit U is formed, the observation computer 5 becomes now possible access to the buses of the prompts to be observed computer emitted by the computer 5 after completion of its programmable access signal ZB causes disappearance of the output signal BE, further is still fed to a timer 22, whereby a temporal logging of the individual processes is made possible.

The previously described mode of operation of the monitor system according to the invention referred to the so-called passive operation, in which the observation computer is caused by the coincidence signals DK _n to access the memory of the system to be observed. For active operation, in which the initiative for access is to come from the monitoring computer at a freely selectable time, additional signals Dl _n must be formed to detect the appropriate time for access to the central memory of the computer 1, each of which changes the beginning of the data to be observed Mark programs. This can be done by entering η additional comparison addresses corresponding to the respective program start and corresponding additional comparison elements in the comparator 9. The sensible period for the beginning of an access is then the time between the appearance of a pulse DK _n and the chronologically next pulse DI _n . During this period of time, a signal ZA output by the observation computer can switch the exclusion circuit 11 to

Initiate the delivery of an output signal BE , this in turn continuing until the signal ZB is output again from the monitoring computer after the access has been completed. In this way, even in active operation, access by the monitoring

computer admitted to the data of the central memory 3 if its data structure is in a consistent state.

F i g. 2 shows one possibility for realizing the exclusion circuit If shown in FIG. The Andes

Coincidence signals DI \ to Dl _n and DK \ to DK _n arising from the outputs of the address comparator unit , which occur as pulses separated from one another in time, are fed to two OR gates 16 and 17 and act on the dynamic inputs

a bistable flip-flop element 18. The signal ZB supplied by the observation computer 5 to terminate its occupancy of the central memory 3 acts on a further input of the OR element 16. The output signal DK of the bistable flip-flop 18

applied to one input each of two AND gates 19 and 20, the outputs of which are routed to an OR gate 21 which supplies the signal 0 £ requesting the bus conquest. The other two inputs of the AND gate

19 and 20 are acted upon by a signal PB which can be input externally to the exclusion circuit 11, this being inverted in the input of the AND element 20. The signal PB is input when the monitor system is to work in passive mode.

1 sheet of drawings

Claims (1)

Patent claims: 1. Circuit arrangement for controlling the indirect access of an autonomously operating observation computer to the central memory of a data processing system, characterized by the following features: