DE3032332A1 - OUTPUT STAGE OF A MONOLITHICALLY INTEGRATED CHARGE SHIFT ARRANGEMENT - Google Patents

Abstract

1. An output stage of a monolithic integrated charge transfer device arranged on a semi-conductor body (1), comprising an amplifier (7) which has a feedback circuit with a capacitor (C) which can be bridged by a periodically operable switch (T1), where the amplifier (7) is in the form of a differential amplifier whose first input (6) is connected to the output of the charge transfer device and whose second input (8) is connected to a constant voltage, in particular a reference voltage, characterised in that the first input (6) is connected to a semiconductor zone (4) which represents the output of the charge transfer device, whose conductivity type is the opposite to that of the semiconductor body (1), and which is supplied with charge quantities transported in the charge transfer device.

Description

SIEIiElTS AKTIENGESELLSCHAFT Our mark

Berlin and Munich YPA 80 P 7 1 2 7 DE

Output stage of a monolithically integrated charge shifting arrangement.

The invention relates to an output stage of a monolithically integrated charge shifting arrangement according to the preamble of claim 1.

Such an output stage is from the article "Few Charge-Differencing Technique for CCD Transversal! Filters" in the "Electronic letters" of April 12, 1979, Vol. 15, Ht. 8, pages 229 to 230, in particular S ¹ Ig. 1, known. The amplifier is designed as a differential amplifier, the output of which is capacitively fed back to its negative input. The latter is connected to one part of a two-part transfer electrode of the transversal filter. Between this part of the transfer electrode and the semiconductor body there is a capacitance, the size of which depends on the space charge zone below the electrode part. However, since the expansion of the space charge zone is influenced by the charge quantities transported in the transversal filter and dependent on different instantaneous values of an input signal, the conversion of the charge quantities into output signals of the differential amplifier is not linear. This non-linearity exists even though the electrode part connected to the negative amplifier input is kept practically at a constant potential because of the positive amplifier input which is at a reference potential.

The invention is based on the object of providing an output stage of the type mentioned at the outset which is as linear as possible To achieve conversion of the supplied, signal-dependent amounts of charge into voltage signals. This up-

St 1 DxI / 08/25/1980

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gate is characterized according to the invention by those in claim 1 Features solved.

The advantage that can be achieved with the invention is in particular that the effect of the signal-dependent space charge capacity is largely turned off. Because of the connection of the absorbed charge quantities Semiconductor region with the input of the capacitive feedback amplifier are changes in charge the space charge capacity largely prevented.

Claims 2 to 4 are directed to preferred configurations and developments of the invention.

The invention is explained in more detail below with reference to the drawing. It shows:

Pig. 1 an embodiment of the invention, ! "Fig. 2 voltage-time diagrams to explain Fig. 1 and

3 shows an alternative circuit to a partial circuit by Pig. 1.

FIG. 1 shows a semiconductor body 1, for example made of p-doped silicon, on which a charge transfer device (CTD) is built. This has a number of elements, each of which contains a predetermined number of transfer electrodes that are separated from the boundary surface 1a of the semiconductor body 1 by a thin electrically insulating layer 2, for example made of SiOp , and each with one of a predetermined number Number of mutually phase-shifted clock voltages are connected. In FIG. 1 it is assumed that each element of the charge transfer arrangement has four transfer electrodes which are connected to four clock voltages which are phase-shifted from one another. Only the transfer electrodes E ,, belonging to the last element E,

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to E. shown, to which the clock voltages 01 to 04 are fed. An output electrode E is connected to a constant voltage U, which generates a potential threshold below E ^.

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An n ⁺ -doped semiconductor region 4> the barrier layer capacitance of which is labeled C. with respect to the semiconductor body 1 is connected via a line 5 to the negative input 6 of a differential _{amplifier 7, the positive input 8 of which is connected to a reference voltage U Ref} ". The output 10 of the differential amplifier 7, which represents the circuit output, is connected to the input 6 via a capacitance C. Furthermore, the series circuit of two field effect transistors CDI and T2 is connected between the circuit points 6 and 10 so that it is parallel to C. The gate electrode of T1 is assigned a clock voltage 0 _R via a terminal 11. The source-drain path of T2 is short-circuited by a connection 12, the gate electrode of T2 being connected to the output of an inverter 13, the input of which is connected to the terminal 11.

In a manner known per se, a sequence of negative amounts of charge, which correspond to successive sample values of an analog input signal, is shifted in the direction of arrow 3 under the influence of clock voltages 01 to 04 (FIG. 2). Each of these amounts of charge, which is just " below E λ when a pulse of 04 occurs, is transported over the potential _{threshold below E 0} into the n ⁺ -doped region 4 when the trailing edge of this pulse occurs.

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animals. If the differential amplifier 7 has a sufficiently large voltage gain (eg v = 1000), the potential of the input 6 corresponds approximately to the potential of the input 8, so that the area 4 is connected to a voltage which corresponds _{approximately to the reference voltage IL, f.} Any amount of charge penetrating into 4 causes

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a corresponding charging of the capacitance C, with a circuit output 10 proportional to the amount of charge Output voltage signal occurs. In doing so, however the voltage at area 4 is not influenced by this amount of charge in the steady state, see above that the junction capacitance G. is constant to this extent remain. Subsequently, T1 is switched to the conductive state by a pulse of voltage 0-d (FIG. 2), see above that the capacitance C discharges again and the circuit prepared for the evaluation of the next following amount of charge transported into the semiconductor region 4 is. To the from terminal 11 over the gate-drain capacitance and gate-source capacitance of 11 in the feedback circuit To compensate coupled pulse components of 0π, the inverted clock voltage becomes 0 · ^ the Gate electrode fed from 12. Here are momentum components the inverted clock voltage via the gate-drain capacitance and gate-source capacitance of 12 into the feedback circuit coupled in, which largely compensate for the pulse components coupled in via 11.

Keeping the voltage across the semiconductor region 4 constant results in the conversion of the signal-dependent Amounts of charge in the output voltage signals U ^ takes place very precisely and with a very high degree of linearity.

Pig. 3 shows a variant of the subcircuit of FIG. 1 located between the circuit points 14 and 10. Here, the differential amplifier 7 is replaced by an inverter. In the discharge phases of the capacitance C, that is, during the occurrence of the pulses 0 _R , the circuit point 14 reaches a predetermined potential, which is thus also fed to the semiconductor region 4.

In addition to the previously described charge shifting arrangement

VPA 80 P 7 t 2 7 DE

with 4 shifting electrodes the output stage can be adjusted according to of the invention can also be used in such arrangements that according to the two-, three- or multi-phase system work. Likewise, the CTD arrangement can also be on a η-doped semiconductor body, the semiconductor region 4 then being ρ -doped and the supplied E. Voltages are each of opposite polarity.

4 claims
3 figures

Claims (4)

Claims Output stage of a monolithic, integrated charge transfer arrangement arranged on a semiconductor body with an amplifier that has a feedback circuit with a switch that can be actuated periodically Has bridgeable capacity, thereby characterized in that the amplifier input (6) with a semiconductor region (4) of the semiconductor body (1) opposite conductivity type to that in the charge transfer device transported amounts of cargo are supplied. 2. Output stage according to claim 1, characterized in that the amplifier is a differential amplifier (7) is formed, the negative input of which with the semiconductor region (4) and the positive input Input (8) is connected to a constant voltage, in particular to a reference voltage (U ^ ~). 3. Output stage according to claim 1, characterized that the amplifier is designed as an inverter (15). 4. Output stage according to one of claims 1 to 3 »characterized in that the switch consists of a field effect transistor (£ 1), the gate electrode of which is connected to a pulse voltage (0-d) is, and that in series with the source-drain path of this field effect transistor (T1), the conductively bridged source-drain path a second, identically constructed field effect transistor (T2) is arranged, the gate electrode of which is connected to the gate electrode of the first field effect transistor (H) via a second inverter (13). ORIGINAL INSPECTED