DE3028561A1 - Integrated MOS electronic component - has V=shaped grooves arranged next to bit conductive diffusion region, using additional etch-selective layer - Google Patents

Abstract

The V-shaped grooves of the highly integrated MOS components are arranged adjacent to the diffusion region, serving as a bit line, using an additional etch,selective layer. They form with this region at least one transistor. The additional layer pref. consists of a silicon nitride. This layer is deposited on the diffusion layer after thermal oxidation. After a selective etching it serves for structuring of the diffusion layer. The nitride layer is selectively etched away after etching the V-shaped holes. The nitride layer (5) is pref. deposited on the substrate (8) prior to depositing of the diffusion layer (3). The second selective etching of the nitride layer provides structuring of the V-MOS regions (11). After a local thermal oxidation of the uncovered silicon region, the remaining nitride layer is removed by third etching step. A highly integrated memory is produced with reduced capacitive coupling between word and bit lines.

Description

Highly integrated component in V-MOS technology.

The invention relates to a highly integrated module in V-MOS technology.

In highly integrated NOS modules, the individual components must such as transistors, resistors, capacitors are arranged with the smallest possible space requirement will.

This problem occurs particularly in memory modules that work dynamically in the design of the memory cell. By using V-MOS technology (e.g. Solid State Electronics, 1976, Vol. 19, pages 159 to 166; Electronic Letters, Sept. 20, 1973, Vol. 9, pages 457, 458) is here with the same structural fineness a significant reduction in area compared to surface cells has already been achieved. In this V-MOS technology, the control electrode of the MOS transistor is produced a V-shaped trench in an epitaxial layer applied to a Si semiconductor substrate etched. An insulating layer made of silicon dioxide is applied in the trench which then the connection for the control electrode of the MOS transistor is arranged. The channel of the MOS transistor runs in the flanks of the V-shaped trench. the two controlled electrodes of the MOS transistor can, for. B. next to the V-shaped Be arranged ditch. Further details of this V-MOS technology can be found in the indicated references. Disadvantage of the previously used V-MOS pyramid cell is the still relatively large coupling capacity between the word and the bit line. This not only reduces the load on the word line (speed problem), but also that of the bit line (interference problem) is significantly increased.

Single-transistor memory cells in V-MOS technology are also already known, (compare e.g. the magazine Elektronik 1977, issue 11, page 48, fig. 5). That Coupling problem with these V-MOS memory modules can only be mastered in this way that the number of memory cells per bit line is kept low, the area-specific Capacitance of the coupling capacitor made small and the diffusion depth of the bit line is reduced. However, the latter measure increases the bit line resistance and thus the runtime of the read signals (speed problem).

The object of the present invention is to provide highly integrated V-MOS components to create with the help of suitable methods, in which the disturbing influence of the coupling capacitance between word and bit lines is reduced.

To solve this problem, according to the invention, the highly integrated Building block designed in such a way that the V-shaped trench using an additional Etch-selective layer arranged next to the diffusion region serving as a bit line are and with this each form at least one transistor.

By these measures it is achieved that with so-called pyramid transistors only about 25% of the previous coupling capacity is available. The necessary Process variants can be implemented relatively easily and without increasing the number of masks in the existing ones Process to be introduced.

Advantageously, silicon nitride is used as the etch-selective layer.

To generate the corresponding V-MOS structures, the procedure is as follows: that the nitride layer after the thermal oxidation of the applied to the substrate Diffusion layer is applied over the entire area and that it is selective after a first Etching to structure the Diffusion layer is used and that the Nitride: layer removed by a second selective etching after the V-hole etching will. (Figures 3 and 5).

Another variant of the method is that the nitride layer takes place over the entire area before the diffusion layer is applied to the substrate and that after a first selective etching for structuring the diffusion paths serves that after the application of the diffusion paths through a second selective Etching of the nitride layer, the V-MOS areas are structured and that after a local thermal oxidation of the uncovered silicon areas the remaining Nitride layer is removed by a third selective etch (Fig. 4 and 5).

In these two processes, the nitride layer is used for structuring of the diffused areas are used. The resulting V-MOS transistors are included self adjusted.

Another method is characterized in that on the epitaxial Layer silicon nitride applied over the entire area and this after a first etching that then serves to structure the diffusion paths and field areas the well areas etched and the diffusion layer applied and after a thermal Oxidation of the doped areas by a second selective etching of the rest Nitride layer is removed (Figs. 6 and 7).

A fourth process variant provides that after the etching of the tub areas silicon nitride is deposited over the entire surface, which after an initial selective Etching is used to structure the diffusion paths and that after a thermal Oxidation of the doping areas by a second selective etching of the rest Nitride layer is removed (Fig. 8).

In the latter two processes, the nitride layer is used as Used as a replacement for the V-hole mask. These two procedures also arise self-aligned V-MOS transistors.

If you see a buried layer in the usual way before, single-transistor memory cells can thereby be improved in a simple manner Generate V-MOS technology.

Based on the known arrangements according to Figures 1 and 2 and the Arrangements according to the invention according to FIGS. 3 to 12, the invention becomes more detailed explained.

1 shows a cross section of a conventional V-MOS memory cell V-MOS technology, FIG. 2 shows the plan view of a V-MOS memory cell in conventional V-MOS technology, Fig. 3 is a plan view for the embodiments according to the FIGS. 4 and 5, FIG. 4 the essential steps of the process sequence for a first exemplary embodiment of the invention according to FIG. 3, FIG. 5, the essential steps of a process sequence for a second embodiment of the invention according to FIG. 3, FIG. 6 is a plan view for an embodiment according to FIG. 7, FIG. 8, the essential steps of a Process sequence for a fourth exemplary embodiment in which the nitride mask is used as a replacement is used for the V-hole mask according to Fig. 9, Fig. 9 is a plan view for the Embodiment according to FIG. 8, FIG. 10 a V-MOS transistor memory cell, at of the bit lines at the end of the V-shaped trench introduced Fig. 11 is a top plan view of a V-MOS transistor structure with great efficiency Channel length, FIG. 12a shows a plan view of a space-saving V-MOS double transistor arrangement according to the invention, FIG. 12b shows the circuit diagram associated with FIG. 12a.

FIG. 1 shows a known MOS single-transistor memory cell using V-MOS technology in cross section. The concealed layer 5 is created by an n + diffusion in the substrate generated. Subsequently, one leaves an epitaxial which is weakly doped with respect to the substrate Grow layer, on the surface of which a structured n + diffusion then takes place.

Through this diffusion layer 3 and the epitaxial layer 7 Then a V-shaped trench is made up to the area of the hidden layer 5 etched in.

After several more steps involving silicon oxide and silicon serve as etch-selective layers, the word line made of aluminum is then used 2 applied in the V-shaped trench both between the diffusion layer 3 as well as the epitaxial layer 7 and the hidden conductor 5 come to lie, a layer of silicon oxide between these three layers and the aluminum 4 is arranged. The interfering coupling capacitances 1 are formed between the Word line 2 and the diffusion layer 3 serving as a bit line.

FIG. 2 shows a plan view of this V-MOS cell according to FIG. 1. Since the V-shaped indentation lies in the middle of the diffusion layer 3, the Coupling capacity 1 evenly around the V-shaped recess.

A substantial improvement can be achieved if one works accordingly the proposal according to the invention, the diffusion paths 3 laterally next to the V-shaped Puncture 12 is arranged so that the word line 2 and the bit line 3 are only in one Cover small area, as shown in Fig. 3 in plan view.

In Fig. 4 the essential steps of the process sequence for a first embodiment of FIG. 3, in which the V-MOS technology according to the Invention from the previous V-MOS technology is shown.

The individual steps are as follows: Step 1a, # n + diffusion of the buried layer (mask 1) 1b, growth of the epitaxial layer 7 1o, all-over n + diffusion 3 of the surface 1d, thermal oxidation 6 of the surface: approx. 5000 i SiO2 (optionally pyrolytic oxide deposition) le, full-surface deposition of Silicon nitride 9 and structuring (mask 2) by selective nitride layer etching If, etching of the thermal oxide 6 in the field area Ig, removal of the n + diffusion 3 in the field area Ih, local oxidation 10 in the field area: approx. 7000 i SiO2 ii, V-perforation 11 with nitride layer as an additional etched edge (mask 3) Ij, removal of the nitride layer 9 (selective nitride layer etching) 1k, gate oxidation 11, etching of the contact holes (Mask 4) Im, depositing and structuring the gate metal 2, e.g. B aluminum (mask 5) In, deposition of the protective oxide 1o, release of the connection pads (mask 6) Fig. 4a shows the state after step 1d, FIG. 4b after step Ig, FIG. 4c after step 1i and FIG. 4d after step Im.

A second embodiment according to FIG. 3 is shown in FIG shown. It differs from the first exemplary embodiment according to FIG. 4 in that it is different Order of individual process steps. They result for this second exemplary embodiment as follows: Step 2a, like 1st modification 2b, 2c, full-area deposition of Silicon nitride 9 (on approx. 100 i Silo2) and structuring of the diffusion paths (mask 2) by first etching the nitride layer 2d, n + diffusion 3 or n + implantation Leave a thin oxide layer in the exposed tub areas 2e, structuring of the V-MOS regions 11 by second etching of the nitride layer (mask 3) 2f, local Oxidation 10 of the uncovered silicon areas (field area and diffusion paths) #ca. 700 i SiO2 2g, removal of the nitride layer 9 (selective nitride layer etching) with underlying thin (approx. 100 #) oxide layer 2h, V-hole etching 11 with the existing Oxide edges as an etching mask Continue with steps 1k ... 1o of the first exemplary embodiment.

5 shows the essential steps of the process sequence of cross-sections, namely Fig. 5a the state after step 2c, Fig. 5b after the step 2d, FIG. 5c after the step 2f and FIG. 5d after the step 2m.

In these two embodiments, the nitride layer is used for structuring of the diffused areas are used.

The top view for a third exemplary embodiment is shown in FIG. 6 shown. The following sequence of steps results for the third exemplary embodiment.

Step 3a, like 1st modification 3b 3c, full-area deposition of Silicon nitride 9 (on approx. 100 i Silo2) and structuring (mask 2) 3d, local oxidation 10 of the uncovered silicon areas (field area and diffusion paths): approx. 7000 2 Si02 3e, etching of the well areas (mask 3) with additional nitride layer Etching edge 3f, n + diffusion 3 or n + implantation in the exposed well areas 3g, thermal oxidation 6 of the doped areas: approx. 5000 i SiO2 3h, removal the nitride layer 9 (selective etching) with a thin layer underneath (approx.

100 i) Oxide layer 3i, V-hole etching 1 with the existing oxide edges as an etching mask, continue with steps 1k ... 1o of the first exemplary embodiment.

The most important process steps are shown in Fig. 7, where 7a shows the state after step 3c, FIG. 7b after step 3f, FIG. 7c after shows step 3e and Fig. 7c after step 3m.

A fourth exemplary embodiment is explained with reference to FIG. 8. The #process steps result as follows: Step 4a, 4b as 1st modification 4c, all-over growth of the thick oxide 13 4d, etching of the well areas 14 (mask 2) 4e, full-surface deposition of silicon nitride 9 (approx. 100 i Si O, as a base) and structuring (mask 3) 4f, Over-etching of the pane over the entire surface to remove the thin (approx. 100 i) silicon oxide 4g, n -diffusion 3 or n + -implantation in the exposed well areas 4h, thermal oxidation 6 of the doped areas: approx. 5000 i SiO2 4i, removal of the nitride layer 9 (selective etching) with the one underneath thin (approx. 100 i) oxide layer 4j, V-hole etching 11 with the existing oxide edges as an etching mask, steps 4k ... 4o as in the first exemplary embodiment.

The exemplary embodiments according to FIGS. 7 and 8 use the nitride mask as a replacement for the V-hole Mtske.

All the exemplary embodiments have in common that self-aligned V-MOS transistors be generated. Figure 8 shows an embodiment in which the adjustment errors are factored in, so that the n + diffusion layer 3 is somewhat over the other side of the V-notch protrudes. However, this part of the diffusion layer is complete from the actual diffusion layer 3, which can be seen in the picture to the left of the V-groove is separated so that it does not contribute to the coupling capacitance with the word line can deliver. The consideration of the special tolerances results from this Embodiment by the order of the process steps, but are the diffusion structures of all embodiments are not designed with minimum dimensions, so that in the event of misalignments the electrical function of the cells is guaranteed.

In Figure 9 is the plan view for zudas Ausführungsbeisptel according to Figure 8 shown.

Figure 10 shows a transistor design with a ratio what: 4. Here, w represents the width of the diffusion connection (bit line) and 1 represents the represents the channel length formed by the V-shaped depression. The V-shaped trench is attached to the front next to the diffusion connection, also when used the buried layer 5 as a memory module.

A V-MOS transistor with a large effective channel length 1 is shown in FIG FIG. 11. The diffusion connection 3 is divided into two sections 3a, 3b. The V-shaped trench, shown in plan view, is pulled apart in a rectangular shape. The left connection can be used as a sink connection and the right one as a source connection will.

A space-saving V-M0S double transistor is obtained in that similar to the arrangement according to FIG. 11, the diffusion connection 3 is split into two Diffusion ports A and B, and the two ports as source ports two different transistors are used while the one below is the V-shaped one Covered layer C lying on the trench serves as a common drain connection. The gate connection G; the one above the V-shaped trench perpendicular to the diffusion ports A. and B is formed in the usual way.

12b shows the current flow of such a double transistor. Such transistors can be used as balancing and isolating transistors.

12 figures 10 claims

Claims (10)

Patent claims ÖÄ Highly integrated module in V-MOS technology, d a d u r c h e k e n n n z e i c h n e t that the V-shaped trench using an additional etch-selective layer next to the diffusion region serving as a bit line are arranged and each form at least one transistor with this. 2. Highly integrated module in V-MOS technology according to claim 1, d a d u r c h e k e n n n z e i c h n e t that the etch-selective layer made of silicon nitride consists. 3. A method for producing a module according to one of the preceding Claims that the nitride layer after the thermal oxidation of the diffusion layer applied to the substrate over the entire area is applied and that after a first selective etching for structuring the diffusion layer is used and that the nitride layer after the V-hole etching through a second selective etch is removed. (Figures 3 and 4). 4. A method for producing a building block according to any one of the claims 1 or 2, that is, that the nitride layer (5) covers the entire surface takes place before the application of the diffusion layer (3) on the substrate (8) and that after a first selective etching to structure the diffusion paths serves that after the application of the diffusion paths through a second selective Etching of the nitride layer the V-MOS areas (11) are structured and that after a local thermal oxidation of the uncovered silicon areas the rest Nitride layer is removed by a third selective etch (Fig. 3 and 5). 5. A method for producing a building block according to one of the claims 1 or 29 d a d u r c h g e k e n n n - I do not know that on the epitaxial layer (7) applied over the entire surface silicon nitride (5) and this after a first etching is used to structure the diffusion paths and field areas, that then the well areas are etched and the diffusion layer (3) is applied and after a thermal oxidation of the doped regions by a second selective one Etching the remaining nitride layer (5) is removed (Fig. 6 and 7). 6. A method for producing a module according to one of the claims 1 or 2, that is, after the etching of the tub areas (13) silicon nitride (5) is deposited over the entire surface, which after a first selective Etching is used to structure the diffusion paths and that after a thermal Oxidation of the doping areas by a second selective etching of the rest Nitride layer is removed (Fig.8). 7. A method for producing a module according to one of the preceding Claims, d a d u r c h e k e n n -z e i c h n e t that in the usual way a buried layer is provided (Fig. 3 to 10). 8. A method for producing a module according to one of the preceding Claims that the V-shaped trench is at the front is arranged to the diffusion layer (Fig. 10). 9. A method for producing a module according to one of the claims 1 to -7, -due to the fact that the diffusion layer (3) is separated by the V-shaped recess into two separate layers (3a and Db) and the V-shaped trench is rectangular in plan view (FIG. 11). 10. Process for the production of a building block according to one of the patent claims 1 to 7, d u r c h g e k e n n -z e i c h n e t that the diffusion layer (3) is divided into two sub-layers by the V-shaped trench, each form the source electrode for a transistor, and that the one below the V-shaped The concealed layer (C) in the puncture acts as a common drainage electrode for both Transistors is used (Fig. 12).