DE3019210A1 - VMOS FET switching device - has bipolar power transistors connected in parallel and biassed at working point below saturation - Google Patents

Abstract

The switching device has a vertical metal-oxide-semiconductor (VMOS) FET(47) and a bipolar power transistor(45). The bipolar transistor is connected by its collector to the VMOS FET's drain and by its base to the source. A device (5') delivers a control signal to the gate of the VMOS FET in order to bias the bipolar transistor at its working point within a region up to saturation. Several such switching devices are provided and have the gates of their VMOS FETs connected together. The collector/emitter paths of the bipolar transistors are in parallel to increase the power switched.

Description

Switching device and method for their

Operation and manufacture Switching device as well Method for their operation and manufacture. The invention relates in particular to one integrated switching device according to the preamble of claim 1 or 14, and a method for their operation and production according to the preamble of the patent claim 11 or 25 and in particular a switching device, the bipolar and field effect transistors contains together.

So far, metal oxide semiconductors (MOS or MIS devices) in low power digital circuits and power bipolar transistors, bipolar Darlington circuits and controlled silicon rectifier (hereinafter also referred to as SCR) for High performance applications intended. Bipolar transistors that are close to their rated current and voltage are operated are easily damaged by power surges and have a positive current temperature coefficient, which leads to thermal instability can lead when such devices are connected in parallel, especially since certain Areas of the substrate of the bipolar transistors under severe operating conditions heat, which will damage or destroy the transistor or transistors evokes.

Bipolar power switching transistors in particular have direct current input impedances between 1.0 and 10.0 ohms and DC gain factors of 10 to 50. Darlington circuits in particular have a high saturation voltage on their main current path, leading to leads to a relatively high static power loss. Controlled silicon rectifier are generally used in power circuits) however, they have the disadvantage that they - once switched on via a signal on their control electrode are - cannot be switched off by adding another signal to their control electrode is fed in or the original signal is removed from it. Controlled silicon rectifier are turned off by either the size of the flowing through their main current path Current is reduced essentially to zero or the voltage at its anode and cathode electrodes are reduced to a zero value. Is accordingly in numerous applications where the voltage on the anode and cathode electrodes of a silicon controlled rectifier does not naturally decrease to zero, Complicated circuitry required to control the silicon rectifier turn off.

It is therefore the object of the invention to specify a switching device, the relatively high switching speeds and a relatively low static power loss has, which is also insensitive to thermal instability, a - has good inrush current rating and by feeding in a low-power signal can be switched on or off in their control electrode.

The solution to this problem is in a switching device according to the The preamble of claim 1 or 14 according to the invention by the characterizing part thereof Part included features given.

An advantageous method for operating or producing a Semiconductor switching device is specified in claims 1 and 25, respectively.

Advantageous further developments of the invention result from the patent claims 2 to 10 and 12.

The invention is based on the knowledge that a bipolar transistor Can be controlled by a VMOS transistor for very fast switching at relatively high power levels with low power dissipation, insensitivity against thermal instability when such devices are connected in parallel and a # substantially increased resistance to damage from current inrushes to effect. The inventor realized that by connecting the drain and the Source electrode of a VMOS transistor with the collector or base electrode a bipolar power transistor, a power switching device and a circuit with Operational advantages are obtained that none of the devices alone can offer. The inventor also recognized that - there the manufacturing processes for a bipolar transistor and a VMOS transistor are essentially the same with the exception of the etching of the V-trench and the subsequent gate oxidation of the VMOS transistor - each device can be produced next to each other on a common substrate, to make a new device on a single integrated circuit chip.

The switching device according to the invention is particularly useful in circuits Relatively high power can be used advantageously for voltage and current switching functions to create. Such circuits can be used in converter systems, inverter systems, Chopping, etc. can be used.

The invention is explained in more detail below with reference to the drawing. 1 shows a schematic circuit diagram of a conventional switching device with a bipolar transistor FIG. 2 shows a section of the bipolar transistor of FIG. 1, Fig. 3 Characteristic curves for the switching properties of the bipolar transistor circuit 1, FIG. 4 shows a schematic circuit diagram of a conventional switching device with a VMOS transistor, 5 shows a section of the VMOS transistor of Fig.

4, FIG. 6 characteristic curves relating to the switching properties of the VM0S transistor circuit of Fig.

4, FIG. 7 a schematic circuit diagram of a first exemplary embodiment of the invention, FIG. 8 a section of the switching device according to the invention, FIG. 9 characteristic curves relating to the switching properties of the switching device according to the invention, 10 is a schematic circuit diagram of another embodiment of the invention, and FIGS. 11 and 12 are schematic circuit diagrams each of a further exemplary embodiment the invention.

In Fig. 1, a bipolar power switching transistor 1 is shown, the Collector electrode is connected to an operating voltage terminal 3, the base electrode of which is connected to an input terminal 5 for receiving a control signal, and its emitter electrode having a reference terminal 7 for connection to a Reference potential point is connected. A load resistor 9 lies between a power connection 11 and the operating voltage connection 3. An operating voltage of + E volts is present at the power terminal 11. If it is assumed that the bipolar transistor 1 is on double- diffused epitaxial planar transistor, so is its Section for the doping profile carried out in particular according to FIG. Of the The manufacturing process for making the NPN transistor 1 of FIGS. 1 and 2 is conventional Art. As shown, the bipolar transistor 1 has a collector region 13 on, by N + material (the sign "+" means a relatively high density the relevant majority carrier) is executed, which is part of the original Substrates is. Above the area 13 is an epitaxial layer 15 made of N material (The symbol ~ - ~ means a relatively low density of the relevant majority charge carriers) grown on the substrate to form the collector region of the transistor. The base region 17 and an emitter region 19 are formed by using P and N materials can be diffused into the epitaxial layer 15 as shown. So that wires The various areas that can be connected to each other are made in a metal deposition process a metal such as aluminum is deposited in metallization zones 21 like this is shown. An electrically insulating thin film coating 20, e.g.

Silicon dioxide (SiO2) is deposited between the metallization zones 21 or applied.

According to transistor physics, there are interelectrode capacitances in a bipolar transistor especially between the base and the emitter, and there are the base and the Collector electrode that is charged when the transistor is switched on or off -and need to be unloaded. E.g. the characteristics in Fig. 3 are typical for the Response of the bipolar transistor switching device of FIG. 1 to a control terminal 5 horizontal current pulse control signal 23. E.g. in Fig. 3 this is Input pulse signal 23 is shown, which has a sufficiently high positive current level should have to drive the bipolar transistor 1 into saturation. If the The amplitude of this pulse signal 23 is too high, too high a base current flows into transistor 1, causing damage or destruction of the transistor, assuming that the pulse time is of sufficient duration to cause occurrence to allow such damage. Curves 25, 27 and 29 represent the tension at the collector and emitter electrodes (Vce) 1 the collector current (Ic) and the represents the power absorbed by the transistor (P). On the leading edge of the pulse 23 the transistor 1 begins to switch on - and it closes its switch on in a period of time Tein, as shown. This switch-on time includes Tein an - initial - delay time td in terms of charge # carrier mobility and a rise time tr, which represents the time in which the collector current I of 10% of its final value increases to 90% of its final value. That of the falling flank The rise time tr associated with the voltage Vce is with the charging of the inter-electrode capacitances connected. In particular, the switch-on time is Ton for a power transistor approx. 2 ps. Especially after the occurrence of the trailing or trailing edge of the input pulse 23 turns off the transistor 1 in a period of time Toff. The switch-off time TaUs includes a storage time ts that coincides with the decay (or neutralization) of the linked minority charge carriers stored in the silicon material of the base area is (extinction of charges), and a fall time tft which is represented by time is who the.

Collector current I by 90% of its maximum worth to drop to 10% of its maximum value.

The fall time tf is based on a complicated physical relationship including mobility, doping profiles, area of the device and the load impedance. When driving the transistor 1 in saturation occurs greatest power dissipation during the rise time and the fall time like this is shown by curves 27 and 29. The switch-off time T is usually longer as the switch-on time Tein; however, both also depend on the output load and depends on how the transistor is driven (pulsed). When transistor 1 turns on, its collector-emitter voltage Vc decreases to a certain minimum value at the saturation of the transistor, and its collector current 1 increases to c certain maximum value determined by the size of the supply voltage and the value of the collector load resistance is set. In particular - like this in the Power characteristic curve 29 is shown - during the saturation time tsät of the transistor 1 the power Ps absorbed during this approximately equal to the product of the Voltage Vce at the collector and emitter electrodes, which is approx. 1 volt, and the value of the current I1 flowing through the load 9: (1) P22 Vce 1L In recent Time became a vertical metal-oxide semiconductor (hereinafter referred to as VMOS) - Developed field effect transistor. A VMOS device has a very high static Input impedance and consequently requires an extremely low drive power, what them to a voltage driven High power gain component power.

VMOS devices offer very fast or short switching times, allow a direct parallel connection of devices without complicated bias networks for switching high current levels and have a negative current temperature coefficient (a positive resistance-temperature coefficient), thereby creating an internal negative feedback for the device to produce, which is essentially the destructive, thermal Bipolar transistors are unstable if they are connected in parallel present with each other. VMOS devices are currently available for processing from voltages up to 400 V with a current of approx. 8 A. However, they have current high performance VMOS devices have a relatively # high forward resistance of approx.

1 ohm between their source and drain electrodes.

This resistance causes a relatively high power loss high power levels. For example, assuming that VMOS devices with 100 A become available in the near future, there will be little improvement in the series on-resistance the device consumes approx. 10,000 W at a current of this magnitude. Comparatively bipolar power transistors have a resistance value below 20 mOhm between their collector and emitter electrodes when they are conducting in the saturated state; However, they have the disadvantage of a relatively small value of the input resistance, a relatively low switching speed compared to a VMOS transistor, and they have other problems as discussed above.

The symbol for a VMOS device 31 in Figs. 4, 7 and 10 - 12 was chosen because it was previously used for VMOS devices nothing yet generally recognized symbol has prevailed. In Fig. 4 is the VMOS device 31 is shown schematically for the bipolar transistor of FIG. The VMOS transistor 31 is with its drain electrode D to the operating voltage terminal 3, with its Source electrode S to the reference voltage terminal 7 and to its gate electrode G connected to the input or control connection 5. Has a VMOS device a static DC input impedance at its gate that is about 106 times greater than with a bipolar transistor, one (depending on the circuit components used) in particular 1000 times greater power amplification with no influenceability through thermal instability or secondary breakdown and switch-on and switch-off times Tein or T (depending on other circuit components) of approx. 50 ns. A VMOS transistor is an essentially voltage-carried device while a bipolar transistor is a current-carrying device. In particular, there are fewer than 100 nA of a static drive current for driving a VMOS device required because the DC power gain of such a switch is so high.

Accordingly, VMOS devices can operate in relatively high power ranges operated, but directly controlled by lower control power devices, e.g. from a CMOS logic (CMOS = complementary MOS) or from optical isolators. A VMOS device does not have a minority carrier storage time because it has a Majority charge carrier device is where the charge carriers tend to be -electric Fields than by physical injection and suction of minority charge carriers are controlled in an active area. However cause parasitic Components such as series gate inductors and a parallel capacitance very much short switching delay times, especially of a few ns. As mentioned above bipolar transistors have a positive current temperature coefficient and a negative temperature coefficient of resistance in their main current path, which can lead to positive feedback or thermal instability, if such Transistors are connected in parallel. I.e. when the VMOS chip heats up, it tends to draw or consume less electricity. Accordingly, VMOS devices can can be connected directly in parallel without the need for special bias circuits, in order to have them share in the total load current equally. This parallel operation allows a current to be switched with magnitudes equivalent to the composite ones Nominal values of the VMOS units connected in parallel.

About the voltage breakdown resilience of VMOS switching devices to boost multiple VMOS devices with their source-drain paths in Row are connected, and their gate electrodes are individually biased. this causes a voltage-breakdown characteristic which is approximately equal to the sum of the voltage-breakdown characteristics of the individual VMOS devices.

A section of a typical VMOS structure is shown in FIG. in the The basic cross-sections are compared with the section of the NPN bipolar transistor in FIG. 2 essentially the same except for the region in which a V-groove 33 is etched. The manufacturing process for a VMOS transistor is essentially the same as the manufacturing process for a bipolar transistor, except that a VMOS device processing the special steps of etching the V-trench 33 and a subsequent gate oxidation 35 needed. Diffusion regions 17 'and 19' of a P- and N + material are located each on the side of the V-groove 3 #, as shown. Also can the doping profiles for the different zones of the VMOS transistor from the corresponding ones Zones of the bipolar transistor differ. The metallization 21 (electrodes) is deposited in the manner shown to provide an electrical connection for the Establish gate and source areas. Other areas are with the oxide layer 20 covered as shown.

If a pulse or control signal 37 (see. Fi. 6) at the control terminal 5 or the gate electrode of the VMOS transistor 31, the transistor switches in particular about 0.05 #s after the beginning of the leading edge of the pulse 37 and in about the same time after the onset of the trailing edge of the pulse 37 off. When the # ~ MOS transistor 31 turns on, its drain-source voltage decreases VDS to a certain, very low level of voltage Vx, like this through a signal 39 is shown and the current flowing through the drain-source path IDS increases in size from a very low level 1 (less than 1 pA of an x leakage current) to a certain, much higher level, like this through a curve 41 is indicated. The size of the source-drain current can be controlled are by taking the upper level of the voltage of the gate pulse 37 within a The range from switching off to complete switching on is set. Be it pointed out that the line level of the bipolar transistor 1 can also be controlled by adjusting the size of the base current. If with the greatest Gate voltage is turned into saturation, have the currently available High performance VMOS switch creates an on resistance between the drain and the Source electrode.

from approx. 0.2 to 1.0 ohms. As a result, as shown in a power curve 43, the power consumed or consumed by a VMOS transistor during the on or on state is equal to the square of the load current 1L multiplied by the saturation resistance rs: With a load current of 40 A, the VMOS transistor 31 accordingly consumes between 320 and 1600 W, depending on the value of the saturation resistance rs, when the VMOS transistor is switched on. Herein lies the major disadvantage of the current state of technology for VMOS power devices; namely, their forward resistance is high in comparison with a bipolar transistor. Accordingly, at their current level of development, VMOS devices are not as advantageous as bipolar transistors for high power switching applications.

The inventor has now recognized that the circuit of FIG. 7 is a very fast solid-state switching device for relatively high performance that causes the major disadvantages of the controlled silicon rectifier, the bipolar transistors, the Darlington Circuits and VMOS devices. As shown is in this first embodiment of the invention an NPN bipolar Power switching transistor 45 provided, the voltage connection with its collector electrode to the operating 3 'and is connected with its emitter electrode to the reference terminal 7'. One VMOS device 47 has its drain and source electrodes on the collector electrode 3 'or

the base electrode 6 'of the transistor 45, and its gate electrode is connected to the input or control connection 5 '. A resistor 49 with a The lower resistance value lies between the base and emitter electrodes of the Bipolar transistor 45 to ensure that transistor 45 is turned off is held when a zero bias is applied to the gate electrode 5 ', and around a discharge path for in the base during the conduction period of the transistor 45 generate stored charge. A preferred value for this resistance is 1 ohm. The resistor 49 can be inside or outside of this novel Combination or summary of the components 45, 47 may be included that are suitable as CSD (Combination Semiconductor Device) is designated by the inventor. The present switching device 45, 47 has the high performance switching advantages of a silicon controlled rectifier and the additional advantage of switching off by applying a suitable signal to the gate of VMOS transistor 47.

A section of this switching device 45, 47 is shown in FIG. Since, as shown and discussed above, VMOS devices and bipolar transistors are manufactured using essentially the same processes, the bipolar transistor 45 and the VMOS device 47 can be fabricated on the same substrate. As Is shown, - s-ind these devices 45, 47 arranged side by side, wherein an isolation trench 51 therebetween in at least a substantial portion of the epitaxial layer 15 is etched. Silicon dioxide layers 20 are above this insulation trench 51 and other zones of the device 45, -47 as shown. The oxide layer of the isolation trench 51 is then used with the metallization 21 electrically connecting the base region 17 of the NPN power transistor 45 with the souce area 17 ', 19' of the VMOS transistor 47 is superimposed. Other metallization zones 21 (electrodes) are superimposed as shown to form the drain and the Collector area electrically with the operating voltage connection 3 ', the emitter area to connect to terminal 7 '- and gate to terminal 5'. Dashed lines 53, 55 and 57 correspond to a deeper etching of the isolation trench 51 to even one greater electrical isolation between the VMOS transistor 47 and the bipolar transistor 45 if required for certain applications. It. be on it pointed out that several such devices 45, 47 on the same substrate can be deposited.

Assuming that the plurality of such devices 45, 47 are the same in their electrical properties and exist in a number N, where N is any integer greater than 1, then - if the devices are directly connected in parallel - the - current carrying capacity of the parallel connected Devices approximately equal to N times the current carrying capacity of a single one of them Devices.

Alternatively, if a plurality N of these devices 45, 47 in series with regard to their main current paths (collector-emitter electrode current path of the bipolar transistor 45) and the gate electrodes of each of the VMOS transistors 47, respectively by a sufficient voltage level to switch on the associated V; MOS transistor 47 are activated, the voltage breakdown capacity of this series-connected Devices 45, 47 approximately N times the voltage breakdown load capacity of a each of these devices 45,47. This means that there is a single one in the series connection floating bias on the gate electrodes of the VMOS transistors 47, each Bias to a voltage on the emitter electrode of the associated bipolar transistor 45 is related. If during the operation of the device 45, 47 a pulse control signal 57 (see Fig.

9) at the control terminal 5 or the gate electrode of the VMOS transistor 47, assuming that the level of the voltage of the pulse 59 is sufficient is high to fully saturate the VMOS device 47, so turns on the VMOS transistor 47 to establish a current conduction path (its drain-source electrode current path) of about 1 ohm between the collector and base electrodes of the bipolar transistor 45 to generate. Because the VMOS transistor 47 is much faster than the bipolar transistor 45 turns on, at that time almost all of the load current IL is into the base electrode of the bipolar transistor 45 controlled, whereby the bipolar transistor 45 is overdriven which greatly accelerates its transition to the state of high conduction. This Overdrive condition only occurs for a short period of time for which - how this is shown in Fig. 9 - the voltage on the collector and the Emitter electrode of the transistor 45 drops rapidly when it is switched on (see. The signal 61), whereby the base current fed in via the VMOS transistor 47 is rapidly reduced, which removes the overdrive condition. The VMOS device 47 provides negative feedback between the collector and base electrodes of the bipolar transistor 45 and represents corresponding to the level of the voltage between the collector and base electrodes of the bipolar transistor in order to keep the latter in a conduction state. As a result the feedback conducts the bipolar transistor close to the saturation edge, it goes however actually not over into saturation (usually a bipolar transistor saturated when the collector-base and emitter-base PN junctions are both in Forward biased are #. After the occurrence of this condition it increases an increase in its base drive current does not significantly affect the collector current of the Bipolar transistor).

In this way, as a result of the very short period of time, the Feedback caused overdrive of the bipolar transistor 45 in approx.

0.5 ps switched on. Therefore, the device according to the invention is inclusive of the bipolar transistor 45 and the VMOS device 47 have a turn-on time that is at least 4 times shorter than the time it takes to achieve that with conventional bipolar switching devices which are operated in a circuit according to FIG. It should be noted that when the transistor 45 is switched on, its collector current 1 (cf. the signal 63) -c rapidly from a relatively low value (leakage or leakage current) to one substantially high value with the device 45, 47 operating in equilibrium increases. The voltage level of the Control pulse 59 can be different Values for controlling the conduction level of the bipolar transistor 45 in a range can be set between switch-off and saturation level for certain applications. In typical switching applications, the level of pulse 59 is made high enough so that the bipolar transistor 45 operates at the saturation edge. If any Short-term or switch-on demand occurs, which suddenly increases the load current IL leaves, whereby the bipolar transistor 45 is further pulled out of saturation, what suddenly increases the voltage at its collector-emitter electrodes, so the transistor 47 responds as a result of the negative feedback, in that more base current in the base electrode of transistor 45 is driven so that the bipolar transistor 45 leads more difficult and consequently goes back to the saturation edge. The increased line lets the voltage at the collector-emitter electrodes decrease. In this way the negative feedback effect generated by the VMOS device 47 improves the momentary or turn-on capability of the bipolar transistor 45 by at least a factor of 4 of its normally rated inrush current carrying capacity. Accordingly, can the switching device 45, 47 according to the invention for controlling inductive loads, such as.

the windings of an electric motor. As a result of the positive temperature coefficient of resistance between its drain and source electrodes Furthermore, the VMOS transistor 47 automatically prevents the bipolar transistor 45 ever becomes thermally unstable when such devices 45, 47 together are connected in parallel.

It is only assumed that the load current is approx.

44 A, and that the direct current gain factor B of the bipolar transistor 45 has approximately the value 10; then, when the device 45, 47 is in equilibrium, a current of approximately 4 A flows through the VMOS transistor: 47 (its "on" resistance r 5 is approximately 1 ohm) into the base electrode of the bipolar transistor 45, causing the latter to generate a current 1 conducts about 40 A through its collector-emitter current path, with a voltage V ce of about 5 V and a voltage Vbe of about 1.0 V between its base and emitter electrodes and a load current IL of 44 A being present. Under the stated equilibrium conditions and assuming that the bipolar transistor 45 is working at the saturation edge, the power P c consumed by the device (cf. FIG. 9) is about 218 W, which can be derived from the following equation: This compares to switching the same level of a load current (44 A) to a power level of consumption of 1,936 W (see. Fig. 6) in the circuit of FIG. 4 with only one VMOS device 31 and with 44 W (see 3) in the circuit of FIG. 1 with only one bipolar transistor 1. However, since the bipolar transistor 45 can only work up to the saturation edge, the charge storage time t of the combined semiconductor device 45, 47 of FIG essentially equal to zero, while -when the bipolar transistor 1 is driven in saturation -this has a storage time of a few.

Depending on the trailing edge of the control pulse 59, the VMOS transistor switches 47 in particular in 0.05 ps and the bipolar tra: .s # stor about 0.45 later the end. Accordingly, the turn-off time for the integrated semiconductor device is 45, 47 approx. 0.5 µs. This is compared with a switch-off time from saturation, which for the transistor 4S alone has a high value of 3.7 us.

Laboratory tests have confirmed the above explanations; the circuit de # r Fig. 7 was constructed using a VN23IA-VMOS transistor (manufactured by from Siliconix Incorporated, Santa Clara, - # California, #USA) # for the transistor 47, a 20 ohm resistor for the load 9, a 2 ohm resistor for the resistor 49 and-an MJE13009 bipolar transistor (manufactured by Motorola Semiconductor Products Inc., Phoenix, Arizona, 85036) for transistor 45. The manufacturer's information for - the # - # VN23IA- # VM0S-Tra # eisto # r are the following VDSmax (highest drain-source-spantung) = 200 V IDSmax. (larger drain-source current) = 8 A Ton (switch-on time with a pulse of +5 V at the gate) = 0.05 µs T off (switch-off time) rds (resistance value between drain and Source electrode, if switched on) = 0.3 Ohm The manufacturer's specifications for the MJE13009 bipolar transistor are: VcEmax (highest collector-emitter voltage) = 400 V ICM (largest collector current in pulsed operating mode) = 24 A Ic (largest permitted continuous collector current) = 12 A (direct current) Tein (switch-on time for resistance switching of 125 V at Ic = 5 A) = - 0.41 ts (switch-off time from operation with resistance load, 125 V operating voltage at 1 = 5A) = 1.65 ps c When + E has the value 100 V and a pulse with an amplitude of +5 V. is connected to the gate electrode G of the VMOS transistor 47, the bipolar transistor 45 switched on in 0.1 ps. When the pulse is removed from +5 V, the voltage is gradually reduced to zero at the gate, the bipolar transistor switches 45 in 0.4 ps.

The switch-on behavior for the same MJE13009 bipolar transistor, used above was examined in the circuit of FIG. 7, the the same components as shown above were used, with the exception that the 20 ohm resistor is loaded by three 100 watt incandescent lamps connected in parallel replaced and the operating voltage was changed from 100 V to 150 V. The cold resistance for each light bulb is about 3 ohms; therefore, the incandescent lamp load 9 constitutes a load from approx.

1.0 ohms when the lamps are cold. When starting to turn on the Bipolar transistor 45 (by applying a voltage pulse to the gate of the VMOS transistor 47, see above), an inrush current with a size of approx. 100 A measured without failure of the bipolar transistor 45. This switch-on attempt was repeated several times with the same result. Accordingly, in the The circuit of FIG. 7 shows the short-term or switch-on load capacity of the MJE13009 bipolar transistor 45 at least 4 times its parameter of 24 A.

In summary, the device 45, 47 according to the invention has a switching speed several times faster (at least 4 times faster) than a bipolar power transistor is; it also has an on-power capability that is about 4 times greater than is in a bipolar transistor; it is also insensitive to a thermal one Instability when connected in parallel with other such devices 45, 47 is; and it eventually has a power dissipation at full conduction that is about 8 times is less than the power dissipation of a power VMOS device that has a conducts equal current. The device 45, 47 also provides one in excess of 1012 ohms DC input impedance and a DC gain factor exceeding 106.

In Fig. 10, there is a bias source 67 in the power switching device 45, 47 are provided to ensure that the device 45, 47 is directly from logic gates very low power can be switched on quickly. The bias source 67 requires only few complex components, since the VMOS transistor 47 only a very low control power is required. The bias source 67 contains two resistors 69, 71, a Zener or Zener diode 73 and a capacitor 75 for filtering. Whenever in this circuit the output signal from one with the control terminal 5 connected logic element to a "high" or positive logic level passes, the bias voltage source 67 responds by essentially the drive current from -approx. 100 nA fed into the gate of VMOS transistor 47 but resistor 71 is to turn on the combined device 45, 47.

In-Fig. 11, another embodiment of the invention has one Plurality of N (N = integer: 2,3 ....) switches 77 (devices 45, 47), whose individual input or control connections 5 with the output of an inverter buffer control element 78 are interconnected. These # N switches 77 can be on a common substrate be provided. A diode 79 is anti-parallel to the bipolar transistor 45 each Switch 77. This diode 79 allows the switches 77 to be switched on both sides, if. complex impedances, such as # e.g. inductive loads, are controlled. The diodes 79 switches 77 can be integrated with the N switches 77 on the same substrate be. An optocoupler 81 provides electrical isolation between an input signal source, which lies between input connections 83 and 85 of the optocoupler 81. To this Signal ground and power switchgear ground are isolated from each other, which essentially precludes power inrushes from being a faulty Cause the switching device to trip. A floating or floating bias source 87 lies between a power connection ### 89 and a local ground (LG) connection 91 for the # power switching side of the circuit. The bias source 87 includes one Resistor 93, a Zener diode 95 and a filter capacitor 97. The bias source 87 provides power for the optocoupler 81st and the buffer driver 78, such as this is shown. A pull-up resistor 79 is located between terminal 89 and the output of the control element 78. As explained above, the switches 77 be connected directly in parallel to currents with sizes approximately equal to N times Current switching nominal value of a single switch 77 to switch. They can also Switch 77 be connected in series with their main current paths to the Voltage breakdown with respect to a single switch 77 to be increased by a factor of approximately N. if however, the switches 77 connected in series are the gates of the respective VMOS transistors 47 preferably not interconnected, but each gate is through a single one floating or floating source 87 and the optocoupler circuit 81, 78 controlled, the local masses (LG) referring to the voltage at terminal 7 'of their respective Switch 77 are related. For purposes of illustration, it will be assumed that each of the switches 77 is the same in electrical properties; in practice this is not necessary applicable. For a given switch 77, the current rating of the VMOS device 47 can be generated by connecting multiple VMOS devices in parallel, to the function of the VMOS device 47 with a current carrying capacity essentially equal to some of the current ratings of the multiple VMOS devices. on similar way several NPN bipolar transistors can be connected in parallel, essentially about the function of a bipolar transistor 45 with a nominal current value equal to the sum of the nominal current values of the individual bipolar transistors.

As explained above, the switching device according to the invention comprises the combination of a VMOS device 47 connected with its main current path between the collector and emitter electrode of a bipolar transistor 45 is located. A resistance 49 with a small resistance value lies between the base and emitter electrodes of the Bipolar transistor 45 to provide a discharge path for those in the base of the transistor 45 stored charge, and around this Transistor during Keep zero bias conditions off. This device 45, 47 can be fully integrated on a single substrate. By having a positive feedback generated between the collector and emitter electrodes of the bipolar transistor 45 the VMOS transistor 47 increases the turn-on efficiency of the bipolar transistor 45 by a factor of 4 to 10. The turn-on capacity of the bipolar transistor 45 is increased because - whenever a short-term or switch-on voltage is an increase the voltage between its collector and emitter electrode (V e) causes what the conduction of transistor 45 moves further away from saturation - the VMOS transistor 47 acts to move more current from the collector to the base electrode of transistor 45 feed back, forcing the latter to be harder to conduct and back to saturation to go, reducing the collector-emitter voltage V and therefore a ce excessive Power consumption is reduced as a result of the short-term condition. After initial Turning on the device 45, 47 allows that available from the VMOS transistor 47 high base current initially overdriving the bipolar transistor 45, while continuing a bipolar conduction transistor 45 with a lower B or DC gain factor can be used; the lower B-factor transistor 45 increases the switching speed of the device 45, 47. In addition, the combined device 45, 47, when connected in parallel with other similar devices, not thermally become unstable; it has a faster switching speed than a power bipolar transistor alone and uses significantly less power than a power VMOS transistor alone. The inventive switch 45, 47 on one single substrate and it can carry a current of at least 5A switch at voltage levels that exceed 50 V. As a result of the high loss it is currently while the currently available VMOS transistors are conducting however not expedient to use the present switch 45, 47 at power levels that exceed 2 kW (advances in VMOS technology are sure to increase the Useful power level of VMOS transistors).

As indicated, VMOS devices have a lot faster switching speeds than bipolar transistors. In certain applications This switching speed difference can cause switch-on problems when switching on the 7 cause circuit. For example, when a control signal of positive polarity and sufficient amplitude at the gate or control terminal 5 ', the switches VMOS transistor 47 turns on rapidly and essentially performs for a short period of time all load current through its drain-source current path until the bipolar transistor 45 begins to turn on and the voltage level between its collector and base electrodes belittles. When the initial inrush current is of sufficient magnitude and duration is, excessive power consumption may occur in the VMOS transistor 47, whereby the device will be damaged as it is a base current to the bipolar transistor 45 feeds.

The large current surge can also damage the bipolar transistor 45. One method of limiting the magnitude of this inrush current is conventional in the use of attenuators that also work during the duty cycle. One possibility is to arrange a reactive impedance in series with the current path of the device to be protected.

In Fig. 12 shows another schematic embodiment of the Invention a switching device that does not require a damping circuit to the to avoid the short-term or transient power-up problems described above. A second VMOS device 101 is attached to the green switching device 45, 47, as shown. The transistor 101 may - although as a VMOS transistor shown - also be a # low power bipolar transistor as a faster one Low power and low voltage switching transistor perform the function of the transistor 101 supplies, as will be explained in more detail below. That extra transistor 101 can be inserted discreetly or on the same integrated circuit chip 103 ~ with the device 45, 47 and the resistor 49 may be included. The entire circuit of Fig.

12 can also be constructed from only discrete components. A bias source 105 with three resistors 107, 109, 111, a diode 113, a Zener diode # 115, an operating voltage connection 117 for receiving an operating voltage + E, a reference terminal 119 for connection to a reference potential point and a Filter capacitor 121 provides bias voltages to the gate and drain electrodes of the VMOS transistors 47 and 101, respectively. An integrator 123 with a resistor 125 and a capacitor 127 is between an input or control terminal 129 and a reference terminal 131. A differentiator having a capacitor 135 and a Resistor 137 lies between control terminal 129 and reference terminal 131.

During operation of the circuit of FIG. 12, control terminal 129 is applied a control signal taking a positive value or a voltage level signal. The differentiator 133 responds to this signal, by (within a substantially short time) at the connection point of the capacitor 135 and the resistor 137 generates a pulse that assumes a positive voltage, which is supplied to the gate of the VMOS transistor 101. Depending on this positive Impulse switches on the VMOS transistor 101 with a brief overdrive, wherein the impedance between its drain-source electrodes is decreased to a current through its drain-source current path from resistor 111 of the bias source 105 to conduct the base electrode of the NPN transistor 45. The transistor 45 speaks on this base current by turning it on and adjusting the impedance between its Collector-emitter electrodes begin to decrease, reducing the voltage across its Collector electrode is lowered. The data of the components of the differentiating element 133 and the integrator 123 are chosen so that - just after the transistor 45 is essentially on - the integrator 123 is sized on the capacitor 127 to develop a voltage of sufficient positive amplitude that the VMOS transistor 47 can complete the turning on of transistor 45, and thus this is held in a high conduction state. As a result of the earlier start of turning on the transistor 45 via the VMOS transistor 101 and the differentiating element 133 accordingly switches the VMOS transistor 47 with a substantially reduced turn-on loss as explained above. Just after turning on the VMOS transistor 47 the capacitor 135 of the differentiating element 133 is essentially charged, whereby the voltage at the gate electrode of the VMOS transistor 101 is the reference potential approaches at terminal 131 via resistor 137, this transistor 101 being switched off will. As long as the one at the control terminal 129 Control signal remains "high" or at a sufficiently positive level, the VMOS transistor remains 47 then switched on to feed a base current into the bipolar transistor 45, whereby the latter is kept conductive up to the saturation edge, as above was explained. When the control signal is removed or its level substantially is reduced to the level of the reference potential, the VMOS transistor 47 becomes quickly switched off via the diode 124, which then the transistor 45 from its switches off the non-saturated conductive state. Since the VMOS transistor 47 a lot faster than the bipolar transistor 45 turns off ~ the bipolar device acts as a turn-off attenuator for the VMOS transistor 47. The circuit of Fig. 12 enables very high frequency switching in a range exceeding 100 kHz. Using current power transistors for transistor 45, this circuit can switch up to 600 V at power levels exceeding 60 kW. The differentiator 133 and the integrator 123 can be omitted by adding individual control signals from a controller (not shown) to the gates of VMOS transistors 101 and 47, the amplitudes, phase relationships and time durations of these Control signals for operation of the transistors 101 and 47 are predetermined as this has been explained above.

Claims (1)

Switching device with a first vertical metal-oxide-semiconductor (VMOS) Field effect transistor with a gate electrode receiving a first control signal, a drain electrode and a source electrode, characterized by a first Bipolar power transistor (45) with a collector electrode connected to the drain electrode (D) of the VMOS transistor (47) is connected and a first operating voltage (+ V) picks up, one connected to the source electrode (S) of the VMOS transistor (47) Base electrode and an emitter electrode. 2. Switching device according to claim 1, characterized by a device (5 '), which receives the first control signal and with the properties of the VMOS transistor (47) is provided to the bipolar transistor (45) on an operating point within to bias an area up to the saturation edge (Fig. 7). 3. Switching device according to claim 1 or 2, characterized in that that a plurality of N of these switching devices (77) are provided, where N is an integer greater than 1 that the gate electrodes (G) of the VMOS transistors (47) of the N-switching devices (77) are connected together, and that the collector-emitter current paths of the bipolar transistors (45) are connected in parallel to one with respect to a single one Switching device to achieve about N times greater current switching load capacity (Fig. 11) 4. Switching # device according to claim 1 or 2 ,. characterized in that a plurality of N-switching devices (77) is provided, where N is an integer greater than 1, that the gate electrodes (G) the VMOS transistors (47) of the N switching devices (77) each have individual control signals received, and that the collector-emitter current paths of the bipolar transistors (45) are connected in series to with respect to a single switching device an approximately To achieve N times greater voltage breakdown load capacity. 5. Switching device according to claim 1 or 2, g e k e n n z e i c h n e t d u r c h a relatively small resistance (49) between the base and the emitter electrode of the bipolar transistor (45), whereby the resistor (49) at switched off VMOS transistor (47) a discharge path of lower impedance for between charge accumulated on the base and emitter electrodes, thereby reducing the turn-off time of the bipolar transistor (45) to reduce (Fig. 7). 6. Switching device according to claim 1 or 2, characterized by means (67) including a bias source of a relatively low one Power with one connected to the gate electrode (G) of the V! OS transistor (47) Output terminal for applying an output voltage to the gate electrode (G) when always the first control signal goes to a high logic level, and to Removing the output voltage whenever the first control signal to a lower one logic level passes (Fig. 10). 7. Switching device according to claim 6, characterized in that the bias source (67) comprises: a power terminal and a reference terminal, two resistors (69, 71) connected in series between the power connection and an output terminal, and a Zener diode (73) between the common connection of the two resistors (69, 71) - and the reference connection, the Zener diode (73) is polarized in one direction to a predetermined bias at the output terminal to generate (Fig. 10). 8. Switching device according to claim 1 or 2, characterized in that that also a switching transistor device (101) is provided, the one second control signal receiving control electrode and a main current path between a voltage source of a second operating voltage and the base electrode of the first bipolar transistor (45) has that the second control signal of the control electrode the switching transistor device (101) before the first control signal is fed in into the gate electrode of the first VMOS transistor (47) fed is that the switching transistor device (101) responds to the second control signal, to substantially reduce the impedance of their main current path, so that a Current flow through there into the base electrode of the first bipolar transistor (45) is allowed and this begins to switch on, that the first biplar transistor (45) the voltage on its collector decreases when it starts to turn on and the Impedance between its collector and emitter electrode lowers that essentially immediately thereafter the first control signal at the gate electrode of the first V ^ IOS transistor (47) lies to turn this on, thereby turning on the first bipolar transistor (45) is completed, and that after this time the control signal is removed, so that the switching transistor device (101) switches off, whereby a brief Appearance of turning on the first VMOS transistor (47) at a time essentially is reduced when the first bipolar transistor (45) partially conducts. 9. Switching device according to claim 8, characterized in that ~ the switching transistor device comprises a second vertical metal-oxide-semiconductor field effect transistor (101) with a drain electrode (D) receiving the second operating voltage, one on the base electrode of the first bipolar power transistor (45) connected Source electrode (S) and a gate electrode receiving the second control signal (G). 10. Switching device according to claim 8 or 9, characterized by a differentiator (133) responsive to an input signal for the second control signal and an integrator (123) responsive to the input signal, around the first control signal a relatively short period of time after the start of the second Control signal, but during the time of its occurrence to generate, wherein the duration of the first control signal essentially at the conclusion of the input signal ends (Fig. 12). Method for operating a power switching device, in particular of a fast bipolar power transistor with base, collector and emitter electrodes over a range of conduction states up to, but not including, saturation and to improve the switch-on behavior (short-term load capacity) of the transistor by at least a factor of five, g e k e n n z e i-c h n e t d u r c h, - retained a sufficient level of voltage of suitable polarity between the Collector and base electrodes of transistor (45) to prevent saturation, and generating feedback between the collector and base electrodes, the acts such that with further removal of the transistor (45) from saturation due to a brief electrical state, a larger base current in the Transistor (45) is fed, and that with the approaching the saturation edge Transistor (45) the base current is reduced to essentially its operating point not in saturation at a predetermined equilibrium level. 1L method according to claim 11, characterized in that the generation the feedback comprises: connecting the drain and source electrodes of a VMOS field effect transistor (47) with the collector resp. the base electrode of the bipolar transistor (45), and operating the VMOS transistor (47) to provide direct feedback to maintain the equilibrium level not to produce in saturation. 13. Use of the switching device according to one of claims 1 to 10 in converter systems, inverter systems, choppers and the like. 14. Inteqrierte semiconductor switching device, labes special according to claim 1, with a substrate of a first conductivity type, a first layer of a second Conduction type superimposed on one surface of the substrate, a second layer of one third conduction type extending into a region of the first layer, one third layer of the first conductivity type extending into the second layer, and a first V-groove extending through the central portions of the second and third Layer extends into at least the first layer, characterized by a fourth Layer (17) of the third conductivity type, located in a different area of the first Layer (15) extends - a fifth layer (19) of the first conductivity type, the extends in the fourth layer (17), - a sixth layer (20) made of electrical insulating material, which the first to fifth layers (15, 17 ', 19', 17, 19) and superimposed on the first V-groove (33), a first electrode (5 '), overlying the sixth layer (20) over the first V-groove (33), a second electrode (3 '), which overlays the other surface of the substrate (13) and is electrical. contacted, a third electrode (7 ') extending through the sixth layer (20) to to electrically contact the fifth layer (19), and a fourth electrode (21), which overlays and extends through the sixth layer (20) over the second, third and fourth layers (17 ', 19', 17) to electrically connect these last three layers connect to. 15. Switching device according to claim 141, characterized in that the switching device responds to a bias voltage on the first electrode (5 '), a low impedance channel for conducting a current from the second electrode (3 ') through the substrate (13), the first, the second and the third layer (15, 17 ', 19') into the fourth electrode (21), from there into the fourth and fifth layers (17, 19) to build up the third electrode (7 '), creating a low impedance path for conducting a current between the substrate (13) and the first, fourth and fifth layer (15, 17, 19) is generated, and that the switching device on one Zero preload. at the first electrode (5 ') responds to substantially the impedance of the canal and a current flow between the substrate (13) and the first to fifth layers (15, 17 ', 19', 17, 19) to prevent such a particularly integrated, very fast semiconductor power switching device to form 16. Switching device according to claim 14 or 15, characterized by a second V-groove (51) extending into at least the first layer (15) and lies between the second and fourth layers (17 ', 17), the sixth Layer (20) of electrically insulated material also superimposes the second V-groove (51), and wherein the fourth electrode (21) is the sixth layer (20) over the second V-groove (51) superimposed. 17. Switching device according to claim 14 or 15, characterized in that - That the first layer (15) consists of an epitaxial layer. 18. Integrated, very high-speed, high-performance semiconductor switching device, in particular according to claim 1, with a semiconductor substrate of a first conductivity type with two surfaces, and a first semiconductor region of the first conductivity type, the superimposed on one of the surfaces, g e k e n: ~ n z e i c h n e t d u r c h -a second and third non-contiguous semiconductor regions (17 ', 17) of one second, opposite to the first type of conduction, the first area (15) overlay a fourth semiconductor region (19 ') of the first conductivity type, which overlays the second area (17 '), the second area (17') the fourth Area (19 ') separates from the first area (15), a first V-groove (33) which overlies and extends through central parts of the second and fourth areas (17 ', 19 ') in at least the first area (15), -a fifth semiconductor area (19) of the first conductivity type overlying the third region (17), the third Area (17) separates the fifth area (19) from the first area (15), a sixth Area (20) made of electrically insulating material, which the first to fifth area (15, 17 ', 17, 19', 19) and the first V-groove (33) superimposed - a first electrode (5 '), which overlays the sixth region (20) over the first V-groove (33), -a second electrode (3 ') which electrically contacts the other surface of the substrate (13), - a third electrode (7 ') extending through the sixth region (20) and electrically contacted the fifth region (19), and a fourth Electrode (21) which electrically the second, the third and the fourth area (17 ', 17, 19') and extends through the sixth region (20) to electrically contacting the second, third and fourth regions (17 ', 17, 19'), and which superimposes the sixth area (20) to electrically the second, the third and to connect the fourth region (17 ', 17, 19'), wherein the substrate (13), the first, third and fifth area (15, 17, 19; or a collector-emitter current path) first means to have a current of at least 5 amps at 50 volts exceeding Conducting voltage levels through the second and third electrodes (3 ', 7'), -wherein das.Substrat (13), the first, the second and the fourth area (15, 17 ', 19') have: A second device to selectively supply a current from the second electrode (3 ') through the substrate (13), the first, the second and the fourth area (15, 17 ', 19 ') into the fourth electrode (21) depending on one relative to the fourth electrode (21) to conduct the first optionally variable voltage to the first electrode (5 '), and means for allowing current to flow between the second and fourth electrodes (3 ', 21) depending on a second voltage with respect to the fourth electrode (21), on the first electrode (5) to prevent -wherein the substrate (13), the first, the third and the fifth area (15, 17, 19) a third device comprise to selectively a current from the second electrode (3 ') through the substrate (13), the first, the third and the fifth area (15, 17, 19) in the third Conducting electrode (7 ') depending on the variable current that is passed by the fourth Electrode (21) through the third and fifth areas (17, 19) to the third electrode (7 ') flows in order to continue a current flow from the second to the third electrode (3 ', 7') to prevent if a current does not flow from the fourth electrode (21) the third and fifth regions (17, 19) flow into the third electrode (7 '), wherein the substrate (13), the first, the third and the fifth area (15, 17, 19) and the third device form a bipolar transistor, and the second device fourth means for preventing the bipolar transistor from saturating. 19. Semiconductor switching device, in particular according to claim 1, with a semiconductor substrate of a first conductivity type with two surfaces, - a first Layer of a second conduction type, which superimposes a surface of the substrate, a gate V-trench that extends at least into the first layer, -a first electrically insulating thin film covering the surfaces of the gate V-trench coated, -a first and a second diffusion region of a third conductivity type, which extend into the first layer, on opposite sides of the V-groove lie and are in contact with this, and a third and a fourth diffusion area of the first conductivity type, which are completely within the first or second diffusion region and extend into them, the third and fourth diffusion regions are each in contact with # the V-groove, characterized by a fifth diffusion region (17) of the third conductivity type extending in # the first layer (15) - one sixth diffusion region (19) of the first conductivity type, that of the fifth diffusion region (17) is surrounded and extends in this, - an isolation V-groove (51), which is at least in the first layer (15) between the second and the # fifth Diffusion region (17 ', 17) extends - a second electrically insulating thin film (20), which coats the surfaces of the isolation V-groove (51), - a first electrically conductive device (21), the the second electric insulating thin film (20) and parts of the second, fourth and fifth diffusion regions (17 ', 19', 17) covers these diffusion areas (17 ', 19', 17) electrically to connect a second electrically conductive device (21), which the other surface superimposed on the substrate (13), a third electrically conductive device (21), superimposing the first insulating thin film over the gate V-trench (51), a fourth electrically conductive device (21), which is part of the sixth diffusion region (19) superimposed, and a third electrically insulating thin film, the exposed one Overlapping areas around the electrically conductive device, thereby dependent by a bias voltage applied to the third electrically conductive device (21) a low impedance path through the substrate (13), the first layer (15) and the first to fourth diffusion region (17 ', 19') arises, so that flow from the second to the first electrically conductive device (21) and from there into the fifth diffusion region (17) can flow, which in turn reduces the impedance between the substrate (13), the first layer (15) and the fifth and sixth diffusion region (17, 19) quickly from a relatively high to a relatively low Value drops, so that current can flow through there, and - whereby depending on one of the third electrically conductive device (21) lying zero bias a relative high impedance between the substrate (13), the first layer (15) and the first to fourth diffusion area (17 ', 19') is created, which causes a current to flow from there in the fifth area (17) prevented, so that a relatively high impedance between the substrate (13), the first layer (15) and the fifth and sixth regions (17, 19) is built. 20. Semiconductor switching device according to claim 19, characterized in that - that the first layer (15) is an epitaxial layer. 21. Integrated, very fast high-performance semiconductor switching device, in particular according to claim 1, with a semiconductor substrate of a first conductivity type with two faces and a relatively high majority carrier density, and - one first semiconductor region of a first conductivity type overlying one of the surfaces and has a relatively low majority carrier density by a second and a third non-contiguous semiconductor area (17 ', 17) of a second conduction type opposite to the first, the first Overlay area (15), the second and third areas # 7 '#. - one have relatively low majority carrier density, a fourth semiconductor region (19 ') of the first conduction type, which overlays the second region (17'), the second area (178) separates the fourth area (19 ') from the first area (15) and has a relatively high majority carrier density, a first V-groove (33), the central parts of the second and fourth areas (17 ', 19') in at least covers the first area (15) and extends through it, a fifth Semiconductor region (19) of the first conductivity type which overlays the third region (17), wherein the third area (17) separates the fifth area (19) from the first area (15) and the fifth region (19) has a relatively high majority carrier density, a sixth region (20) of an electrically insulating material comprising the first to the fifth area (15, 17 ', 17, 19', 19) and the first V-groove (33) superimposed, a first electrode (15 ') forming the sixth region (20) over the first V-groove (33) superimposed on a second electrode (3 ') which electrically connects the other face of the Substrates (13) contacted, a third electrode (7 '), which extends through the sixth Area extends and electrically contacts the fifth area, and one fourth electrode (21; or source and base electrode) ~ which electrically connect the second, the third and fourth areas (17 ', 17, 19') connects and through the sixth region (20) extends to electrically the second, the third and the fourth area (17 ', 17, 19') to contact, and the sixth area (20) superimposed to electrically connect the second, third and fourth areas (17 ', 17, 19 ') # to connect, the substrate (13), the first, the third and the fifth Area (15, 17, 19) have a first device to a flow of at least 5 A at voltage levels exceeding 50 V through the second and third electrodes (3 ', 7'), the substrate (13) being the first, the second and the fourth Area (15, 17 ', 19') have: A second device for optional routing a current from the second electrode (3 ') through the substrate (13) ,. the first, the second and fourth areas (15, 17 ', -19') in the fourth electrode (21) depending on a first, optionally variable with respect to the fourth electrode (21) Voltage at the first electrode (15 ') and means for preventing a Current flow between the second and the fourth electrode (13 ', 21) depending on a second voltage applied to the first electrode (5 ') with respect to the fourth Electrode, wherein the substrate (13), the first, the third and the fifth area (15, 17, 19) a third device for optionally directing one Current from the second electrode (3 ') through the substrate (13), the first, the third and fifth areas (15, 17, 19) in the third electrode (7 ') dependent of a variable current flowing from the fourth electrode (21) the third and fifth areas (17, 19) flow into the third electrode (7 '), to prevent a current flow from the second to the third electrode (3 ', 7'), when a current does not flow from the fourth electrode (21) through the third and fifth Area (17, 19) flows into the third electrode (7 '), the substrate, the first, the third and fifth areas (15, 17, 19) and the third device one Form bipolar transistor, and wherein the second device is a fourth device has to prevent the bipolar transistor from saturation. 22. Integrated, very fast semiconductor power switching device, in particular according to claim 1, having a substrate of an N + conductivity type, a first Layer of an N conductivity type overlying a surface of the substrate, a second layer of a P -line type, which is located in an area of the first layer extends, a third layer of an N -type, which is extends into the second layer, and a first V-groove extending through central parts extending the second and third layers into at least the first layer by a fourth layer (17) of one P -line type, which is located in another Area of the first layer (15), a fifth layer (19) of an N -conductivity type, extending into the fourth layer (17), a sixth layer (20) of an electrical insulating material covering the first to fifth layers (15, 17 ', 19', 17, 19) and superimposed on the first V-groove (33), a first electrode (5 '), the sixth Layer (20) superimposed over the first V-groove (33), a second electrode (3 '), which overlays the other surface of the substrate (13) and makes electrical contact, a third electrode (7 ') extending through the sixth layer (20) to to electrically contact the fifth layer (19), and a fourth electrode (21), which overlays and extends through the sixth layer (20) over the second, the third and fourth layers (17 ', 19', 17) to electrically make these last connecting three layers together. 23. Switching device according to claim 22, characterized by a Isolation V-groove (51) extending at least into the first layer (15) between the areas of the second and fourth layers (17 ', # 17). 24. Switching device according to claim 22, characterized in that the first layer (15) is an epitalxial layer. 25. A method of manufacturing a semiconductor switching device, in particular according to claim 1, with a substrate of a first conductivity type, a first layer of a second conductivity type overlying a surface of the substrate, a second layer of a third conductivity type, which extends in a region of the first layer extends, a third layer of the first conductivity type that extends extends into the second layer, and a first V-groove that extends through the central portions extending the second and third layers into at least the first layer by introducing a fourth layer (17) of the third conductivity type into another Area of the first layer (15), Applying a fifth layer (19) of the first conduction type in the fourth layer (17), - application of a sixth Layer (20) of electrically insulating material on the first to fifth layers (15, 17 ', 19', 17, 19) and the first V-groove (33), - application of a first electrode (5 ') on the sixth layer (20) over the first V-groove (33), applying a second electrode (3 ') on the other surface of the substrate (13), applying a third electrode (7 ') extending through the sixth # layer (20) and electrical contacting the fifth layer (19), and applying a fourth electrode (21), which overlays and extends through the sixth layer. (20), onto the second, third and fourth layers (17 ', 19', 17).