DE29714397U1 - Circuit for storing the history of an analog signal for display on a digital screen - Google Patents

Description

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title

Circuit for storing the course of an analog signal for display on a digital screen

Description

The invention relates to a circuit for storing the course of an analog signal (AS) for display on a digital screen.

According to the known state of the art (Data Module Inc., USA), digital screens for displaying analog signals are known.

The analog signal is first digitized using a digital/analog converter; the digitized values are temporarily stored in a buffer memory and fed to the digital screen for visual display of the analog signal.

The sampling clock rate is based on the desired resolution of the analog signal. A higher sampling clock rate guarantees a better approximation of the signal displayed on the screen to the analog signal.

However, a higher clock rate also places higher demands on the circuitry, especially on the speed (switching speed) of the buffer memory used. Faster memories are more expensive than slower ones.

It is therefore an object of the invention to provide a circuit for storing the course of an analog signal (AS) for display on a digital screen, which allows a high sampling clock rate for the analog signal with a lower clock rate for the storage arrangement.

This object of the invention is solved in an advantageous manner by the features specified in the characterizing part of claim 1.

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Advantageous further developments of the invention are characterized in the subclaims.

An embodiment of the invention is shown in the drawings and is described in more detail below.
Show it:

Fig. 1A is a circuit diagram with two memories connected in parallel, one of which is supplied with a clock that is derived from a periodic square-wave voltage and the other of which is supplied with a clock that is supplied with the inverted periodic square-wave voltage,

FIG.1 B and FIG.1 C show a schematic representation of the periodic square wave voltage (FIG. 1B) according to FIG.1A and the inverted periodic square wave voltage (FIG. 1C) in temporal relation to one another with identification of the signal edges from which the clock signals are derived,

FIG. 1D and FIG. 1E show a schematic representation of the clock pulses (FIG. 1D) derived from the periodic square-wave voltage according to FIG. 1B and the clock pulses (FIG. 1E) derived from the inverted periodic square-wave voltage (FIG. 1C) in temporal relation to one another,

FIG.2 a schematic representation of the course of an analog signal with sampling times and sampling values,

FIG.2 shows a schematic representation of the course of an analog signal AS as a function of time t with sampling times and sampling values. The analog signal AS is sampled equidistantly at the times T11, T12, T21, T22, T31, T32 etc. The digitized sampling (ordinate) values are given in brackets at the corresponding sampling times. For example, the sampling value at time T52 is equal to -7. For simplification reasons, the dimension (e.g. volts or amps) for the sampling values is omitted.

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FIG. 1 B shows a schematic representation of a periodic square-wave voltage curve R with cycle C. FIG. 1 C shows a schematic representation of the inverted square-wave voltage curve R' with cycle C. Due to the inversion, both voltage curves are phase-shifted by half a cycle.

From the square wave voltage curve R, the clock pulses CL {FIG.

1 D) derived;

From the inverted square wave voltage curve R', the clock pulses CL' (FIG. 1E) are also derived from the positively rising signal edge at the times T12, T22, T32, T42, etc.

The time points Tn2 (n= 1-k) lie between the time points Tn 1 (n = 1-k)

When the clock pulses occur, the analog signal is also sampled (see FIG. 2); the designation of the sampling times in FIG. 1 and FIG. 2 are the same.

According to the illustration in FIG. 1 A, the analog signal AS is fed via an amplifier 4 (e.g. an amplifier with the type designation LT 1364 from Linear Technology, USA) to a first analog/digital converter 1-1 (e.g. one with the type designation AD 9059 BRS 9635 from Analog Devices Inc., USA) and a second (preferably the same) analog/digital converter 2-

1. The first analog/digital converter 1-1 is clock-controlled by the clock pulses CL, the second analog/digital converter by the clock pulses CL'.

The digitized sample values SC (solid line in FIG.2) from the first analog/digital converter 1-1 are stored in a first addressable memory 1 in an address-controlled manner. The address control is carried out via the address counter 1-2 driven by the clock pulses CL.

The digitized sample values SC {dashed line in FIG.2) from the second analog/digital converter 2-1 are address-controlled into a second digital memory

2. The address control is carried out via the address counter 2-2, which is driven by the clock pulses CL'.

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As already mentioned, the clock pulses CL are derived from the periodic square-wave voltage R. For this purpose, this square-wave voltage is fed to a circuit 1-3, which generates the clock pulses CL from the positive signal rise {in FIG. 1B, strongly drawn) in the square-wave voltage. Such a circuit is usually implemented using a standard FLIP-FLOP circuit.

To generate the clock pulses CL', the square-wave voltage R is first fed to an inverter circuit 3, which inverts the rising edges of this sequence, i.e. the positive rising edge becomes a negative one and vice versa. As a result, the inverted signal R' appears to be phase-shifted by half a cycle compared to the sequence R. Such inverter circuits are generally known and can be implemented, for example, using a FLIP-FLOP circuit.

The inverted signal R' is fed to a circuit 2-3 (which is functionally identical to circuit 1-3), which in turn generates the clock signals CL' from the positive edge rise of the sequence R'.

The circuit shown in FIG. IA makes it possible to store sample values, which are obtained with a high sampling rate at the times T11, T12, T21, T22,..., in memories with a lower storage clock rate - here half the sampling rate. While the corresponding sample values are recorded in the first memory at the clock times T11, T21, T31, T41,..., the second

Memory 2 at the cycle times T12, T22, T32, T42 , the corresponding

Sample values are recorded. The clock rate of the clock pulses CL and CL' is only half as large as the sampling rate of the analog signal at all times of CL and CL' taken together. The times of the clock sequence CL lie between the times of the clock sequence CL'.

If the analog signal is not sinusoidal, Fourier analysis shows that the signal is made up of sinusoidal oscillations of different frequencies. The higher the sampling rate, the more high-frequency sinusoidal components can be taken into account. In principle, the highest frequency of the sinusoidal oscillation to be taken into account by the device should be sampled twice during one period.

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The circuit shown in FIG. 1A is monitored and controlled by a microprocessor (not shown). For example, the addresses under which the sample values of the analog signal are to be written one after the other into memories 1 and 2 are specified by the microprocessor. The microprocessor recognizes when the buffer memory is fully loaded, i.e., can no longer store any sample values. In this case, no further sampling of the analog signal takes place: the sample values stored in memories 1 and 2 are read out in a time-interleaved, address-controlled manner and displayed on the digital screen.

As soon as memories 1 and 2 are free to receive new data, a new sampling process for the analog signal can follow. The resulting sample values are recorded in memories 1 and 2 as described above and then read out again for display on the digital screen.

The data is read out at a digital screen-specific readout rate, again under the control of the microprocessor.

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Claims (3)

•Pens 1 Protection claims 1. Circuit for storing the course of an analog signal (AS) for display on a digital screen,
characterized in that two addressable (1-2; 2-2) read/write memories (1; 2) are provided, that an analog/digital converter (1-1; 2-1) is connected upstream of each of these memories (1, 2), that the first memory (1), the analog/digital converter (1-1) connected upstream thereof and its address control (1-2) are clock-controlled by a first clock signal sequence (CL), that the second memory (2), the analog/digital converter (2-1) connected upstream thereof and its address control (2-2) are clock-controlled by a second clock signal sequence (CL'), that a clock generator circuit (1-3) is provided for generating the first clock signal sequence (CL) from a periodic square wave voltage sequence R, that an inverter circuit (3) is provided for inverting the periodic square-wave voltage sequence (R to R') and that a clock generator circuit (2-3) is provided for generating the second clock signal sequence (CL') from the inverted periodic square-wave voltage sequence (R'), which has the same function as the clock generator circuit (1-3), that the first (CL) and second clock signal sequences (CL') are time-shifted from each other by half a cycle (C) of the periodic square-wave voltage sequence (R), that the sampling of the analog signal (AS) can be carried out at a sampling rate which corresponds to the times of the clock signals in the first (CL) and second (CL') clock signal sequence,
that the sample values for the timing of the clock signals of the first U-97-005 ··· 'Sweet 2 ·· ·· ·· · Clock signal sequence (CL) from the analog/digital converter (1-1) connected upstream of the first memory (1) can be stored in the first memory (1) in a digitalized manner in the time cycle of the first clock signal sequence, that the sample values for the times of the clock signals of the second clock signal sequence (CL') from the analog/digital converter (2-1) connected upstream of the second memory (2) can be stored in the second memory (2) in a digitalized manner in the time cycle of the second clock signal sequence (CL'), and that the sample values stored in both memories (1 and 2) can be read out in a time-interleaved manner for display on the digital screen 2. Arrangement according to claim 1,
characterized in that the analog signal is a sine wave. 3. Arrangement according to claim 1, characterized in that the circuit is microprocessor controlled. U-97-005