DE2953215A1 - DIGITAL PHASE-LOCKED LOOP - Google Patents

Description

Digital phase locked loop

Field of application of the invention

The invention relates to a digital phase-locked loop, preferably for regenerating a bit sequence in synchronous data transmission systems, which contain redundantly coded information that is modulated in a suitable manner, transmitted from a transmitter to a receiver.

Description of the prior art

So that a data signal can be correctly regenerated on the receiver side of a synchronous data transmission system, the information, including the bit sequence and bit phase, must be available in the receiver. It is known to be a phase-locked Loop to use, for example, by two zero crossings in the transmitted baseband signal for regeneration the bit sequence is controlled.

Summary of the invention

In data transmission systems of the type mentioned above, there is sometimes the risk that the bit sequence regeneration device in an incorrect phase position synchro-

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is nized even if the frequency is correct in itself. This means that the system's data detector is not in the ■ ;;; Eye center in the eye diagram of the transmitted signal scans, so that the resulting bit error frequency is high is. Since a phase-synchronized loop only sporadically receives relevant control data in order to get out of this state correct synchronization can take a relatively long time to resolve. This is natural a clear disadvantage with all systems of this type and particularly troublesome with a system for a two-way connection on the same channel, e.g. alternate transmission and reception from each end station. In such systems, of course, the synchronization sequence is particularly frequent.

The phase-locked loop according to the invention _/ the distinguishing features thereof emerge from the appended patent claims, solves the technical problem mentioned above, provided that the transmitted signal is coded redundantly in some way. Above all, the solution offers the advantage that the synchronization time, for example when switching on, is considerably reduced by preventing synchronization in an incorrect phase position.

Brief description of the drawing

The invention will now be described with reference to the accompanying drawing, which shows an embodiment of a represents phase locked loop according to the invention.

Preferred embodiments

In the following description it is assumed that the receiver Can determine errors in the transmitted data stream. This possibility

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There is a possibility, for example, when data with a Parity bit or with redundant data coding. Such coding means that the transmitted signal elements are correlated, for example with a baseband coding according to the partial response method, a two-phase coding, AMI coding (alternating marking negation), Miller coding, etc.

The correlation between the signal elements in these codes is primarily used to determine an appropriate one Obtaining spectral distribution for transmission can however, they can also be used to enable error detection on the recipient side.

If AMI coding is chosen as an example, the binary Information "1" is transmitted with pulses whose polarity alternates and the binary information "0" with a missing one Impulse, i.e. a zero level. By simply checking whether the pulses are in the received baseband signal in the detector alternate polarity, detection errors or bipolar impairments (BPV) can be detected.

Is the regenerated bit sequence synchronized to the correct phase position to control the time in which the data detector finds the baseband signal and demodulates it, BPV only occurs because of interference in the data transmission itself on, on the other hand, the regenerated bit sequence is out of phase, for example during the synchronization sequence, or during incorrect synchronization of their phase position, the number of BPVs increases very sharply.

The drawing represents part of the receiver in a transmission system which is formed in accordance with the above. The transmitted data signal, which, if appropriate, is denodulated, arrives at the data detector 2 of the receiver, where it is scanned. In a subsequent process,

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it is decoded in decoder 7. One connected to the detector input Bit sequence extraction circuit 1 samples the baseband signal with respect to a periodically appearing feature, for example, the signal passage through certain predetermined levels or a fixed level, for example the NuIl-PegeI ^ ab. Every time the signal goes through one of these Level passes or another predetermined criterion is met, a pulse-shaped appears at the circuit output Signal. The output of the bit sequence extraction circuit 1 is connected to one of the inputs of a phase comparator circuit 5 connected, which has two inputs and two outputs. The outputs of the latter are with the control inputs a digitally controlled oscillator 4, the output of which is connected to the remaining input of the comparator circuit connected. As the illustration shows, the phase comparator circuit 5 compares the phase positions of the first and second input signals with respect to each other. If the phase of the first input signal is ahead, then appears an output signal at one of the outputs, while for the inverse relationship an output signal at the other output occurs. The control inputs of the oscillator receive these signals and the signals control the frequency of the oscillator up or down, depending on which control signal is present and in such a way that the phase difference between the input signals to the phase comparator circuit 5 decreases.

The output of the oscillator 4 is also with. the scanning signal input of the detector 2 connected, which means that the sampling frequency and phase of the detector are determined by the corresponding respective output variables of the oscillator 4.

However, according to the above, the loop can synchronize in an incorrect phase position, even if the recovered frequency is inherently correct.

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As mentioned, the consequence of this is that the bit error frequency in the output signal of the detector becomes high.

An error detector 3 is connected to the detector output according to the preferred embodiment and checks the detector output signal, to determine whether, taking into account the signal coding, the expected inherent redundant Properties are present. If this is not the case, a signal from the output of the error detector is sent to one of the inputs an adder circuit 6 connected thereto. This addition circuit is in the signal path for a Output signal of the phase comparator circuit 5 in such a way that its output with a control input of the oscillator 4 and its input with an output of the phase comparator circuit connected is.

For the typical case that the phase-locked loop was synchronized in an incorrect phase position and relevant control data for the oscillator 4 occur relatively infrequently to the loop from this state take out, the arrangement explained above obviously gives the possibility, depending on the connection with the addition circuit to put the oscillator in the correct phase position by a decrease or increase in frequency steer. Since the bit rate is high, at least in the initial stages of this correction, the pulse frequency becomes at the output of the error detector 3 high and consequently the synchronization sequence is fast.

The device operates in accordance with the above explanations of course, even if the loop was not synchronized in an incorrect phase position, but is in a far phase-shifted starting position at the beginning of the data transmission.

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The fault detector is thus permanently connected in the system, but during the normal state of equilibrium of the system mostly inactive. Only those in the actual transmission Errors introduced between the transmitter and receiver are registered and lead to the application of control pulses to the oscillator. However, such control pulses are looped without difficulty in the normal control cycle compensated.

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Claims (1)

V- Claim Digital phase-synchronized loop, preferably for bit sequence regeneration in synchronous data transmission systems, which redundantly send encoded data from a transmitter to a Transmit receiver, the data may be modulated in a predetermined manner, with a digitally controlled oscillator (4) with a first and a second control input and an output for Feeding of scanning signals to a data detector arranged in the receiver, a phase comparator circuit (5) which having first and second inputs and first and second outputs, the first input for receiving a bit sequence signal extracted from the transmitted signal is used and the other input to the output of the oscillator is connected, while its first output is connected to the first control input of the oscillator, characterized in that an addition circuit (6) with two inputs and one output with one input connected to the second output of the phase comparator circuit is connected with its output to the second input of the oscillator and with its second input to the Output of an error detector (3) is connected that the Error detector the output signal of the data detector at his Receives input and checks whether the expected, inherent, redundant properties, taking into account the signal coding this signal is present and, if this is not the case, emits a pulse-shaped signal at its output. 030601 / 0CU3