DE2952314C2 - - Google Patents

Description

The present invention relates to a data processing system according to the preamble of claim 1.

Typically, computer memory stores both operands as well as instructions. Operands generally Data that is processed and instructions are commands, which together form a computer program. A command word includes usually a statement part that has a storage space addressed in the computer memory. The number of storage locations in memory addressed by a given command can depend on the number of bits that the address part the command word and the hardware, that responds to these bits. Command words usually exist from 8-bit bytes, although any other number of bits in a byte can be used. Furthermore, it is not unusual with regard to the address part of a command, Use 1, 2, 3 or more bytes. With an address part In a command that has an 8-bit byte, only 2⁸ = 256 memory locations in the memory can be addressed. At 2nd Bytes with 8 bits each can already have 2¹⁶ = 65 536 memory locations can be addressed. Although with two 8 bit bytes more Storage spaces can be addressed are more time and a greater number of cycles each time it is called Address word from the memory and its processing required. Furthermore, more storage space is needed to accommodate the larger ones Save words. With the development trend to mini computers and microprocessors comes in the computer memory and power flow becoming more and more important. Regarding minicomputers, Microprocessors and dialog processors is therefore an improved addressing device is increasingly desired, a great addressing performance with a minimum of computer Cycle time when the address part of a command is retrieved.  It is also a malfunction of a computer system wanted a diagnosis by a remote station over hundreds or even being able to run thousands of kilometers. To this That way, the cost of maintaining a computer can be significant can be reduced.

There are many memory addressing devices in the prior art, their structure of the improved addressing of main memories serves. A typical addressing device for addressing the main memory of a computer can be US-PS 32 67 462 be removed. This facility is used for direct addressing, where any number of characters you want, starting with any arbitrarily selected position can.

The commands stored in main memory are general stored in adjacent storage locations in groups, so that the group forms a computer program. Accordingly, it is generally not required an additional address for the second command, etc. because the original address is modified can be made by adding the number 1 to the one already retrieved Address is added, causing the next adjacent and referenced storage space.

Other modification methods include index registers that are created by the original address can be addressed and the original Replace address or modify to a new address for the operand to be called. A typical facility this type can be found in US Pat. No. 3,284,778.

Further refinements in the addressing process led to the relative addressing where the address part of a command does not refer to the absolute memory address, but rather to any real address, such as a page or a segment within the main memory. This page or this segment can be relative to the beginning of the segment or be arranged on the side. Accordingly, the hardware  the relative address within a segment or page with the storage space of the beginning of this segment or this Link page to specify the absolute address. Typical Examples of such addressing devices can be found in the US patents 39 38 096 and 34 61 433.

Additional addressing methods increase the speed and the Performance by being smaller from a high-speed memory Use capacity to support main memory and by getting addresses in advance before they can be used by the addressing device. In this way the speed of addressing is increased. A typical one An example of such an addressing device can be found in US Pat 32 51 041.

To increase the capacity of a main memory, a virtual Storage system used, the operating system such as the IBM System 370 on one Magnetic disk maps existing addresses in the main memory. The user addresses the main memory and has the final print, a main memory with a very large capacity to have. Regarding the publication: Computer Organization and the System / 370 by Harry Katzan Jr. referenced in 1971 by Van Nostrand Reinhold Company of New York was released.

All of these addressing methods generally refer to Large computer systems and they require additional hardware in the form of index registers, buffer memories, etc. In addition storage space is not important for large computers like small computers.

In the case of small computers, there is therefore a need for an improved one Address modification system that the hardware of the basic addressing mechanism used and at the same time the cycle time for access to multiple address words reduced to a minimum.

It is therefore the object of the present invention, a Data processing system specify that with lower Cycle time and short command word length an extended Memory addressing allowed. The solution to this task succeeds according to the characteristic features of the patent claim 1. Further advantageous embodiments of the Data processing system according to the invention are the dependent claims removable.

The addressing of a memory with a capacity that greater than that specified by the command word length Storage capacity is already from US Pat. No. 3,553,653 known. This is done there by adding a few bits of the command word logically combined with a status word, while the remaining bits of the command word direct addressing of the memory.

In the case of the present invention, the present a short command word using certain bits of this Command word a PROM signal generator addressed to a information stored in certain registers when read out with regard to an address area expansion modify. For example, with a command word addressed by 8 bit 768 memory locations instead of 256 will.

An embodiment according to the present invention now with reference to the figures of the accompanying Drawing described. It shows  

Fig. 1 is a schematic overview of a computer system that uses a telephone line for dialogue.

Fig. 1AA uses a more detailed schematic diagram of a computer system, the telephone lines for dialogue.

Fig. 1A is a schematic block diagram of the preferred embodiment of the invention.

Fig. 1B is a schematic diagram of the typical Adressierformats the invention.

Fig. 1C an image of the side-division PROM.

Fig. 2A is a schematic diagram of the typical configuration of the real storage according to the invention.

Fig. 2B is a schematic diagram of a typical structure of the virtual memory according to the invention.

Fig. 3, 4, 4A, 4B, 4C, 5A, 5B, and 7 are diagrams of the preferred embodiment of the invention.

Fig. 6A is a flowchart for description of parts of the invention.

Fig. 6B is a timing chart for explaining an embodiment of the invention.

Fig. 1AA shows a known computer dialogue system in which the invention may be advantageously employed. The computer 107 in the front-door station is constantly switched on and supplied with power, regardless of whether the computer 101 is transmitting data in the central station or not. For the transmission of data, the central computer 101 dials the telephone number of the external computer 107 by manual operation or via an automatic dialing device 103 . The dialing signals are sent to the modem 104 , which provides line control signals to the transmission control unit 102 to thereby initiate the data transmission dialog. The transmission control unit 10 is, for example, a standard interface unit between a modem 104 and a computer 101, as is offered for example by the company Electronic Industries Associations under the name EIA RS-232-C standard. These standard interface units receive, generate and transmit various signals as follows:

• 1. Data signals
  • a) transmission data (to the modem);
    Data generated by the terminal or computer for transmission
  • b) Receive data (to the terminal or computer);
    Data received from the modem for the terminal
• 2. Time signals
  • a) timing for the transmission signal element;
    two connections are defined; one sends signal element time information from the sending terminal for the computer to its modem; the other sends time information from the sending modem through its terminal or the computer.
  • b) timing for the received signal element;
    two connections are defined, one of which sends timing information for the signal element from the receiving terminal to its modem or computer, while the other gives timing information from the received modem to its terminal. A modem for start-stop transmission does not need these timing signal connections; they are therefore optionally available.
• 3. Control signals
  • a) Send request (to the modem);
    Signals on this connection are generated by the transmitter terminal when it wants to provide information. The modem's carrier signal is transmitted during this connection's duty cycle. (With half-duplex operation, the switch-off state of this connection keeps the modem in the data reception state.)
  • b) ready to send (to the terminal or computer system);
    Signals on this connection are generated by the sending modem to indicate that it is ready to transmit data. They arise due to a transmission request from the transmitting unit (with full duplex operation, the modem is always in the transmission state).
  • c) data record readiness (to the terminal or computer);
    Signals on this connection are generated by the local modem to indicate to the transmitting device that the modem is operational. (The following control signals are only optionally available).
  • d) data terminal readiness (to the modem);
    If the terminal or the computer system transmits the switched-on state on this connection, it effects the connection of the modem to the transmission line. The off state causes disconnection to end a call or free up the line for other use.
  • e) ring indicator (to the terminal);
    a signal on this connection notifies the terminal that the modem is receiving a call signal from an external unit.
  • f) data carrier detector (to the terminal);
    a signal on this connection signals the reception of the carrier, ie the sine wave which the signal is modulated on. If the carrier is lost, for example due to a fault in the line, the terminal is informed of this by means of a switch-off status in the connection.
  • g) data modulation detector (to the terminal);
    the switch-on status on this connection reports to the terminal that the signal is being demodulated correctly by the modem. If the quality of the modulation drops below a predetermined threshold value, the terminal can take the necessary steps, for example requesting a new transmission or a reduction in the transmission speed.
  • h) speed selector;
    there are two speed dial connections, one to the modem and the other to the terminal. They can be used to change the transmission speed.
• 4. Ground connections
  • a) protective earth;
    this is connected to the machine frame and possibly external earth connections
  • b) signal ground connection;
    this forms the common reference potential for all circuits. When the connection between the central computer 101 and the modem 104 is established, the data transmission takes place as soon as the modem has converted the data into a form allowing transmission via the connecting line 105 . The data is received by the modem 106 and translated back into a digital format and then passed on to the receiving external computer 107 .

Fig. 1 shows a block diagram of an arrangement according to the invention. The standard interface transfer control between modem and data processor is omitted here for the sake of simplicity. By using a remote-controlled power supply device 125 of the computer need not be continuously switched in the remote station 124, but is only supplied with current when the central computer 120 desires data to the external computer 124 to send. If this is the case, a connection is established between the central computer 120 and the modem 123 , either automatically as described above or by lifting the telephone receiver and dialing the front-door station. As soon as the telephone connection with the front-door station is established, digital control signals 120 A are emitted by the central computer 120 and converted by the modem 121 into carrier-frequency analog signals 120 b , so that they can be transmitted by the modem 121 via the telephone lines 122 . You reach the outdoor station's modem 123 via line 122 , arrive there as 120 C analog signals and are converted back into digital signals by the modem 123 . These signals are received by the power supply control device 125 of the front-door station, which initiates the necessary steps to switch on the outdoor computer 124 in order to prepare it for the reception of data signals.

Referring to FIG. 1A, a block diagram is shown of a preferred embodiment of the invention, also showing the flow of information and the modification information for improved addressing. A microprocessor 101 , which can be specified by the commercially available type 6800 from Motorola Inc., uses an address bus 102 with 16 bits for addressing the main memory 108 . This results in an addressing possibility for the 64K bytes of the main memory 108 . The formats of the command are shown in Fig. 1B. There are primarily two formats, one of which identifies an 8-bit operation code and an 8-bit byte a, while the other has an 8-bit operation code, an 8-bit byte a and an 8-bit byte b. To save storage space and cycle time, it is more advantageous to use only byte b. Accordingly, in the schematic representation of FIG. 1A, register 103 uses the first 5 high-quality bits 8, 9, 10, 11 and 12 to address the page division signal generator 105 . This generator 105 is an integrated circuit that is commercially available under type number 5610 and is manufactured by Motorola Inc. The page division signal generator 105 stores 32 words that can be addressed by bits 8-12 of byte b. Since 5 bits are used to address the page division signal generator, each of the 32 words can be addressed. The internal circuit of the generator 105 is such that when the first 8 words are addressed, ie up to the address 07, the signal CPGLIN is activated, ie assumes the low level. When the next 4 words of signal generator 105 are addressed, ie addresses 8-11, both signals CPGLIN and CPGDIR are activated. When the next word 13 is addressed at address 12, all of the following signals are activated: CPGLIN, CPGDIR, CPGCCB and CPGAD4. The side division signal generator 105 is enabled when there is a low level output from the microprocessor 101 at its input terminal E. A low level input signal is applied from the output of NOR gate 104 to input terminal E of page division signal generator 105 when all of the input bits 1-8 of byte a are at the low level or "0". These bits 1-8 of byte a have the value "0" if a modification of the 16-bit address formed by bytes a and b is desired. If all bits of byte a have the value "0", a signal with a low level is accordingly obtained at the output of NOR gate 104 , which is fed to input terminal E of signal generator 105 for its release. If the side-division signal generator is enabled 105, so one of the control signal memory locations 105 is a b by bits 9-13 of the byte released. If one of these control signals 105 a is effective, ie has the low level, then the virtual 16-bit address 106 is modified to the real address 107 , which then addresses the main memory 108 . If none of the control signals 105 a is effective, then the 16-bit address 106 is identical to the 16-bit address 107 and there is no modification to the addressing of the memory 108 . The mechanism for executing this modification will be explained in more detail later in connection with FIG. 3. Therefore, assuming that the control signal CPGCCB is effective, the bit 11 of the virtual address is replaced by the bit at position α of the CCB register 115 and the bit 12 is replaced by the bit at position β in the CCB register 115 replaced to form the real address. If the control signal CPGDIR is effective, bit 10 of the virtual address is replaced by bit D of channel register 114 . If the control signal CPGLIN is effective, bit 9 of the virtual address is replaced by bit M of the CH register 114 and bit 8 of the virtual address is replaced by bit H of the CH register 114 . If the control signal CPGAD8 is active, bit 7 of the virtual address is replaced by the value "1". Finally, if the control signal CPGAD4 is active, bits 4, 5 and 6 of the virtual address are replaced by the value "1".

The CE $ U2U signal is used to address the line number of a selected receiver / transmitter USART 116 or 117 . Such receivers / transmitters are commercially available from Texas Instruments under type number 74LS245. The control signal CEI02U enables the I-bus 113 via the bidirectional bus driver 111 . These bidirectional bus drivers are also commercially available from Texas Instruments under type number 74LS245. The signal CEI02U allows a dialogue of the I-bus 113 with the U-bus 112 , while the signal CEU2I0 allows a dialogue of the U-bus 112 with the U-bus 113 . Various registers can be connected to the I-bus to save dialog information. Some typical such registers are, for example, the high order data register 120 , the low order data register 121 , the channel number register 122 and the status register 123 . These registers are in communication with the microprocessor via I-bus 113 and U-bus 112 and with main memory 108 via I-bus 113 and M-bus 109 . For the different connection to the I-bus 113 for a dialogue with the main memory 108 and with the microprocessor 101 , it is necessary to allocate memory space in the main memory for different lines and channels which are assigned to each dialogue connection. According to Fig. 2A it is seen that a part of the storage area of the real storage 200 is reserved for rows 0-3. Each line has 64 bytes and the total of 4 lines 0-3 contains the storage space for the logic table LCT. Each line 0-3 is further divided into two channels, each with 32 bytes. Accordingly, there are 8 channels with 32 bytes that comprise the 4 lines with 64 bytes of the logic table LCT. The next 256 bytes are reserved for channel instruction programs CCP. There are also 3 to 4 K bytes which are reserved together with the unused memory space for channel instruction programs CCP. Below this storage space there are an additional 256 bytes reserved for the CCB channel control block. As with the storage space for the logic table LCT, each line 0-3 is assigned a control block CCB of 64 bytes, which is divided into two channels with 32 bytes each. Below this memory space, memory space is reserved for the firmware main memory. Accordingly, it can be seen that each line 0-3 is assigned a memory space of the logic table LCT and the control block CCB, which is each divided into two channels. A portion of the addressing mechanism described in connection with Figure 1A addresses all of these memory locations. In order to do this, however, the two address bytes a and b must be taken, since an address byte comprises 8 bits and only 256 memory locations can be addressed with 8 bits. As can be seen in FIG. 2A, however, 768 storage locations (3 × 256) are provided, the 3K / 4K storage locations having not yet been taken into account. These 256 memory locations are the most frequently addressed memory locations, since lines 0-3 have to maintain a constant dialog with the logic tables LCD, the control blocks CCB and the firmware. To address the 768 memory locations, it is very ineffective to use the 16 bit address, which can normally address over 64,000 memory locations. With an 8-bit address, however, only 256 memory locations can be addressed. The exemplary embodiment of the present invention permits the addressing of the 768 memory locations by the first 5 bits 8-12 of the b-byte 103 by allowing the modification of the virtual address of FIG. 2B in the manner explained above. This short form of addressing saves cycle time and memory space.

Referring to FIG. 1C is a logic diagram of the page division signal generator 105, the side-division PROM that is shown 300th The scheme is self-explanatory. The address memory locations are shown in different number systems in the first three columns, while the last column contains the information that is actually stored in this address memory location. The fourth column specifies the hexadecimal storage locations that have the same content.

According to Fig. 2B 256 memory locations are shown in the memory 201, which is reserved as virtual memory. The first 64 memory locations or bytes are numbered decimally from 0 to 63 and hexadecimally from 0 to 3F and they include the logic table LCT of the current line used by the instruction program CCP. The next 32 memory locations or bytes at the decimal memory locations 64-95 and the hexadecimal memory locations 40-5F are reserved for the logic table LCD of the current channel used by the firmware. The next 8 memory locations or bytes corresponding to the decimal memory locations 96-102 or the hexadecimal memory locations 60-67 are reserved for the active control block CCB of the current channel. This is followed by an unused storage space and then three storage spaces for 8 bytes each, which are reserved for the receiver / transmitter USART of the current line, the covered receiver / transmitter USART of the current line and the expansion of the logic table LCT of the current channel.

A typical example illustrates how the improved addressing scheme of the invention works. It is therefore assumed that memory location 5 of line 0 of virtual memory 201 is to be addressed. Accordingly, all bits 0 to 7 of byte a of register 103 are "0", thereby enabling NOR gate 104 and page division signal generator 105 . The next 5 bits 8 to 12 also have the value "0", while bit 13 has the value "1", bit 14 has the value "0" and bit 15 has the value "1", which means that the binary address 101 or the decimal address is 5. The virtual address 106 also has the value "0" in bits 0 to 12, bit 13 having the value "1", bit 14 the value "0" and bit 15 the value "1". However, the control signal CPGLIN is additionally active since bits 8 to 12 of byte b in register 103 have the value "0". It has previously been shown that when bits 8-12 are used to address the first 8 words in the page division signal generator 105, the CPGLIN signal is active or low. When the CPGLIN signal is active, bits 8 and 9 of virtual address 106 are replaced accordingly by bits H and M of channel register 114 . With the initial assumption that memory location 5 of row 0 is addressed, bits H and M of channel register 114 have the value "0" and accordingly bits 8 and 9 of real address 107 also have the value "0". The final real address therefore has bits 0-12 with the value "0", bit 13 has the value "1", bit 14 has the value "0" and bit 15 has the value "1", making the fifth Memory location of line 0 of the real memory is addressed.

In order to develop the problem one step further, it is now assumed that the fifth memory location in line 1 is to be addressed. The bit content of register 103 and virtual address 106 will not have changed compared to the previous example. However, since row 1 is now to be addressed, channel register 114 has the value "0" in its high-quality bit H and a value "1" in bit M. If the signal CPGLIN is reactivated accordingly, since bits 8-12 of byte b of register 103 all have the value "0", bit 8 of virtual address 106 is replaced by bit H of channel register 114 , which has the value "0", and bit 9 of virtual address 106 is replaced by the middle one Bit M of channel register 114 is replaced, which in this example has the value "1", since line 1 is addressed. The real address 107 will therefore have the value "0" in bit positions 0 to 8, bit 9 will have the value "1", bits 10-12 will remain at the value "0", bit 13 will still have the value "1", bit 14 still has the value "0" and bit 15 still has the value "1". Accordingly, the hexadecimal memory location 45 is now addressed in real memory, which is the fifth memory location in line 1. It can easily be seen from this consideration that the same addressing can be carried out at memory location 5 of line 2 or line 3, by only replacing bits H and M of channel register 114 with bits 8 and 9 of virtual address 106 in order to achieve the to get real address 107 .

Referring to FIG. 3, the detailed logic block diagram of the page dividing means for improved allocation of virtual addresses to physical addresses is shown. First, a structural description is given, where the various structures of FIG. 3, where possible, are identified by elements in FIG. 1A. The operation of the structure of FIG. 3 is then described to show the various functions performed. It can be seen from Fig. 1A previously described that the page division mechanism is designed to modify bits 4 through 12 of the virtual address format 106 and form the final real address 107 , bits 4 through 12 either in accordance with the signals presented be modified or not. Referring to FIG. 3, it is noted that the multiplexer (MUX) 302, 303 and 304 and driver 305 provide the output signals on lines 302 A, 303 A, 304 A, 305 A and 305 B, which lines the modified bits 8 to represent the real address 107 . The multiplexer 301 and the driver 308 form the output signals on lines 301 A , 308 A , 308 B and 308 C , which represent bits 4 to 7 of the modified real address 107 . The register 309 corresponds to the register 114 in FIG. 1A and it stores the bits H, M and D and supplies these bits as output signals on the lines 309 A , 309 B and 309 C. The register corresponds to the CCB register 115 in FIG. 1A and it stores and supplies the α and β bits as signal outputs on the lines 310 A and 310 B.

The read only memory PROM 300 corresponds to the page division signal generator 105 . As described above, it delivers the various signals for the transmission of the virtual address 106 into the real address 107 . The division of the read-only memory PROM 300 corresponds to that in FIG. 1C. The drivers 305 and 306 are connected to an AND gate 311 A to form the real memory address bits 11 and 12. Register 311 is used to store various signals.

Each of these facilities is commercially available from manufacturers such as Texas Instruments, Motorola, Intel and other semiconductor manufacturers available in the table below I the type numbers of the various components are given:

Table I

Component with reference number

MUX 301, 302, 303 and 304 74LS253 drivers 305, 306, 307 and 308 74LS241 registers 114, 115, 120, 121, 122, 123, 123 A , 309, 310, 311 360, 361, 370, 371, 372 and 382 74LS374 AND gate 311 A , 354, 358 A , 371 and 372 74LS08 PROM 300 and 384 5610 decoders 351, 352, 353, 355, 356, 357 and 380 74LS139 comparators 358 and 358 B 74LS08 USART 116 and 117 - bus drivers 110 and 111 -

Referring again to FIG. 3, the operation and function of the page subdivision device for the improved assignment of virtual addresses to real addresses will be described in more detail. As previously described in connection with FIG. 1A, the dialog page division line signal CPGLIN assumes the active state by assuming the low level when the addresses 0 to 7 of the PROM chip 300 are addressed. This is shown in the page division PROM list in FIG. 1C, in which the content of the list has the value 01111111 in the first 8 positions. Bit position 7 has the value "0", which activates the signal CPGLIN. This signal is then fed to input terminals 2ag and 2ah of multiplexers 302 and 303, respectively. The other input control signal at the input connections 1ag and 1ah of the multiplexers 302 and 303 is predetermined by the logic signal "1" (LOGIC 1), which is switched so that it is always at the high level. If the signal CPGLIN is active, ie has the low level, it addresses the input connections 1ag and 1ah of the multiplexers 302 and 303 , which means that the signals are passed on at the input connections 1g and 1h and as output signals 302 A and 303 A accordingly occur. By tracing the signal CPGCNH at the input terminal 1g of the multiplexer 302 to its source, it can be seen that it comes from the high quality bit on the line 309 A of the channel register 309 . In the same way, by tracing back the input signal CPGCNL at the input terminal 1h of the multiplexer 303, it can be determined that it comes from the output line 309 B of medium significance. This corresponds to bits H and M of channel register 114 in Fig. 1A. Accordingly, when the signal CPGLIN is activated, bits H and M of registers 114 and 309 are used accordingly for virtual address bits 8 and 9 on output lines 302 A and 303 A. Conversely, if the signal CPGLIN is not activated, the address bits 8 and 9 of the virtual address are not modified and these are passed on as they are to the output lines 302 A and 303 A of the multiplexers 302 and 303 . This is due to the fact that when the CPGLIN signal and the LOGIC 1 signal are high, addresses 3g and 3h are addressed decimally (binary 11) to multiplexers 302 and 303 . The input address 3g of the multiplexer 302 is predetermined by the signal CADU08, which is interpreted as the dialog address of the microprocessor bit 8. The input address 3h of the multiplexer 303 is predetermined by the signal CADU09, which is interpreted as a dialog address microprocessor bit 9. If the input connections 3g and 3h are addressed, these connections are activated and the addresses on these connections can be passed on to the output lines 302 A and 303 A of the multiplexers 302 and 303 .

The next control bit for the modification of the virtual address 106 , which is taken from the PROM chip 300 , is the directional bit CPGDIR. The directional bit is the low-order bit D in the channel register 114 or the bit on the line 309 C at the output of the channel register 309 . The directional bit is activated when the addresses 8, 9, 10 and 11 (decimal) of the read-only memory PROM 300 are addressed (see FIG. 1C). If these bits 8-11 are addressed, the output signal CPGLIN also becomes active. Accordingly, in addition to the signal CPGLIN applied to the multiplexers 302 and 303 , the signal CPGDIR is supplied to the input terminals 1d and 1ai of the multiplexers 301 and 304 . If the signal CPGDIR at input terminal 1 of multiplexer 304 is inactive, it does not matter whether the input signal CPGAD8 at input terminal 2ai of multiplexer 304 is high or low, since either state activates input terminal 0b or 2b (binary addresses 0 or 11) and the signal CPGCND is supplied to these two addresses. The signal CPGCND comes from the output line 309 C of the channel register 309 , which corresponds to the bit D of the channel register 114 and 309 . Accordingly, when the directional bit CPGDIR is activated, the 10th bit (decimal) of the virtual address 106 is modified in accordance with the content of the bit D of the channel register 114 . There is no influence on the signal CPGDIR at the input connection 1d of the multiplexer 301 , unless the signal CPGAD8 is also activated. This is due to the fact that when the signal CPGAD8 (high level) is inactive, only the addresses 2e or 3e (binary 10 or 11) of the multiplexer 301 can be addressed, and these two are the same and represent bit 7 of the dialog address of the microprocessor. However, if the signal CPGAD8 from the read-only memory PROM 300 is also activated (low level), only the addresses 0e or 1e (binary 00 or 01) of the multiplexer 301 are addressed and active. The logic signal LOGIC 1 with the value "1" is supplied to both addresses and this signal is passed on to the output line 301 A of the multiplexer 301 if both signals CPGAD8 and CPGDIR are active or if only the signal CPGAD8 is active.

Thus, when the CPGAD8 signal is active, bit 7 becomes the virtual one Modified address and set to the value "1".

As previously described with reference to FIG. 1A, bits 11 and 12 of virtual address 106 are replaced by channel bits α and β of register 115 when channel register bit CPGCCB is active, ie at the low level. The register 310 in Figure 3 corresponds to. The channel register 115 and the bit CPGCCH on the output line 310 A the bit α of the channel register 115 and the bit CPGCCL on the output line 310 B the bit β of the register 115 corresponds to these bits replace the bits 11 and 12 the virtual address when the signal CPGCCB is active, ie at the low level. Let us now consider what happens. If the signal CPGCCB is activated, it is fed to the input terminal 11 of the driver 306 and an input terminal of the AND gate 311 A. Accordingly, the driver 306 is turned on and the channel Steuerbitsignale CPPGCCH and CPGCCL on the output lines 310 A and 310 B are applied to the terminals 1 h and 0h the driver 306 accordingly and passed to the output lines 306 A and 306 B of the driver 306 to the Replace bits 11 and 12 of the virtual memory address. It should be noted that if the signal CPGCCB is low at input terminal 1 of driver 306, it is enabled, but the same signal applied to input terminal 19 of driver 305 blocks this driver. Thus, the signals CADU on the input connections 24 and 25 of the driver 305 are not passed on to the output connections 305 A and 305 B , but are replaced by the bits of the channel register 310 in the manner described above. It can thus be seen that either driver 306 or driver 305 , but not both, is enabled and that either the channel register bits are passed through driver 306 or the microprocessor address bits are passed through driver 305 to the output.

Finally, the modification of bits 4, 5 and 6 will be explained with regard to the virtual address modification. As was previously determined with reference to FIG. 1A, this is done via the signal CPGAD4. When address 12 (decimal) of the page division signal generator is addressed, all of the following signals become active: CPGLIN, CPGDIR, CPGCCB and CPGAD4. This can be seen from FIG. 1C, in which the address 12 (decimal) has the following bit combination 00001111. Thus, bit positions 4, 5, 6 and 7 are at the low level and are active, so that the signal generator 105 in Fig. 1A outputs the signals CPGAD4, CPGCCB, CPGDIR and CPGLIN. It has already been shown how the first 3 signals modify the virtual address in its active state and it will now be shown how the signal CPGAD4 modifies the virtual address and the value "1" in bits 4, 5 and 6 of the inserts virtual address. The signal CPGAD4 is fed to the enable terminal 19 of the driver 308 . When driver 308 is enabled, binary value "1" in bits 4, 5 and 6 is set accordingly. If it is not released, the microprocessor address CADU for bits 4, 5 and 6 is passed on accordingly. The reason for this is that driver 308 is a commercially available tri-state circuit of type LS 241, which has pull-up resistors for the applied signal. Accordingly, when a low level signal such as the CPGAD4 signal is asserted, this signal does not enable driver 308 and the output signals are pulled up to + 5V, resulting in logic level "1". If, on the other hand, the signal CPGAD4 is inactive, that is to say the high level, the driver 308 is released and allows the address signals to be passed on to the input connections 1k, 2k and 3k of the driver 308 .

The page division signal generator 105 in FIG. 1A and its equivalent in the form of the read-only memory PROM 300 in FIG. 3 not only generate signals by which the memory 109 can be addressed more effectively, but also generate signals which are more effective addressing and more effective Enable dialogue between the latch 108 , the microprocessor 101 and the various registers and peripheral devices on the I-bus and the U-bus. This dialogue between the various devices, such as between the registers and the memory and the registers using the U-bus and the I-bus, is triggered by activating the signal CEU2I0. The signal CEU2I0 has the low level and is activated when the assigned bit in the memory map according to FIG. 1C has the value "0". It should be noted that the signal CEU2I0 corresponds to the bit position 1 of the page division signal generator 105 . According to Fig. 1C, showing the memory map of the Seitenunterteilungs- signal generator 105 and its corresponding read-only memory PROM 300, it is seen that there are 3 addresses at which one is stored in bit position 1 is "0". These addresses correspond to the decimal storage locations 18, 21 and 22 or the virtual hexadecimal storage locations 90, A8 and B0. Therefore, if any of these memory locations of the page division signal generator 105 or the read-only memory PROM 300 are addressed by the microprocessor 101 , the signal CEU2I0 becomes active and has the low level. The signal DEU2I0 triggers the dialog process and controls the release of the bus driver 111 in FIG. 1A and the bus driver 711 A in FIG. 7. The signal is also fed as an input to the AND gate 354 in FIG. 4 and ensures a pulse output after the data on the bus has become valid.

Referring to FIGS. 3 and 4 a signal CEU2I0 in bit position 1 of the memory PROM is generated 300 when the release of the I-bus driver 711 A is desired to transmit data from the U-bus to the I-bus and this either write in the channel register 114 , the CCB register 115 or the S register 123 A. In accordance with Fig. 4 it can be seen that the signal CEU2I0 an input terminal of the AND gate 354 is supplied to an AND operation with a key signal CTPHZD is subjected, to generate the signal CEU2I0-10 at the output of AND gate 354. This signal is then fed to the enable input of decoder 355 . Furthermore, the bits 10 and 11 of the address 103 of the dialog address unit are fed to the input connections 20 A and 10 A of the decoder 355 . These bits are then decoded to activate one of 4 signals at the output ports of decoder 355 . If the bits 10 and 11 at the input connections 20 A and 10 A of the decoder 355 have the value 10 or the binary decimal value 3, then the output signal CEU2I0-A2 is released and applied to the release input of the decoder 357 . In addition, bits 13 and 14 of the dialog address unit, ie the signals CADU13 and CADU14, are applied to the input connections 2PA and 1PA of the deodoriser 357 . If both bits 13 and 14 have the value "0", the signal CEI2CN is activated at the output of decoder 357 and used to write into channel register 114 in FIG. 1A and 309 in FIG. 3, respectively. On the other hand, the bits 13 and 14 have the values "0" and "1" and supplied as signals CADU13 and CADU14 the input terminals 2PA and 1PA of the decoder 357, so at the output of the decoder is 357, the signal CEI2CB and used actively to the CCB register 115 in Fig. 1A and 310 in Fig. 3 to address. Finally, if bits 13 and 14, which are supplied as signals CADU13 and CADU14 to the input connections 2PA and 1PA of the decoder 357 , have the value "1" and "0" or the decimal value 2, then the signal at the output of the decoder 357 CEI2SR activated and used to address the S register 123 A. The signal CEU2I0 is thus used to enable the bus driver 111 and the address registers 114, 115 and 322 A. Accordingly, when the microprocessor 101 processes a write command which specifies the writing of the accumulator contents of the microprocessor into the hexadecimal storage space A8, the microprocessor applies the contents of the accumulator to the U-bus and releases the bus driver 11 in the writing direction, whereupon the bus information is released is keyed into the appropriate register address.

If a write command is being processed and information is being written to any of the registers on the I-bus, then the bus driver 110 of FIG. 1A also enables the M-bus 109 and the same information written in the address register is also written into an addressed section of the I-bus Memory 108 inscribed. In this connection, reference is also made to FIGS. 2A and 2B. The bus driver 110 is released by a missing signal CEMB2U and it switches the M-Bus through in the direction of the memory 108 . Thus, the information written in the registers is also written into a "shadow memory" which stores the information for diagnostic purposes or for the test and which forms a storage space for storing data when external maintenance is performed.

When reading data from the I-bus to the U-bus, it is necessary to block the data transmission from the M-bus to the U-bus. This allows the I-bus to control the data on the U-bus. This function is carried out by generating the signal CEI02U in the page division signal generator 105 . This signal is then fed to the enable terminal of decoder 351 in Fig. 4 and at the same time bits 9 and 10 of address 103 are applied to input terminals 2K and 1K as signals CADU09 and CADU10. These signals are subjected to a first decoding level to produce an output signal CEI02U-A1 at the output terminal 01 of the decoder 351 when the input bits 9 and 10 have the values "0" and "1", respectively. The CEI02U-A1 signal is then applied to the enable terminal of decoder 352 along with bits 14 and 15 on input terminals 2LA and 1LA. Depending on the binary value of bits 14 and 15, one of 4 subinstruction signals is generated at the output terminals of decoder 352 . If bits 14 and 15 have the value "0", which corresponds to the addressing of the hexadecimal memory location A8 in the virtual memory, a sub-instruction CEDH2I-00 is generated at the output terminal 00 of the decoder 352 . This signal is then fed to the enable terminal of register 360 . Register 360 corresponds to high quality data register 120 in FIG. 1A. The signal CEI02U accordingly represents a means for reading data from the high-quality data register 120 onto the I-bus and onto the U-bus. However, since the bus driver 110 has been blocked by the presence of the signal CEMB2U, it is blocked by the address 103 addressed memory location is not read and only the high-quality data register 120 is read. Similarly, low order data register 121 is read when bits 14 and 15 are 01, thereby addressing output terminal 01 of decoder 352 . Thus, the CEDL2I-00 signal is generated which is applied to the enable terminal of register 361 in Fig. 4A. It can thus be seen that registers 360 and 361 according to FIG. 4A correspond to registers 120 and 121 in FIG. 1A.

The bus driver 110 in Fig. 1A corresponds to the driver 370th in Figure 4B. This is a bidirectional driver and it can either drive data from the memory bus 109 to the U-bus 112 or vice versa. The direction of the data transfer is controlled by the signal CEMB2U. If the signal is present, data flow from memory bus 109 to microprocessor bus 112 is permitted, and if the signal is not present, data transfer in the opposite direction is permitted. The CEMB2U signal is generated via the AND gates 371 and 372 in FIG. 4. These AND gates perform a simple AND operation of various signals, these signals being predetermined by the microprocessor read signal CUREAD, the key signal CIPHZ2 and the dialog enable signals CESR2U and CEIN2U. From these signals, the signal CEMB2U is generated, which is then fed to the one input terminal of the AND gate 371 . It should be noted that in the case of a transfer operation from the I-bus to the U-bus, that is to say in other words in the case of a read operation from a register on the I-bus to the U-bus, this signal at the input of AND gate 371 has a high level and that the signal CEMB2U has the high level, even if the remaining signals have the high level. When this high level signal is applied to the input terminal of driver 370 in Fig. 4B, it blocks the passage of information through bus driver 110 from the I-bus to the M-bus.

The addressing of the receiver / transmitter USART 116 and 117 will now be described with reference to FIGS . 1A, 1C and 4. The signal that triggers this addressing is given by the signal CE $ U2U, which occurs as bit 3 on the page division signal generator 105 in FIG. 1A. It is to be removed Fig. 1C that the only address having the value "0" in bit position 3, the hexadecimal Address 88. If this memory location is therefore addressed, bits 0, 3, 4, and 7 become active. As previously mentioned, bit 3 specifies the signal CE $ U2U, which is fed to the enable terminal of the decoder 350 A in FIG. 4 and which participates in the decoding of the middle bit of the channel number CPGCNL. Depending on the value of this bit, one of two output signals CE0U2U and CE1U2U is effective at the output connections 0 and 1 of the 350 A decoder. If the signal CE0U2U is active, the receiver / transmitter USART 116 is released, while if the signal CE1U2U is active, the receiver / transmitter USART 117 is released. If information is written into the released receiver / transmitter USART, it is also written into the part of the memory which is addressed by the address 103 . This type of dual addressing uses two virtual addresses that are converted to the same physical address to form a duplicate address or a shadow image of the physical device actually addressed. For example, it has been shown how the hexadecimal address 88 addresses the receiver / transmitter USART by generating an enable signal for the correct receiver / transmitter USART. Referring to FIG. 1C is seen that the hexadecimal address C8 has the same binary value, such as hexadecimal address 88, with one exception, which is that the bit number 3 of the hexadecimal address 88 has the value "0", while the bit number 3 the hexadecimal address C8 has the value "1". Accordingly, it can be seen that, with the exception of the third bit, the hexadecimal address 88 supplies the same signals as the hexadecimal address C8, so that the address C8 can be regarded as the shadow of the addressed receiver / transmitter USART if the signal CESU2U through the hexadecimal address 88 is delivered. It can thus be seen that the hexadecimal address 88 or decimal address 17 addresses the actual USART data, while the hexadecimal address C8 or decimal address 25 addresses their shadows. Accordingly, when writing under the hexadecimal address 88, USART is written into the receiver / transmitter and the appropriate memory location is addressed, which is specified by the hexadecimal address C8, which is done in accordance with the principles explained above. This is explained using a typical example. First, the page division signal generator 105 is addressed with respect to the decimal storage space 17. Using the address format 103 , the address is as follows: 0000000010001000. It should be noted that bits 8 to 12, which effect the actual addressing, contain the decimal number 17 in binary format. Referring to FIG. 1C it is seen that the decimal space has 17 active bits in the positions 0, 3, 4 and 7. Bit 0 generates the signal CPGAD8 in the page division signal generator 105 and this signal sets the bit 7 to the value "1" in the active state. Bit 3 forms the signal which addresses the receiver / transmitter USART and which does not take part in changing the virtual address to a real address. Bit 4 of the page division signal generator specifies the signal CPGAD4, which in its active state sets bits 4, 5 and 6 to the value "1". Finally, bit 7 of signal generator 105 supplies the signal CPGLIN in the active state and sets the high-quality bit and the medium-value bit of the channel register to bit positions 8 and 9 of the real address. Assuming in the present example that each bit position has the value "0", bits 8 and 9 result in the value "0" and the final real address has the value: 000011110000000. If the decimal address 25 is now addressed, then Address format 103 takes the following form: 0000000011001000. Again, FIG. 1C shows that the following signals are active: CPGAD8, CPGAD4 and CPGLIN. Since the signal CE $ U2U, which was also present in the previous example, does not participate in the change of the addresses, the final real address is the same as the previously specified address and has the following form: 000011110000000. It can thus be seen that the same address is addressed in memory. Accordingly, if external maintenance or diagnostic operations are required, only the shadow memory can be addressed and addressing the actual receiver / transmitter USART is not necessary. The same applies in principle to other peripheral devices or registers that are also connected to the I-bus.

This shading technique when addressing a hardware component such as the receiver / transmitter USART, des Channel register or channel control block register, etc. is special useful and saves cycle time when there is an interruption occurs in which the content of a register, for example of the CCB register must be replaced. In the conventional version the content of the register is read out and in a temporary memory is saved and it becomes the new information registered in the register. If the original content of the register is to be written back, the register must first read out again and the content in a temporary Memory can be saved and then the original Content to be written back. With the invention The shading concept only has to be used in an interrupt mode the new information is written into the register,  there is a shadow or an image of the original information in the register in a predetermined memory location of the main memory is saved. The old information remains in that Receive shadow storage space and if this is in the register can be written back directly from the shadow Storage space can be read out. Since about 3 µs for a read operation and 4µs are required for a write operation, can save a total of 4µs during each complete cycle will.

The preferred embodiment of a vectorial interruption will be described below with reference to FIGS. 5 and 6. Fig. 6B shows the timing diagram of the interrupt sequence. The PTIME3 signal is a mass-effective TTL signal that is generated by the CPU 600 every 500 ns and has a pulse width of 100 ns. This signal is used extensively by system 600 a peripheral controls to set and reset states on buses 620, 621 and 622 and to act as a data strobe. The BINTR signal is the interrupt request signal that is on an open collector driver line on the buses and is grounded by some peripheral control of the system when that controller attempts to interrupt. The PIOCT signal is also a mass TTL signal that is used by the CPU 600 to indicate to a selected controller that there are coded states on the bus that transmit the bus dialog control information to the controller. The data bus valid signal indicates that the data on the bus is stabilized. When activated by the CPU 600 , the PBYTE signal provides the low-order byte, ie bits 8-15 of the addressed word, to a controller such as the microprocessor 601 . Finally, the PBBUSY or PROCED signals indicate in the active state that either a controller is busy and rejects the instruction or that it accepted the last interrupt that was on the bus.

The microprocessor interrupt mechanism described here is activated when the CPU 600 triggers an I / O command that is directed to one of the I / O devices 620 and 601 via the I / O bus via the channel number. Should the command be directed to this microprocessor 601 , a decoder recognizes the channel number and sets the microprocessor interrupt request. The 16 bits of information on the system bus during instruction initiation (see Fig. 6B, signal PIOCT) include the 10 bit channel number and the function codes a and b. At the time the channel number is compared and it is determined that it is the microprocessor's channel number, this information is stored in register 362 (channel number) and register 311 (FCN) and an interrupt request to the microprocessor is made in a flip-flop. Flop saved. Since the microprocessor treats this request as a masked interrupt, its action can be postponed. The chronological sequence of these measures is shown in FIG. 6B.

Typically, when the microprocessor 601 receives an interrupt command, it sequentially addresses hexadecimal locations FFF8 and FFF9 in main memory 108 , in which the high and low bytes of the interrupt vector are stored. It can be seen that the hexadecimal address FFF8 with binary notation in the address format 103 has the following bit combination: 1111111111111000. In the same way, the hexadecimal address FFF9 with binary notation results as follows: 1111111111111001. If the address FFF9 is accordingly addressed after the high-quality byte of the interrupt register has been fetched, the bits with the value "1" of the address FFF9 take effect. These bit signals are supplied in various combinations or individually to the various hardware circuit elements in FIG. 3. In other words, these address bits are used instead of the hexadecimal address FFF9 in the main memory 608 A and 608 B to a) disable the page division address mechanism and b) enable the decoder 380 in the CPU, which in turn c) releases the register 311 , to deliver a predetermined base address to the PROM / RAM 601 B and which e) in turn contains the address of a selected function code within 64 function codes. This happens when bits 0, 1, 2, 13, 14 and 15 of the aforementioned address are applied to the input ports of decoder 380 as shown in FIG. 4C. As previously mentioned, when addressing the hexadecimal address FFF9, bits 13 and 14 have a value of "0" and bit 15 have a value of "1", these bits being fed to the decoder 380 enable ports. In addition, bits 0, 1 and 2 of the address, all of which have the value "1", are applied to terminals 1, 2 and 4 of decoder 380 in Fig. 4C. Since the connections to which bits 13 and 14 are supplied in the form of signals CADU13 and CADU14 have an inversion and the information at connections 1, 2 and 4 of decoder 380 each has the value "1", an active signal results CADUH7 at output terminal 7 of decoder 380. This is the case since binary value 111 is decoded as decimal value 7. The CADUH7 signal is then applied to the enable terminal F of the register 311 in Fig. 3 and is also applied simultaneously to the enable / disable input terminal of the multiplexers 301, 302 and 303 and to the AND gate 311 A , thereby causing the page division addressing mechanism is blocked. Instead of accessing the hexadecimal memory location FFF9, the register 311 is released accordingly and it supplies the low-order bits 10 to 15 at its output connections. These bits form an address for addressing the RAM or the PROM 601 B memory. The content at the address of the memory 601 B is stored in the least significant byte position of the program counter 601 D. The information in the register 311 represents the function code information according to FIG. 5B, which was delivered by the central processing unit CPU when an interruption was triggered (see signal PBYTE in FIG. 6B). Since the page division addressing mechanism has been disabled and since the CADUH7 signal again addresses the hexadecimal memory location FFF9 to the register 311 and because the CADUH7 signal also enables the register 311 , the least significant bits 10 to 15 of the register 311 are used to open Access information in the memory 601 B , which is stored in the low byte position of the program counter 601 D. Since there are 6 bits in the least significant byte of the function code, up to 64 memory locations in the RAM or PROM 601 B can be addressed. Each of these memory locations contains the low-order byte of the interrupt vector, to which its function code is assigned, which, when supplemented, includes the interrupt address.

Depending on the information content of the function code, an interrupt is accordingly achieved which can start in any of 64 different storage locations in the PROM 601 B memory and can accordingly carry out up to 64 different interrupt operations. In addition, the program counter 601 D or other registers receive their information from a shadow memory location and accordingly it is not necessary to first unload and then save the old information and then load the new information and repeat the same process again if the Interrupt loop is exited. It should also be noted that the normal microprocessor interrupt procedure which directs the microprocessor to address FFF9 is bypassed and an address of 64 unique addresses is automatically provided by the function code, thereby effectively clipping to 64 different vectors or routines.

Referring to Figs. 4 and 6B should be noted that this AND gate 358 A is supplied with an activation of the signal CADUH7 together with a phase signal CTPHZD, whereby the signal CEI2CN triggered. In addition, the CADUH7 signal is ORed with the CECN2I signal in gate 358 B to trigger the CECN2I signal. The signal CEI2CN is applied to the terminal C of the channel register 309 in FIG. 3, which, as previously explained, corresponds to the channel register 115 A in FIG. 1A. In the same way, the signal CECN2I is used to clock the content of the channel number register 122 in FIG. 1A on the I-bus or vice versa.

The vector break accordingly does two things: First, it automatically addresses any of 64 memory locations according to a unique function code and then loads the hardware channel number register with the channel number that is required for treatment. The Channel control block register CCB-115 can also be used in one Interruption can be changed, what of the function code depends.

Claims (4)

1. Data processing system with at least one microprocessor, a plurality of address modification registers and a memory, the memory locations of which can be addressed by real addresses and which contains command words that can be executed by the microprocessor, some command words being of short type, ie having shorter address fields than other command words and addressing a first one Serve the number of memory locations, which is less than the total number of memory locations, characterized by a device for expanding the addressing options specified by the short-word command words, which in combination has the following features:

• a) means ( 104 ) for determining whether a command word currently being processed by the microprocessor ( 101 ) is of the short type;
• b) a signal generating device ( 105 ) which can be activated by this determining device ( 104 ) and which generates a predetermined number of control signals (CPGLIN to CPGAD8) from a part of the short address field when a short-word command word is present; and
• c) a device ( 106, 107 ) connected to the signal generating device ( 105 ) and the address modification registers ( 114, 115 ) for supplementing the address field of the short type into real addresses for addressing the memory ( 108 ), the number of which is formed by this device Addresses is greater than the first number of memory locations.

2. Data processing system according to claim 1, characterized by
a first device ( 103 ) for generating a predetermined number of virtual addresses (in bits 8-12 in the b-byte), on the basis of which the signal generating device ( 105 ) generates the predetermined control signals (CPGLIN to CPGAD8) when activated, which in the set state specify multiple predetermined substates, and
a gate device ( 301-308 ) which is connected to the control signals (CPGLIN to CPGAD8) and the address modification registers ( 114, 115 ) to form real addresses, the gate device ( 301-308 ) in the non-set state of the control signals (CPGLIN to CPGAD8) forms a real address corresponding to a first virtual address, and in the set state of the control signals (CPGLIN to CPGAD8) forms a real address from bits of the address modification data and from bits of a second virtual address based on a predetermined substate, the number of bits of the address modification data and the number of bits of the second virtual address used is determined by the selected substate of the control signals. 3. Data processing system according to claim 1 or 2, characterized in that the signal generating device ( 105 ) is predetermined by a programmable read-only memory (PROM). 4. Data processing system according to claim 2, characterized in that the gate device comprises multiplexers ( 301-304 ) and drivers ( 305-308 ).