DE29521024U1 - Circuit arrangement for generating a clock signal - Google Patents

Circuit arrangement for generating a clock signal

Info

Publication number
DE29521024U1
DE29521024U1 DE29521024U DE29521024U DE29521024U1 DE 29521024 U1 DE29521024 U1 DE 29521024U1 DE 29521024 U DE29521024 U DE 29521024U DE 29521024 U DE29521024 U DE 29521024U DE 29521024 U1 DE29521024 U1 DE 29521024U1
Authority
DE
Germany
Prior art keywords
generating
clock signal
circuit arrangement
arrangement
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE29521024U
Other languages
German (de)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE29521024U priority Critical patent/DE29521024U1/en
Publication of DE29521024U1 publication Critical patent/DE29521024U1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/745—Simultaneous conversion using current sources as quantisation value generators with weighted currents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Evolutionary Computation (AREA)
  • Fuzzy Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
DE29521024U 1995-04-12 1995-04-12 Circuit arrangement for generating a clock signal Expired - Lifetime DE29521024U1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE29521024U DE29521024U1 (en) 1995-04-12 1995-04-12 Circuit arrangement for generating a clock signal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19513956 1995-04-12
DE29521024U DE29521024U1 (en) 1995-04-12 1995-04-12 Circuit arrangement for generating a clock signal

Publications (1)

Publication Number Publication Date
DE29521024U1 true DE29521024U1 (en) 1996-06-27

Family

ID=26014367

Family Applications (1)

Application Number Title Priority Date Filing Date
DE29521024U Expired - Lifetime DE29521024U1 (en) 1995-04-12 1995-04-12 Circuit arrangement for generating a clock signal

Country Status (1)

Country Link
DE (1) DE29521024U1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10147942A1 (en) * 2001-09-28 2003-04-24 Siemens Ag Analog key-press detection circuit has keys arranged in base, collector or emitter lines of transistors connected to series-connected resistors
DE102004063198A1 (en) * 2004-12-23 2006-07-13 Atmel Germany Gmbh Driver circuit, in particular for laser diodes and method for providing a drive pulse train
DE102011052895B4 (en) * 2010-08-24 2017-05-18 Infineon Technologies Ag Digital waveform synthesis

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10147942A1 (en) * 2001-09-28 2003-04-24 Siemens Ag Analog key-press detection circuit has keys arranged in base, collector or emitter lines of transistors connected to series-connected resistors
DE10147942B4 (en) * 2001-09-28 2004-02-12 Siemens Ag Analog button detection circuit
DE102004063198A1 (en) * 2004-12-23 2006-07-13 Atmel Germany Gmbh Driver circuit, in particular for laser diodes and method for providing a drive pulse train
DE102004063198B4 (en) * 2004-12-23 2009-04-30 Atmel Germany Gmbh Driver circuit, in particular for laser diodes and method for providing a drive pulse train
DE102011052895B4 (en) * 2010-08-24 2017-05-18 Infineon Technologies Ag Digital waveform synthesis

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Legal Events

Date Code Title Description
R207 Utility model specification

Effective date: 19960808

R150 Term of protection extended to 6 years

Effective date: 19980714

R151 Term of protection extended to 8 years

Effective date: 20010719

R152 Term of protection extended to 10 years

Effective date: 20030731

R071 Expiry of right