DE2949787A1 - CACHE STORAGE UNIT FOR USE IN CONNECTION WITH A DATA PROCESSING UNIT - Google Patents

Description

DIPL. ING. HEINZ BARDEHLE Munich, December 1979

PATENT ADVOCATE Λ (I

• 3V 2949767

File number: My reference: P 2996

Honeywell Information Systems Inc. 200 Smith Street Waltham, Mass., V. St. v. A.

Cache storage device for use in Connection to a data processing unit

030024/0883

P 2996

description

The invention relates to data processing systems and, more particularly, to a data processing system including a notepad storage unit designated cache storage unit that handles requests for instructions and operands relieved.

It is known per se that many data processing systems each have a main memory and one in the following only contain notepad storage unit referred to as the cache storage unit, which is located between the Data processing unit of the system in question and the main memory is provided and their purpose therein exists to increase the performance of such a data processing unit. In addition, are Such high-performance data processing units have been provided with instruction buffers in order for a fast Provide access to commands.

It has been recognized that even with the use of a cache memory unit and an instruction buffer, the Performance of the data processing unit represents a compromise through the transition from one command sequence to a second command sequence. To overcome this a known system includes an instruction buffer which is able to store two instruction sequences which are used for the Use by the data processing unit can be available. More information regarding this Systems can be found elsewhere (see US patent application dated December 30, 1977, Serial Nor. 866 083).

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Although the above arrangement facilitates the transition from one instruction sequence to another instruction sequence, it nevertheless requires that the execution of the call or the fetching of the Commands of the command defining a sequence must be completed before the command for calling or fetching Commands of a second sequence is issued to the main memory. During the period in question, the Processor unit or processing unit to stop their operation. The cache device relies on loading all commands of a block in the command buffer the processing unit in parallel with the issuance of the next command to fetch a second block of commands in operation.

Even in the event that it would be possible to use the above sequence of instructions for calling first and second blocks of information successively without the To interrupt operation of the processing unit, it would still be necessary to stop the operations as long as until the execution of the two commands has been completed before another command to the Call of instructions is issued.

In either case, there would be a significant degradation in the performance of the processing unit.

The invention is accordingly based on the object of creating an improved cache memory system.

A cache memory arrangement is also intended to be provided which allows a high degree of overlap of commands Specify instruction blocks from a main memory.

The object indicated above is achieved by the

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Invention as set forth in the claims.

According to the present invention is a cache memory unit for use in connection with a data processing unit created, with a faster access to by the cache memory unit in question Data and instruction words are retrieved from a main memory connected to the cache memory unit in response to commands received by the data processing unit. These Cache memory unit comprises an instruction buffer with a plurality of addressable memory locations, the serve to store sequences of command words. Also is a bistable command indicator provided, which is used to store a group of ads, the number of which is at least the maximum Corresponds to the number of read commands that can be processed at any point in time. Furthermore is a control device is provided with a display device, with the processing unit and the Command buffer is connected and which is operated on the occurrence of each specific read command in such a way, that it generates signals for switching one of the displays of the group associated with the particular type of read command is, the switching from a first state to a second state simultaneously with the Switching the other displays or display devices of the group in question takes place in the first state. The ads control the relevant Control device in such a way that the BefehXspuffer is released to only those command words that have been transferred to the cache memory unit. The registered mail takes place on the occurrence of a last command of the specific read command type.

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The invention also includes a cache memory unit for use in connection with a data processing unit created to provide quick access to data and commands from a Main memory connected to the cache memory unit concerned .., whereby the fetching takes place in response to commands that are received by the data processing unit. The cache memory unit in question comprises instruction address register means having a number of bit positions for Storage of an address of a next command word which can be accessed by the data processing unit he follows. An instruction buffer connected to main memory is also provided and has a number of sections or areas, each of which has a plurality of addressable memory locations for storing a Has sequence of command words. Each memory location has a large number of bit positions that serve to store a command word. In addition, at least one further bit position is provided which is switched in such a way that it switches from a first state to a second state when a command word is written into the relevant memory location. With the instruction address register facility, the Processing unit and the command buffer is connected to a control device that responds to the occurrence a signal corresponding to the second state from the relevant one bit position of one of the memory locations generates an output signal for the processing unit in the event that it is determined that the next instruction word designated by the instruction register device and stored in one of the buffer storage locations of one area has been enrolled.

According to a preferred embodiment, the cache memory unit contains a cache memory which is in a Multitude of levels is organized, each of which is used for

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Storage of a number of information blocks in the form of data and commands is used. The cache pech unit also includes a control arrangement, an instruction buffer for storing instructions from the Main memory are included, and a transit block buffer, which contains a large number of storage locations Having storage of commands of the read type.

The control arrangement has a plurality of groups of bit storage elements, the number of which the number which corresponds to transit block buffer locations. In the preferred embodiment, each group comprises one Pair of instruction fetch flag display storage circuits, those with the command buffer for controlling the writing of command blocks in the relevant Buffers are effectively connected. Specifically, each is a different pair of the pairs of instruction fetch flag display memory circuits retrieving first and second groups, half-blocks or blocks of information associated.

Normally, as a result of a branch or transfer, each time a read-type instruction - which designates the retrieval of either a first block or a second block of commands - from the Processing unit is included - with the relevant block as command call 1 (IF1J or as Command call 2 (IF2j is designated - one of the Command fetch flags attached to the transit block buffer space to which the instruction of the read type has been loaded into the binary state 1 set. Corresponding command call indicator displays, which belong to the other memory locations, which belong to the main memory before Save transferred commands IF1 / IF2 are reset to the binary states 0.

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Accordingly, the instruction buffer becomes through the states of instruction fetch flags are controlled so that only those Instructions are loaded, which are taken from the main memory, on the last IF1 / IF2 instruction there. Accordingly, there is no conflict with old blocks of instructions received from main memory have been recorded after a new IF1 / IF2 command has been issued, since the command call-up flags indicate which enable the writing of the commands of the old block in the command buffer, automatically set to zero or deleted when the license plate display on the occurrence of the new Command has been set. As a result, the commands are transferred to the processing unit will.

In the preferred embodiment, the groups of bit storage elements include a cache write flag indicator, which belongs to the respective transit block storage location and which is normally in the binary state 1 is set, which causes the memory information to be written into the cache memory will. In accordance with the binary state of the cache write flag indicator, the commands called upon the occurrence of the new IF1 / IF2 command as well as the commands of the old block in written to the cache regardless of the instruction fetch flag states.

In accordance with the teachings of the present invention, when the transfer or branch instruction - the through the processing unit that generated the IF1 / IF2 command is executed - is a stop command (NOGO), prevented the command from changing the command fetch flag displays. In addition, the cache memory unit can a new IF1 / IF2 command for the respective

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Time to submit without the operations of the processing unit stop until the previous IF1 / IF2 command has finished executing.

Accordingly, the arrangement of the preferred embodiment of the present invention enables a significant amount Overlap with regard to the processing of IF1 / IF2 commands without affecting the completeness of the commands, which are written into the command buffer despite the occurrence of commands of the old ones Blocks following the previous IF1 / IF2 commands. This is the performance of the system in terms of the processing of transfer or branch instructions increased to from an instruction stream or from an instruction sequence to switch to another command sequence.

The cache memory unit instruction buffer has first and second areas for storing first and second instruction blocks, respectively, which are received from the main memory will.

Each instruction buffer area contains a plurality of word storage locations, each of which has a number of bit positions having. A specific bit position of each word memory location is used to provide a display to be supplied when a command word is written into the memory location. The one with the respective buffer storage area the control arrangement connected to the buffer memory area is operated in such a way that all word memory locations including the specific bit positions in binary states 0 are then reset if the A command requesting a command block from the main memory is ready for transmission the main memory.

As soon as a command word is in a word memory location of the Is written into the buffer memory area, the

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corresponding bit position switched to binary state 1. The ones contained in the control arrangement Command buffer standby circuits are activated by the states of the specific bit positions of the memory locations causes an output signal for the processing unit to generate in order to enable the transmission of the requested instruction words to the processing unit, as soon as they are received from the main memory. This means in detail that the preferred Embodiment of the cache memory unit has at least one instruction address register with a number of bit positions which are used to store address signals indicating the address of the next command denote to be fetched from the cache storage unit.

A comparator circuit provided within the control arrangement serves to receive the address signals from the instruction address register. Set these address signals determines which command word is to be transmitted within the block. Signaling is also carried out accordingly the states of the specific bit positions of the command buffer areas. In accordance with the These circuits generate states of the specific bit positions within the instruction buffer area Output signal by which the command readiness circuits are caused to transmit a to release such next command word to the processing unit when the word in question in one of the command buffer area locations is written. Accordingly, it does not matter in which order the command words are sent out; the processing unit is able to execute the instruction as soon as it has taken up the command in question. This leads to an increased efficiency.

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The invention is explained in more detail below with reference to drawings, for example.

1 shows the principles in a block diagram System employing the present invention. FIG. 2 shows in a block diagram one in the system according to FIG Fig. 1 provided main processor and a cache memory unit.

FIGS. 3a to 3e show in detail the elements shown in FIG illustrated blocks.

FIG. 4 shows the cache memory unit shown in FIG. 2 in a block diagram.

Fig. 5 shows in detail a cache memory processor section steep device.

Figure 6a illustrates the format of the control store controller of the system of Fig. 1. Fig. 6b illustrates the format of microinstruction words of a flow control memory of Figs. Figures 7a through 7e illustrate in detail different areas of the cache memory unit.

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As can be seen from Figure 1, the system embodying the principles of the present invention has at least an input / output processor 200, a system interface unit 100, one at high speed multiplexer 300 operating at low speed, multiplexer 400 operating at low speed Main processor 700, a cache memory or scratch pad memory 750 and at least one memory module, respectively a local memory module 500 and at least one memory module corresponding to a memory module 800 on. The various modules are with a number of connections of the system interface unit connected via a plurality of lines of different types of interface devices 600 to 604. Specifically, the input / output processor 200, the cache memory 750, and the high speed one operating multiplexers 300 connected to ports G, E and A, respectively, while the low speed operating multiplexer 400, the local memory module 500 and the main memory module 800 with the connections J, LMO or RMO are connected. The main processor 700 is connected to the cache memory 750.

The system interface devices are explained below. Before the processor 700 and the cache storage unit 750 that are constructed in accordance with the principles of the present invention are, the interface devices to 604 are considered first.

The data interface device 600 is one of the interface devices which are used for an information exchange between an active module and the system interface unit 100. The exchange of information is caused by the fact that the link states of different signal lines are in agreement can be controlled with predetermined rules, which are controlled by a

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Sequence of signals are executed, which are referred to as "dialog".

The interface device 601 is a programmable interface device which is used for command information transmission from an active module to a designated module. The transmission is thereby causes the link states of the various signal lines in accordance with before specified rules, which are executed by a sequence of signals, which is referred to as "dialogue".

Another interface device is the interrupt interface device 602 for interrupt processing by the input / output processor 200 cares. This means that the interface device enables the transmission of interruption information through an active module of the system interface unit 100 to the input / output processor 200 for processing purposes. In appropriate In a manner related to the other interface device, the transmission of interrupt requests is carried out in that the link states the various signal lines are controlled in accordance with predetermined rules, carried out by a sequence of signals called "dialog".

A next series of interface lines used by certain modules of FIG. 1 corresponds the local memory interface device 603. This interface device ensures an exchange of information between the local memory 500 and the modules of the system. The exchange of information is thereby causes the link states of the various signal interface lines to correspond

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can be controlled with predetermined rules that are executed by a dialog sequence of signals.

The memory and the programmable interface commands are from the same physical data lines transmitted to the interface device. The interface device does not include a number of Lines for processing interrupt requests, which is why the over the system interface unit 100 modules connected to the local storage do not directly cause a storage interruption can.

For a detailed description of the elements of the system shown in FIG. 1 and the interface devices 600 to 603 is referred to the US-PS 40 06 466.

The final interface device 604 is an internal interface device that connects between the Cache memory unit 750 and the central processor is provided. This corresponds to the cache memory / central unit interface lines according to FIG. 5. This interface device ensures the exchange of information and the exchange of control signals between the processor 700 and the cache memory unit 750. The The relevant signal exchange is brought about by the link states of the various signal interface lines being controlled. The cache / central processing unit interface means includes one A large number of data for the processor lines (ZDI 0-35 »P0-P3), a large number of ZAC and write data lines (ZADO 0-23, RAD024-35, P0-P3), a processor request signal line (DREQ-CAC), a plurality of cache memory command lines (DMEM 0-3), a hold cache memory line (HOLD-C-CU), a delete line

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(CANCEL-C), a transfer line (CAC-FLUSH), a read word line (RD-EVEN), a read command buffer line (RD-IBUF), a double read line (FRD-DBLE), an odd line (FODD), a variety of Command lines (ZIBO-35, P0-P3), a control line (DSZ), a read I buffer data line (RD-IBUF / ZDI), a plurality of zone bit lines (DZD 0-3), a bypass cache memory line (BYP-CAC), a write signal line (WRT-SGN), a command buffer empty line (IBUF-EMPTY), a command buffer ready line (IBUF-RDY),

a CP stop line (CP STOP), a CP control line (DATA-RECOV), a descriptor control line (FPIM-EIS), a transfer stop line (NO-GO) and a variety of Ifcrt address lines (ZPTRORTO-1).

The instructions, cache memory commands and data are provided to the cache memory unit 750 via various means Lines of these lines fed. In addition, the operation of the processor 700 is certain Lines of these lines released or blocked, as will be explained below. Below will be the central processing unit / cache interface lines are described in detail.

Central processing unit / cache memory interface lines

Name Description

DREQ-CAC This line runs from the

Processor 700 to the cache storage unit 750 there. If the DREQ-CAC line carries a binary signal 1, then a ZAC command is issued over to the cache memory 750 wear. In the event of a write ZAC command, write data words in the one

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or the two cycles following the ZAC command, and Data words are transferred from the processor 700 to the system interface unit via the cache memory 750 without modification 100 transferred.

DMEMO, 1,2,3 These lines run from the

Processor 700 to the cache memory. These lines are encoded to identify the instruction that the cache memory 750 is to execute. The following coding is provided: DMEM = OOOO - no operation, no action is taken and no cache memory request is made.
DMEM = 0001 - direct - the direct instruction enables processor 700 to perform a direct transfer of an operand value without affecting the cache 750 portion. This means that no cache memory request is generated by this type of instruction.
DMEM = 0010 - Address Command in Cyclic Address Sequence (ADD-WRAP): This command is executed to return to the command given to cache memory 750 by processor 700. In the same cycle, the command is issued to processor 700 over ZDI lines 0-35.

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DMEM = 0100 - Loading the command buffer, command call 1 (LD-IBUF-IFI ;: The load command buffer command is used to put the address of the next block of instructions in the other register RICA / RICB to load.

There are three possible operational sequences for this command. 1. In the event of a cache change are then bypassed if the cache memory 750 is not the block address stored in the cache memory and that stored in this memory Level loaded into the other command register. A cache access is then made to invoke the desired instruction which is sent to processor 700 via the ZDl lines 0-35 on the occurrence of the following T clock pulse is transferred out. The other command register now becomes the command register used.

2. In the case of cache misses, that is, when the cache memory 750 is not bypassed by the bypass circuits designated block address and the plane designated by the designated circuits in the other command register loaded. The processor is shut down or upon the occurrence of the following T clock pulse held on

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to determine whether the generation of the IF1 instruction is on a Transfer command issued. If this is the case and if the transfer command is a stop command

then the command register currently being used is used to to access the next instruction and processor 700 is turned on. If the IF1 command by a transfer or Transfer order issued which is a GO instruction, then cache 750 sends a memory request to the system interface unit 100 regarding the desired block of information off, and an address list assignment is made with respect to the missing block. the Instructions received from the memory are first written into the instruction buffer and then into the cache. The requested command is made to processor 700 over the ZDI lines and processor 700 will respond to the occurrence of the following T clock pulse switched on or triggered. The remaining commands in the block are from the instruction buffer over the ZIB lines to the processor transferred to.

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3. If the cache is to be bypassed, there is a hit or change signal Full / empty bit is reset for the relevant block. All other operations are identical to the operations of the fallback case, apart from the fact that that no address list assignment is made and that the block is not written into the cache will.

DMEM = 0101 - Load the command buffer - Command call 2 (LD-IBUF-IF2): The load command buffer command is used for this purpose, the level of the second block of commands in the command register currently in use to load. The processor 700 is not shut down in the event of an evasive condition. There are also three possible operational consequences for this command exist.

1. In the case of a cache, save before r-hit status and if there is no bypass, the level of the second block of instructions becomes the one currently in use Command register loaded.

2. In the event of a cache bypass condition and if it exists no bypass is made in the event that the IF1 instruction is the result of a transfer instruction stop condition has been determined, the IF1 operation is deleted. In another case as a stop condition, a

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Address list assignment with regard to the second block of commands made, and the plane obtained from the recirculation circuits becomes the one just used Command register written. The cache memory 750 sends a memory request to the Memory related to the block. When the commands are recorded, they are first entered in the Instruction buffer and later written into cache memory 750. When the commands are needed they are read from the command buffer and sent to the processor 700 via the ZIB lines 0-35 transferred to.

3. in the case of a bypass or a bypass, in the case that a hit or change status is present, the full / empty bit for the relevant Block reset. All other operations are the same as those in the case of cache bypass except that there is no address list assignment and that the block is not in the Cache memory 750 is written.

DMEM = 0110 - Load a four-way instruction: The loading of a four-way instruction is used to transfer the block address for data (not

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Commands) into the other command register. This process is similar to the process of occurrence of the signal IF2, apart from the fact that the address and the level (circulation circuits provide the level when a cache miss condition present) can be written into the other command register. If the data is not in the cache 750 are included and when the processor 700 requests this data before going out have been recorded in memory, then the processor is paused or shut down until the data are recorded.

DMEM = OI11 - pre-read (PR-RD): The pre-read command will do so is used to load the cache memory with the data that the processor 700 is ready to use expected in the near future. There are three possible operational sequences as follows available:

1. On a cache hit and there is no bypass the readout command is executed as a no-operation command.

2. If there is a cache escape signal and there is no bypass , cache 750 generates one

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Memory request with respect to the block, and also an address list allocation with respect to of the missing block. When the data is recorded from the memory they are written into the cache memory. The processor 700 is referring to this state of affairs held. 3. If the cache is bypassed, the read command treated as a no-operation command.

DMEM = IOOO - single read command (RD-SNG): The single read command is used to transfer a single data word to the processor 700. There are four possible operational sequences for this command.

1. In the event of a cache memory hit and the addressed word is read from cache 750 without bypassing and on the occurrence of the next T clock pulse over the ZDI lines 0-35 to processor 700.

2. In the event of a cache evasion and there is no bypass, the processor will 700 is paused and the missing block is stored in the

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Address list. The cache memory 750 transfers the memory request to the Main memory. The data words are written into the cache memory when they are included. When the requested data word is received, the Processor 700 for the occurrence of the following T clock pulse turned on.

3. In the event of a cache hit and bypass, the full / empty bit of the addressed block is reset and processor 700 is shut down or held. The cache memory 750 transfers the request for a word to memory and the processor 700 is triggered on the occurrence of the following T clock pulse switched on, namely on the inclusion of the requested data word. The data word is not written to cache 750.

4. In the event of a cache evasion and bypass, the same operations occur as if the cache hit was present and a bypass, apart from the fact that the full / empty bit of the addressed block is not will be changed.

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DMEM = I001 - delete read command (RD-CLKj:

The delete read command or read delete command is used to to transfer a data word from the memory to the processor 700 and also this data word from the relevant Clear memory. There are two possible operational sequences related to this command available,

1. On a cache hit the full / empty bit for that block is reset and processor 700 is shut down. The cache memory 750 executes a memory request for a data word. The memory deletes the relevant memory location. When the word is recorded, broadcast the cache memory 750 sends the word to the processor 700 and switches the processor 700 on the next T clock pulse. The word is not written into cache 750.

2. The same operations run in the event of a cache fallback as if there was a cache hit, however apart from the fact that the full / empty bits of the addressed block are not changed.

DMEM = 1010 - Read double command (RD-DBL): The read double command is used for this

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drawn to transfer two data words to processor 700. There are two types of Double read commands that differ in the order in which the data words are sent to the processor 700 are fed. If the line DSZ1 carries a binary signal "0", then it is Order given by an odd word and an even word. If the Line DSZ1 carries a binary signal "1", then the sequence is given by an even number Word and then by the occurrence of an odd word. There are four possible Operating sequences for this command.

1. On a cache hit and lack of bypass, the first word is passed to processor 700 over the ZDI lines 0-35 transmitted when the following T clock pulse occurs. Upon the occurrence of the next T clock pulse, the second data word is over transmit ZDI lines 0-35 to processor 700.

2. If there is a cache evasion and there is no bypass, processor 700 is turned off and an address list assignment is made regarding

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of the block containing the addressed word pair. The cache memory 750 transmits the memory request to the system interface unit 100 with respect to of the block. When the data words are recorded they are cached enrolled. If the requested word pair is available, the first word becomes the Processor 700 transferred to the occurrence of the following T clock pulse is switched on or triggered. The cache memory 750 transmits the second word to processor 700 upon the occurrence of the next T clock pulse there.

5. If there is a cache hit and a bypass, the full / empty bit becomes of the addressed block is reset and processor 700 is shut down. The cache 750 is transferring the request for the two data words to the memory. As soon as the two Words are available, processor 700 is turned on and the first word of data becomes this Processor for the occurrence of the following T clock pulse

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fed. The processor 700 takes the second data word upon the occurrence of the next T clock pulse out. the Data words are not written into the cache. 4. In the event of a cache evasion and a bypass run the same operations as in the case of a cache hit and a workaround, apart from the fact that there is no change in the full / empty bits he follows.

DMEM = 1011 - Remote read command (RD-RI-IT): The remote read command is used for normal cache reads to bypass. When the command is received, processor 700 is shut down, and the request is transferred to main memory. If that requested word pair is fetched from the memory, then the processor 700 is the first word fed to the occurrence of the subsequent T clock pulse is switched on. The second data word is sent to the processor 700 fed upon the occurrence of the next T clock pulse. the The order in which the data words are transmitted is such that first an odd-numbered word and then an even word

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appear. There are none within the cache 750 Changes.

DMEM = HOO - single write command (WRT-SNG):

The single write command is used to write data into memory to enroll. There are two possible operational sequences in relation to this this command.

1. On a cache hit, cache 750 transfers the request to the store. If this request is accepted, the data word becomes transferred to the memory. The data word is also written into cache memory 750.

2. The same operations run in the event of a cache fallback as with a cache hit, except that none Change to cache memory 750 occurred.

DMEM = I110 - double write command (WRT-DBL):

The double write command is used to write two data words into the memory. This command is executed in a similar way to the single write command, except that two words are transferred / written instead of one word.
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HOLD-C-CU CANCEL-C CAC-FLUSH

DMEM = H 11 - Remote write command (WRT-RMT):

The remote write command is used to perform normal cache memory writes to bypass, in that if the addressed words are in the cache memory 750 exist, these words are not updated. The cache memory 750 transmits the Request to the memory, and if it is accepted there, two data words become the Transfer to memory. This line runs from processor 700 to the cache memory 750 there. If this line carries a binary signal 1, then this control signal specifies that the cache 750 as on HOLD for requests or data transfers is to be assumed. This line runs from processor 700 to cache memory 750. If this line is a binary signal 1, the relevant control signal indicates that the cache memory 750 has any Should ignore the processor command that is currently being executed.

This line runs from the processor 700 to the cache memory 750. If this line carries a binary signal 1, a

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RD-EVEN

ZADO 0-23 RADO 24-35, P0-P3

The cache 750 pass started (this means that the cache 750 is in a in which it appears empty by resetting all full / empty bits will).

This line runs from the processor 700 to the cache memory 750. When the cache makes a double word request to the system interface unit, then the even word in kept in a special register (REVN). If the line RD-EVEN carries a binary signal 1, then the content of the REVN register is transmitted via the ZDIN switch delivered to the ZDI lines.

These forty unidirectional lines extend from processor 700 to cache 750. The lines in question are used to transfer ZAC commands and write data words to the cache memory 750 . If the line DREQ CAC carries a binary signal 1 , the ZAC command and, in the case of a write command, the write data words are transmitted during one or two cycles in response to the ZAC command. The coded commands occurring on the DMEM lines

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can be the same commands as the ZAC command.

RD-IBUF This line runs from the Pro

processor 700 to the cache memory 750. If this line carries a binary signal 1, then shows this line indicates that the processor 700 is receiving the instruction from the instruction register RIRA. In most cases, the relevant command is used to pick up the next instruction to be loaded into register RIRA.

DZD 0-3 These four lines mainly from

the processor 700 to the cache memory 750. You transfer Zone bit signals of the odd word related to the double write commands .

BYP-CAC This line runs from the

Processor 700 to cache memory 750. If they are a binary signal 1 then causes the cache memory 750 to read data words to request read commands from the main memory. When a cache hit occurs, the block containing the requested data is retrieved from cache 750 led out by resetting the associated full / empty bit will. With regard to the single write or double write commands, the data in the Cache memory 750 written in »

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WRT-SGN

FPIM-EIS DSZ1

NO-GO

when a cache hit occurs.

This line runs from the cache memory 750 to the processor 700. It is used to signal the processor 700 during the write commands that the cache memory 750 has completed the transmission of the ZAC commands and data words to the system interface unit 100. This line runs from the processor 700 to the cache memory 750. If it carries a binary signal 1, the cache memory 750 is signaled that the processor 700 is issuing an IF1 instruction for additional EIS descriptors.
This line runs from the processor 700 to the cache memory 750. The state of this line determines for the cache memory 750 the order in which the words are to be sent to the processor 700 when a double read instruction is executed.

This line runs from the processor 700 to the cache memory 750. If they are a binary signal 1 leads, this indicates that the processor 700 is executing a transfer command, which is a NO-GO command. This causes the cache memory

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RD-IBUF / ZDI

FRD-DBL FODD

signals that he should delete the IF1 command he was in And that the IF2 command should also be ignored, which is currently being delivered to the DMEM lines.

This line runs from the processor 700 to the cache memory there. It causes the cache memory 750 to access the data word at the address contained in the other instruction register and this Transmits data to the ZDI lines. In view of a pending LDQAD instruction, cache memory 750 halts processor 700, when the RD-IBUF / ZDI line carries a binary signal 1. This line runs from the processor 700 to the cache memory 750. She signals that Cache 750 in advance that processor 700 is requesting a double read operation.

This line runs from the processor 700 to the cache memory 750 there. It is used in conjunction with the FRD-DBLE line to to signal the order of the requested words. If this line carries a binary signal 1, this indicates that the order is odd - even.

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ZDI 0-35 These forty lines, the signal P0, P1, P2, P3 Ie transmitted in one direction,

run from cache 750 to the processor 700. They indicate data from the cache memory 750 the processor 700.

ZIB 0-35 These forty lines, the signa- P0, P1, P2, P3 Ie transmitted in one direction,

run from cache memory 750 to processor 700. they give Commands to processor 700. BUF-EMPTY This line runs from the

Cache 750 to processor 700. If it carries a binary signal 1, this indicates that the Cache memory 750 has transferred the last instruction from the present instruction block.

BUF-RDY This line runs from the cache

store 750 to processor 700. If it carries a binary signal 1, this indicates that there is at least one instruction in the cache 750 in the present instruction block. The appearance of a Binary signal 0 on this line indicates a non-ready state

1. if the command address

of an IF1 block in the cache memory on the first instruction of an IF2 block that is not in the cache memory and is not contained in the IBUF2 buffer,

2. and if commands from the IBUF1 buffer or from the IBUF2 buffer

OÖ0Q24 / QÖ83

BUF-FULL

CP STOP

and when the next command to be called is in a two-word buffer is which has not been picked up by the memory.

This line runs from the cache memory 750 to the processor 700. It indicates that there are at least four commands in the present command block or that there are at least one command and an outstanding IF2 request. This line runs from the cache memory 750 to the processor 700. When it is at a binary 1, it indicates that the processor 700 is halted or requires a wait or halt state in its operation. In the event of a read evasive condition as a result of a processor command, the processor is held in response to the subsequently occurring T clock cycle pulse. When the processor is triggered, the DATA RECOV line carries a binary signal 1, which means that the processor registers concerned are scanned again. If the line RDIBUF / ZDI carries a binary signal 1 before the data is received from the memory, then the processor 700 is held before the T-clock pulse which then occurs. If it is drawn, it will be

090024/0883

DATA-RECOV ZPTR-OUT 0-1 the requested data for the processor 700 on the ZDI lines made available and used on the subsequently occurring T clock pulse. This line runs from the cache memory 750 to the processor 700. It is used to to scan the processor registers again after the processor 700 has been shut down, and to the determination of a cache memory backup state or a read bypass condition. At the end of the cycle within which on the line DREQ CAC a binary signal 1 occurs, the evasive state is determined, with however, processor 700 cannot shut down until after the following occurs T clock pulse. Accordingly, bad data / instructions are put into the processor registers keyed in from the ZDI / ZIB lines. If the requested data / commands are available a binary signal 1 is sent to the DATA RECOV line in order to scan the registers again, scanned during the last cache request.

These two lines run from the cache memory 750 to the processor 700. You lead signals encoded in such a way that the

030024/0803

--T9-,

the two least significant bits of the address of the command that is in the RIRA command register or in the I buffer is included.

The following describes the processor 700 according to FIG. 2 in general. As can be seen from Fig. 2, the comprises Main processor 700, a sequence control unit 701, a Control unit 704, a sequence or execution unit 714, a drawing unit 720, an auxiliary arithmetic and control unit 722 and a multiplication / division unit 728. These units are connected to one another in the manner shown in FIG. The control unit 704 also has a number of connections to cache storage unit 750, as shown is.

The sequence control unit 701 comprises an execution control store address preparation and branching unit 701-1 and a sequence control memory 701-2. The memory 701-2 and the unit 701-1 are as over Bus lines 701-3 and 701-6 are shown interconnected.

The control unit 704 has a control logic unit 704-1, a control memory 704-2, an address preparation

OÄDO 2 4/0 8.8 3

unit 704-3 »data and address output circuits 704-4 and an XAQ register area 704-5, which is marked with connected to the units concerned in the manner that can be seen.

As can be seen from FIG. 2, leads from the system interface unit 600 a number of input lines to the cache memory unit 750. The lines this interface device have been described in detail above. In connection with the operation of the It should be noted, however, that certain of these lines in the cache memory unit 750 are identified below Way carry specially coded signals.

1. MITS 0-3 for read processes are coded as follows: Bits 0-1 «00,

Bits 2-3 = transit block buffer address containing the ZAC command for the present read operation. For the write operation, bits 0-3 ^{β are} odd word zones.

2. MIPS lines carry the following coded signals: Bit 0 - 0,

Bit 1 = 0, even word pairs (words 0, 1) Bit 1 * 1 odd word pairs (words 2, 3) Bits 2-3 = transit block buffer address that contains the ZAC command for the received data.

With regard to the interface lines DPS 00-35, P0-P3, it should be noted that these lines provide read data to the Run cache memory unit 750 there. The lines DTS 00-35, P0-P3 are used to Data from cache memory 750 to the system interface unit 100 to be transferred.

The control unit 704 takes the necessary control to execute address preparation operations, command · -

090024/0883

call / execution operations and with regard to the sequential control of the various operating cycles and / or Machine states. Control is through logic circuits of block 704-1 and through the Sequence control unit 701 is carried out with respect to the various parts of control unit 704.

The XAQ register area 704-5 comprises a number of Visual program registers such as index registers, an accumulator register and a quotient register. Other visual program registers, such as the instruction counter and address register, are included in the address preparation unit 704-3.

As can be seen from Fig. 2, the area 704-5 receives signals from the unit 704-3 which are characteristic of the Contents of the command counter. These signals arrive on lines RIC 00-17. Also, over the lines ZRESA 00-35 output signals from the execution unit 714. These signals correspond to the results the operations performed on the various operands. The area 704-5 also receives an output signal from the help computing and control unit supplied via the lines RAAUO-8.

The area 704-5 outputs signals which are indicative for the content of one of the registers provided within the relevant area. These signals are given as an input variable to the address preparation unit 704-3. The address preparation unit or address formation unit 704-3 routes the relevant information via a switch to the execution unit 714, namely via the lines ZDO 0-35 »in a corresponding manner the content of certain registers of the registers contained in the area 704-5 can be sent to the execution unit 714 via the Lines ZEB 00-35 can be transmitted. Finally, the contents of selected registers can be extracted from these registers from the

090024/0883

- φτ-

Area 704-5 to the multiply / divide unit 728 can be transmitted over the lines ZAQ 00-35.

The address preparation unit 704-3 generates addresses from the contents of the various Registers that are contained in the relevant unit and gives the resulting link signals, effective addresses and / or absolute addresses for distribution to the other units via lines ASFA 00-35. The address formation unit 704-3 receives the results of the operations performed by the execution unit 714 on two operands are. These result signals are transmitted over the lines ZRESB 00-35 added. The unit 704-3 receives signals which are indicative of the content two base pointer registers from control logic unit 704 via lines RBASA and RBASBO-1. The output signals of the multiplication / division unit 728 are delivered to the address generation unit 704-3. Eventually the contents of a secondary instruction register become (RSIR) as an input signal via the lines RSIR 00-35 to the unit 704-13.

The data and address output circuits 704-4 generate the cache address signals transmitted over the lines RADO / ZADO 00-35 to the cache memory unit be delivered. These address signals correspond to the signals applied to an input line of the series of Input lines ZDI 00-35, ASFA 00-35 and ZRESB 00-35 are issued. The relevant lines selected by switches included in the circuits of block 704-4. These circuits are will be explained in detail below.

The control logic unit 704-1 provides data paths that interface with the various

Have units soft in the cache storage unit 750 are included. As described in detail here, the lines ZIB 00-35 provide an interface to an instruction buffer contained in cache memory 750. The lines ZDI 00-35 are used for this used to transfer data signals from the cache memory 750 to the control logic unit 704-1. the ZPTROUT lines are used to transfer address information from the cache memory 750 to the Unit 704-1 to be transferred. Other signals are cut over the other data and control lines of the cache memory central processor Job facility submitted. These lines include the line CP-STOP shown separately in FIG.

As from Flg. 2, control logic unit 704-1 provides a number of groups of output signals. These Output signals include the contents of certain registers, such as a basic instruction register (RBIR), its content as input variable to the control store 704-2 is supplied via lines RBIR 18-27. The control logic unit 704-1 receives certain control signals that are read out from the control memory 704-2 and via the Lines CCSDO 13-31 can be transmitted.

The control logic unit 704-1 also includes a secondary Command register (RSIR), which is loaded in parallel with the basic command register at the beginning of command processing will. The content of the secondary command register RSIR 00-35 is, as mentioned above, the input variable of the address formation unit 704-3 supplied. In addition, part of the content of the secondary command register is used as an input variable the auxiliary arithmetic control unit 722 over the lines RSIR 1-9 and 24-35 fed.

As explained here, the control store 704-2 has the effect of an initial decoding of program instruction operation

03O02A / 0883

codes, which is why it is designed to have a number of memory locations ^ 1024), one for each possible instruction opcode.

As already mentioned, the signals provided on lines RBIR 18-27 are used as input signals Control store 704-2 supplied. These signals select one of the 1024 possible memory locations. The content of the selected memory location is transferred to lines CCSDO 13-31 and CCSDO 00-12, as can be seen from FIG. The signals sent to the lines CCSDO 00-12 correspond to the Address signals that are used to address the sequence control unit 701, as explained here will.

The remaining portions of the processor 700 will now be briefly described. The execution unit 714 ensures an instruction flow, in the course of which the unit 714 executes arithmetic and / or shift operations on operands that are selected from the various input variables. The results of such operations are fed to selected outputs. The execution unit 714 receives data from a data input bus line corresponding to lines RDI 00-35. The source of this data is control logic unit 704-1. The contents of the accumulator and quotient registers contained in the area 704-5 are output to the execution unit 714 via the aforementioned lines ZEB 00-35. The signals delivered to the input bus lines ZDO 00-35 by the address generation unit 704-3 are delivered via switches aXe contained in the sequence unit 714 to the lines ZRESA 00-35 and ZRESB 00-35 shown in FIG. In addition, the execution unit 714 receives a series of notepad memory address signals from the auxiliary computing and control unit 722, which signals are transmitted via the lines ZRSPA 00-06

030024/0883

moreover, the unit 722 is a Displacement information via the lines ZRSC 00-35 to the unit 714.

The drawing unit 720 is used to execute drawing commands that require such operations, like the translation and preparation of data fields. As explained here, these types of instructions are referred to as Extended Instruction Set (EIS) instructions. Such Instructions that the drawing engine 720 executes include the transmit, scan, and compare instructions. Signals, which are characteristic of operands are via the Lines ZRESA 00-35 released. Information regarding the type of character position within a word and with regard to the number of bits are output to the character unit 720 via the input lines ZDB 00-07.

Information that is indicative of the results of certain data operations is transmitted over the lines ZOC 00-08 delivered to unit 722. Such information includes exponent data and data in hexadecimal form. The drawing unit 720 outputs output operand data and control information to the Unit 722 or to unit 728 via the lines RCHU 00-35.

The auxiliary arithmetic and control unit 722 performs arithmetic operations in response to control information, as shown in FIG Exponents used in floating point operations. In addition, the relevant unit calculates operand lengths and pointers and generates counting information. The results of these operations are reported via the lines ZRSPA 00-06 and via the lines ZRSC 00-06, which have been mentioned above to the drain unit 714 submitted. The information signals that correspond to characters, such as 9-bit characters, 6-bit characters, decimal data converted from the input hexadecimal data,

030024/0883

Quotient information and sign information are sent to the area via lines RAAU 00-08 704-5 submitted.

As can be seen from Fig. 2, the unit 722 receives a number of input signals. The character pointer information is fed in via lines ASFA 33-36. An EIS numerical scale information as well Alphanumeric field length information is fed to the unit 722 via the lines RSIR 24-35. Further signals relating to the invocation of special commands are transmitted via lines RSIR 01-09 fed. The exponent signals for the floating point data are provided to unit 722 on lines ZOC 00-08, while floating point exponent data signals from unit 704-1 via lines RDI 00-08. Shift count information signals for the various commands (e.g. binary shift commands) are sent to the unit via the Lines RDI 11-17 released. With regard to the input signals on lines RCHU 00-35 it should be noted that lines 24-35 carry signals corresponding to the length of the EIS command fields, while lines 18-23 carry address modification signals to the unit 722.

The last unit is the multiplication / division unit 728, which is used for quick execution of multiplication and division orders. This unit can be of conventional construction and, for example be designed in the form of the multiplication unit described in US Pat. No. 4,041,292. The indicated in Fig. 2 unit 728 takes over the lines RCHU 00-35 multiplier, dividend and Divisor input signals. The multiplicand inputs from register area 704-5 are via the lines ZAQ 00-35 are supplied. The results of the

030024/0883

Computation processes carried out by the unit 728 are sent as output signals to the lines ZMD 00-35 submitted.

As mentioned earlier, the cache unit 750 transmits data and control signals to the system interface unit 100 and takes such signals from this unit over the data interface line on. Cache unit 750 transmits and receives data and control signals to processor 700 Information from this processor over the lines of the interface device 604. Finally, the Cache memory unit 750 addresses and data signals from circuits 704-4 over lines RADO / ZADO 00-35 on.

Processor 700 will now be described in detail. Certain areas of the designated areas that make up the processor shown in FIG will now be described in detail with reference to FIGS. 3a to 3e.

Referring to Figures 3a and 3b, it can be seen that the processor has two control stores: (1) The control unit control store 704-200, which forms part of the control unit 704, and (2) the flow control memory 701-3, which is contained in the sequence control unit 701.

The cache oriented processor 700 includes at According to the preferred embodiment of the present invention, a three-stage so-called pipeline system. this means that processor 700 will require at least three processor cycles to process a given To terminate the program command, and that it can issue a new command start of this cycle. In order to can be the number of program instructions in a given processing stage at any given point in time are present.

030024/0883

According to the preferred embodiment, the processor 700 includes the following stages: an instruction cycle (I), in which a command evaluation, an operation code decoding and an address formation take place, a cache memory cycle (C) in which the cache memory unit 750 is accessed to ensure high performance operation, and an execution cycle (E) in which instruction execution takes place under a microprogram control.

With regard to the control, it should be noted that during the I cycle, the Qperationscode des over the lines

given command
RBIR 18 ^ 27 / is used for access to a memory location or to a memory location within the control memory 704-2. During a C cycle, the content that has been accessed in control memory 704-2 is output to lines CCS DO 00-12 and used for access to one of the storage locations in sequence control memory 701-2. During the C cycle, the microinstructions of the microprogram used to execute the instruction are read from the flow control memory 701-2 into a 144-bit output register 701-4. The signals labeled MEMDO 00-143 are distributed to the various functional units of the processor 700. During an E cycle, the processor performs the operation specified by the microinstruction.

With particular reference to Figure 2, it should be seen that control store 704-2 is a control unit control store 704-200 which is addressed by the opcode signals appearing on lines RBIR 18-27. The relevant control memory 704-200 comprises 1024 memory locations, the content of which during of an I operating cycle in an output register 704-202 is read. In Fig. 6a the format is schematic

OÖ002A / 0883

which illustrates words stored in control store 704-200.

From Fig. 6a it should be seen that each control unit control store word comprises five fields. The first field is a 13-bit field which is an ECS starting address location for the instruction for which an opcode is provided on lines RBIR 18-27. The next field is a 3-bit field (CCS0) which is used for Control of certain operations is used. The bit interpretations of the field depend on their destination and on it whether they are through certain logic circuits or can be decoded under microprogram control. The next field is a 4-bit field which specifies register control operations serves.

The next field is a 6-bit sequence control field or Sequence control field which is coded to designate a sequence of operations that are carried out under a hardware wired link control circuit as well as the cache memory operation. In the In the present embodiment, this field is encoded as 75g. The last field is a 6-bit display field, which is not important for understanding the present invention.

As can be seen from FIG. 3a, the CCSA field signals corresponding to a control unit control store word are output as input signals to the sequence generator circuits 701-7 via a connection path 704-204. The signals corresponding to the CCSR field are sent as input signals to the execution unit 714 via the connection path 704-206 submitted. In addition, the same signals are used as input signals to the address generation unit 704-3 via a further connection path 704-208.

030024/0883

The signals characteristic of the sequence control field are used as input signals to the sequential control logic circuits 704-100 via the connection path 704-210. As explained here, decode these circuits control the sequencer field and generate signals by which the cache memory unit 750 enters the Stand is placed to perform the specified operation.

As mentioned earlier, the drain address generator circuit is given 701-1 an input address corresponding to the CCSA field from the control store 704-2. How out Fig. 3b can be seen, these circuits comprise an input address register 701-10, the output of which with a Position of a 4-position switch 701-12 is connected; this position is labeled ZECSA. The exit of the relevant switch serves as an address source for the control store 701-2. In the first position of switch 701-12, an address is received from MICA register 701-14. The contents of the register 701-14 is updated at the end of each cycle to point to the location within the ECS control memory that follows that location or that storage location, the content of which during the relevant Cycle has been read out.

In the second position, the ZCSBRA selector switch 701-18 evoked address selected. The third position is the address of the first Microinstruction selected in each microprogram supplied by the CCS control store, where a Loading into REXA register 701-10 takes place. If the CCS output signal fails at the end of a microprogram is available, a predetermined address (octal address 14) is automatically selected.

In the first position of the branch switch 701-18

030024/0683

signals are received corresponding to a branch address selected from memory 701-2 has been read into register 701-4 and which in turn becomes a return control register 701-20 has been forwarded. In the second and fourth positions of the switch 701-18, signals from the RSCR register 701-20 or a MIC register 701-15 or the contents of a number of vector branch registers 701-36. The MIC register 701-15 stores an address pointing to the microinstruction ^^ word following the microinstruction word which is performed. This address corresponds to the address from switch 701-12, with an increment by one by incrementing circuit 701-12 he follows.

The vector branch registers comprise a 4-bit vector branch register 0 (RVBO), a 2-bit vector branch register 1 (RVB1) and a 2-bit vector branch register 2 (RVB2). These registers are loaded with address values derived from Signals are derived which are stored in a number of different display flip-flops and registers and which are used as input signals to the number of groups from input multiplexer selection circuits 701-32 and 701-34. The output signals of the respective circuits 701-32 and 701-34 are input signals to two-position selection circuits 701-30 submitted. These circuits in turn generate the output signals ZVBRO, ZVBR1 and ZVBR2, the can be stored in register 701-36.

Switch 701-36 provides an address based on the testing of the various hardware indicators signals and status flip-flops signals, which are selected via an INDGRP field. The branch decision is masked (ANDING) of the

03Ö02W08Ö3

selected display set with the fields INDMSKU and INDMSKL of a microinstruction word determined. if a vector branch is selected, the INMSKU field is treated as a field containing four zero bits. The OR signal of the eight bits is compared with the state indicated by the microinstruction fields TYPG and GO is defined. The hardware signals are passed through a number of data selection circuits 701-28, of which only a selection circuit is illustrated. The output signals these selection circuits are sequentially used as inputs to another five-position multiplexer selection circuit 701-26 supplied. The output of the multiplexer circuit 701-26 is sent to a comparator circuit which combines the display signals with the mask signals and, in a manner, to form the result signals MSKCBRO-7 to generate.

The signals MSKCBRO-7 are used in a further comparator circuit supplied, which the relevant signals with the state branch test signals TYPGGO and according to summarizes to set or reset a branch decision flip-flop 701-22. This Flip-flop generates a signal RBDGO, the state of which indicates whether a branch is taking place. The output signal RBDGO is used as a control input signal to the first input of two inputs or positions of the Switch 701-12 supplied. If the branch test condition is not met (i.e. the signal RBDGO = 0) then the incremented address is selected from MICA register 701-14.

In some cases, as in the present case, it is not possible to test the state of a display for the cycle that follows the formation of the relevant display. Because of this, the historical development

030024/0883

Recording development registers HR0-HR7 (not shown) for register storage of the group related advertisements are provided. The states of the displays stored in this way are selected and saved in a Tested in a similar way to the rest of the ads (these are masking fields).

The unit 701-1 also comprises a number of display circuits, certain of which are display circuits can be used to control the operation of certain parts of the processor 700 when the Strings processed by certain types of commands have been issued. These display circuits are contained in block 701-42; they are under the control of a field within the Microinstruction word according to Fig. 6a set and reset (this is the IND6 field). The bits of this field, read from the ECS output register 701-4 are output to an RMI register 701-38 for a decoder 701-40 to be decoded. Based on the state of the status indicator signals sent by the different processor units are included (e.g. 714, 720, 722, etc.), the relevant Auxiliary flip-flops switched to binary 1. the The output signals of these flip-flops are switched via the various positions of a four-position switch 701-44 is applied to the GP3 position of switch 701-26 to run a test. Same output signals become a ^ wide position of a ZIR switch 701-43 to cause storage via the ZDO switch 704-340. The ZIR switch 701-43 also receives display signals from the display register (IR) 701-41. This register is about the RDI lines 18-30 and 32 for the occurrence of loaded with certain commands.

030024/0883

29Α9787

The display status signals include, for example, the Output signals of the various adder circuits (AL, AXP) of the unit 720. These signals set different Flip-flops of the output indicator flip-flops provided in a number, labeled FE11, FE12, FE13, FE1E, FE2E, FE2 and FE3 are designated. Flip-flops FE1E and FE2E become one during each FPOA cycle Command set. These flip-flops in turn set flip-flops FE11, FE12 and FE13 when the Output signals from the adder circuits AL or AXP of the unit 720 occur. Setting and resetting these indications are described in more detail below in connection with the explanation of the operation described. The dispensing flag flip-flops that are important to the embodiment are accordingly the following Boolean expressions are set or reset, with the setting in each case with SET and resetting is indicated with RESET.

FPOA + IND6FLD field

IND6FLD field.

FPOA + IND6FLD field.

IND6FLD field.

IND6FLD field .FElE (ALES + AXPES +

DESCl ΑΡ0-4 = 0) + IND6FLD - FeÜFElE-

DESCl- (AP0-5 = 0 + APZN + ALZN) + IND6FLD field

FPOA + IND6FLD field.

IND6FLD field-FElE- (ALES + AXPES + FE13).

FPOA + IND6FLD field.

IND6FLD field -FElE-ALES + IND6FLD field

FPOA + IND6FLD field.

FE2 = IND6FLD field -FE2E-ALES + IND6FLD field · FE2E-DESC2- (AP0-4 = O + AP0-5 = »0 + APZN + ALZN) + (IND6FLD field) FE2E-DESC2 + IND6FLD.
RESET: FE2 = FPOA + IND6FLD field.

SET FElE RESET. FElE SET FE2E RESET FE2E SET FEIl KESET FEIl SET . FE12 RESET FE 12 SET FE13 RESET FE 13 SET FE 2

030024/0883

SET: FE3 = IND6FLD field DESC3 (AP0-4 = 0 + APO-5 + APZN + ALZN) + IND6FLD field -DESC3 + IND6FLD.

RESET: FE3 = FPOA + IND6FLD field.

via IND6FLD * issues a specific code.

ALES "= AL-O or AL-C;
AXPES = AXP = O or AXP-C;
APZN «APO-7 * 0; And,
ALZN »ALO-Il ⁵ 0.

The ZCSBRA switch 701-18 is normally enabled, if the branch decision flip-flop RBD did not go to binary 1 during the previous cycle was set. The first position is a 13-bit branch address selected by the current microinstruction issued via the RCR register 701-20 will. The branch address gives the direct addressing of any one of the memory locations of the ECS control memory free. In the second position the chaining of the six lower ones will be Address bits selected from the present microinstruction issued via MIC register 701-15, and the upper seven bits of the branch address from the present microinstruction via the RCR register 701-20 is delivered. This allows branches within a 64 word page like this determined by the contents of the MIC register 701-15 is (available storage space + 1).

In the third position, the concatenation of the four low-order bits from the RVBO vector branch register.der six bits from the branch field of the present microinstruction stored in the RCSR register and the upper three bits of the address stored in the MIC register. this enables 16-fold branches. In the fourth position

030024/0883

294978?

becomes the concatenation of the two low-order zeros with the four bits from the vector branch register RVBO as well as with the four most significant bits of the branch address field of the present microinstruction and selected with the upper three bits of the present address stored in the MIC register. This allows 16-fold branches in the three Control storage locations between each adjacent pair of destination addresses.

In the fifth position, the concatenation of the two low-order zeros with two bits from the vector branch register RVB1 as well as with the six bits of the branch address of the current microinstruction and the upper three bits are selected from the MIC register. This enables branches with four possible Determinations with three control memory locations between the respective neighboring pair of destination addresses.

In the sixth position, the concatenation of the two low-order zeros with two bits of the Vector branch register RVB2 and with the six bits of the branch address of the current one Microinstruction and the upper three bits are selected from the MIC register. this makes possible fourfold branches with three control memory locations between the respective neighboring pair of destination addresses.

The output signals of the failure 701-12 address a specific memory location within the control memory 701-2, which causes the reading out of a microinstruction word with a format shown in FIG. 6b. From Fig. 6b it can be seen that this microinstruction word is encoded in such a way that there is a number

090024/0883

-u

encompassed by different fields that are used for this purpose, the various functional units within the processor 700 to control. Only those fields are described here that are refer to the present embodiment.

Bits 0-1 bit 2

Bits 3-5

Bits 6-6 Reserved for future use

EUFMT Defines the format with which EU is described. By EUFMT-O is a first microinstruction format specified, while another microinstruction format is defined by EUFMT = I. TRL TR means at low

Write control level. Write control of the EU short-term registers TR0-TR3.

OXX No change No change 100 Letter TRO Letter TR4 101 Write TR1 Letter TR5 110 Letter TR2 Letter TR6 111 Letter TR3 Letter TR7 TRH TR means high level Write control Write taxation of the EU short-term Register TR4-TR7. OXX 100 101 110 111

Bits 9-12

ZOPA ZOPA counter control

030024/0883

Selection of the output signal of the ZOPA switch.

O) 0000 TRO D. 0001 TR1 2) 0010 TR2 3) 0011 TR3 4) 0100 TR4 5) 0101 TR5 6) 0110 TR6 7) 0111 TR7 8-11) 1OXX RDI 12) 1100 ZEB 13) 1101 ZEB 14) 1110 ZEB 15) 1111 O (ineffective).

Bits 13-16 ZOPB ZOPB switch control.

Selection of the output signal of the

ZOPB switch.
Bits 17-18 ZRESA ZRESA switch control.

Selection of the output signal of the

ZRESA switch.

00 Arithmetic and logic operation

01 sliding device

0O Notepad memory / RDI switch

11 ZDO

Bits 19-20 ZRESB ZRESB switch control.

Selection of the output signal of the ZRESB switch.

00 arithmetic and linking work

01 sliding device

10 notepad memory / RDI switch

11 ZDO

Bit 21 RSPB scratch pad memory buffer scan

steering.
Sampling RSPB with ZRESB data

0 no sampling

1 scanning of RSPB 030024/0883

Bit 22

Bit 23

Bits 24-25

Bits 24-27

Bits 24-29 bits 26-31

Bits 30-31 RSP scratch pad memory write control.

0 Read the notepad memory

1 Writing the notepad memory

ZSPDI Notepad Memory / RDI Switch -

steering

Selection of the output signal of the notepad memory / RDI switch

0 Notepad memory output signal

1 RDI

ZSHFOP Shifting the operand switch control

Selection of the left operand for the shift device

00 ZOPA output signal

01 EIS output signal

10 0

11 Selection of 0 or -1 depending on from bit 0 of the right operand for the shifter

Arithmetic and logic unit ALU (arithmetic and logic unit) function control

Selection of the operation related to the two input signals (A and B) are to be used for the arithmetic and logic operation.

RFU For future use

reserved

ZALU ALU switch control Selection of the output signal of the ZALU switch

030024/0883

Bits 32-33 NXTD Next Descriptor Control Scanning the RBASB and RDESC registers

00 RBASB 00 RDESC 01

01 RBASB 01 RDESC 01

10 RBASB Alt RDESC 10

11 No samples (not complied with) Bits 32-35 CCM control constant field on the

referenced by the CONTF field

will Bits 34-35 IBPIPE IBUF / Pipeline Control

Choice of reading from IBUF or pipeline operation

00 No operation

01 Reading from IBUF / ZDI (old)

10 Type 1 of a restart release or

11 Type 4 restart wait bits 36-37 FMTD

Selection of loading of the various CU registers and display of the interpretation given to the MEMADR field for a low CU control is to be given.

00 No operation

01 RADO ASFA

10 RADO ZRESB

11 RADO ASFA

Bits 38-40 MEMADR cache memory control

Selection of Cache Operations · The full interpretation regarding this control is a function the FMTD control.

000 No operation

001 Single reading 010 Quad load

030024/0883

Bit Ί1

Bits 42-44

2949797

011 Read ahead

100 individual letters

101 double letters

110 single read transmission (only with FMTD = 11)

111 single word writing (only with FMTD = 11)

ZONE Zone control

This creates a zone or none

Zone for a low CU control

displayed.

0 No zone

1 zone

TYPA Type A mark

This indicates that the

Type A superimposed on fields is used

will.

000 Type — A = 0 fields

100 type A = 4 fields

Bits 44-46 PIPE Pipeline control No surgery selection of the type to be read out Type 1 restart and trip Reboots Restart type 2 000 Restart type 3 001 Restart type 4 010 Restart type 5 011 Restart type 6 100 Auxiliary register write 101 steering 110 an auxiliary control gate or Bits 44-47 AUX REG of register combinations, selection

030024/0883

Bits 45-46

to be sampled with data selected by the AUXIN control panel are*

O; 0000 No sampling Fields are used. D. 0001 RRDXA Type B = O fields 2) 0010 R29 3) 0011 R29, PRDXA, FRL, RID 4) 0100 RRDXB 5) 0101 RTYP 6) 0110 RBASA 7) 0111 RBASA, RTYP 8th) 1000 RBASB 9) 1001 RDESC 10) RBASA, R29, RRDXA TYPEB Identification type B This indicates that of type B superimposed OO

11 Type-B = 3-fields bit 47 RSC RSC scan control

Scanning the RSC register (shifting

the counter) Bit 47 RSPA RSPA scan control

Scan RSPA register bits 47-48 N / A
Bit 47 RAAU RAUU sampling control

Scan the RAAU register bits 48-49 ZLX ZLX switch control

Selection of the output signal of the

ZLX switch
Bits 48-49 ZSPA ZSPA switch control

03002Λ / 0683

29A9787

Selection of the output signal of the

ZSPA switch

Bits 48-50 AUXIN auxiliary register input

steering

Selection of the in the auxiliary register (s)

data to be scanned Bit 49 ZADSP ZADSP switch control

Selection of the output signal of the

ZADSP switch
Bits 50-52 ZSC ZSC switch control

Selection of the output signal of the

ZSC switch
Bits 50-52 ZRSPA ZRSPA switch control

Selection of the output signal of the

ZRSPA switch

Bits 50-52 ZAAU ZAUU switch control bit 51 RSIR RSIR register scan

Scan the RSIR register as

Function of the AUXIN field Bit 53 RDW R1DW, R2DW register scanning.

Scanning the R1DW or R2RW register

as a function of the RDESC register bits 53-54 ZLNA ZLNA switch control.

Selection of the output signal of the ZLNA

Switch.
Bits 54-57 CONTF Various flip-flop controls

Selection of a group from four groups

of control flip-flops caused by the

Control constant field (CCM) too

set or reset.

The flip-flops include those flip-flops

of blocks 704-104 and 704-110. Bits 55-56 ZLNB ZLNB switch control.

Selection of the output signal of the ZLNB

Switch.
Bits 55-56 ZSPA (2) type A = 2, ZSPA switch,

RSPA register control.

03002 ^ / 0003

Selection of the output signal of the ZSPA switch and scanning of the RSPA register.

Bits 57-58 ZPB ZPB switch control.

Selection of the output signal of the ZPC switch.

Bits 59-62 ZXP ZXP switch, RXP register,

Bank management.

Selection of the output signal of the ZXP switch and the RXP register to be written to.

Bits 59-63 ZLN (I) ZLN switch, RLN register

(Type A = 1) Bank control Selection of the output signal of the ZLN switch and the RLN register that is being written to.

Bits 59-60 ZPA ZPA switch control.

Selection of the output signal of the ZPA-Charter s.
00 m RPO

11 RP3
Bits 61-62 ZPB ZPB switch control

Selection of the output signal of the

ZPB switch.

00 = RPO

11 = RP3

Bits 63-64 ZXPL ZXPL switch control

(Type A = O)

Selection of the output signal of the ZYPL switch.

030024/0883

οο

RXPA

Bit 63

Bits 63-66 Bit 64

Bits 64-68 Bits 65-66

Bit 65-66

11 = RXPD

ZLN (2) ZLN switch, RLN register (type A = 2) bank control Selection of the ZLN switch output signal and the RLN register that is being written to. RDIN RDI input control. Selection of the in the RDI register too keying data and selection of one of the modification control fields (MF1-MF3, TAG) of a command word. RDI scanning can also be done through the MISCREG field can be controlled. ZXPL (1) ZXPL switch control. (Type A = 1)

Selection of the output signal of the ZXPL switch.

ZRPAC ZRAP switch, ZAPC switch, (Type A = 2), RPO-3 register bank control.

Selection of the output signals of the ZRPC and ZRPA switch and the RPO-3 register into which the ZRPA output signal is written. ZXPR ZXPR switch gate control. (Type A-O)

Selection of the output signal of the ZXPR switch.

ZXP (D ZXP switch, RXP register (Type A »D bank control selection of the output signals of the

030024/0883

- '100 * -

ZXP switch and the RXP register,

into which the output signal is written.
Bits 67-68 ZPD ZPD switch control.

(Type A = O)

Selection of the output signal of the ZPD

Switch.
Bit 67 ZPAC (4) ZRPA switch,

ZRPC switch,

(Type A = 4) RPO-3 register bank control

Selection of CPA from the ZRPA counter and

Scanning the RP1 register. Bit 67 TYPD type D identifier

Type D mark shows D superimposed

Fields.
Bit 68 ZRPB (4) ZRPB switch, RP4-7 register,

Bank control

(Type A = 4)

Select the O from the ZRPB switch and ₍ scan the RP4 register.

Bits 68-71 MEM cache control.

Selection of cache memory operation in

Connection with the SZ control. 0) 0000 No operation

15) 1111 Remote Write Bits 68-70 IBUF IBUF Read Control.

Selection of the destination of the IBUF data when IBUF is read. Bits 69-73 AXP ZXPA switch, ZXPB switch,

(Type A = O) AXP adder, ZAXP switch, RE register control.

030024/0883

Selection of the output signals of the ZXPA and ZYPB switches, with regard to which the AXP adder function is performed and the output signal of the ZXP switch. Further scanning of the RE register.

Bits 69-73 ZRPB ZRPB switch, register RP4-7

Bank control (type A = 1) Selection of the output signal of the ZRPB switch and the RP4-7 register, in that the relevant output signal is written.

Bits 69-71 ZRPAC-3 ZRPA switch, ZRPC switch

ter RPO-3 register bank control (type A = 3)

Selection of the output signals of the ZRPC and ZRPA switch and the Register RPO-O, in which the ZRPA output signal is written will.

Bits 72-74 ZRPB (3) ZRPB switch, register RP4-7,

Bank control (type = 3) Selection of the output signal of the ZRPB switch and the register RP4-7, into which this output signal is written.

Bits 72-73 SZ size / zone cache control.

The control of the cache memory operations is in connection with the MEM control field.

Bits 74-78 ZRPB (3) ZRPB switch, register

RP4-7 register Bank control (type A «0) Selection of the output signal of the ZRP switch and the register RP4-7,

03002A / 08B3

Bits 74-78

Bits 74

Bits 75-77

Bits 75-78

Bits 75-78 Bit 78

Bits 79-83

Bits 79-81

into which the relevant output signal is written. AL ZALA switch, ZALB switch, AL adder control (Type A = 1) Selection of the output signal of the ZALA switch and the ZALB switch and the AL adder function applied to these output signals.

TYPE Type E identification The identification of Type E shows the Type E superimposed on fields. ZXP (3) ZXP switch, RXP register bank, control (type A = 3) Selection of the ZXP switch output signal and the RXP register into which the relevant output signal is written.

MISCREG Various register controls.

Selection of different operations in different registers (e.g. RBIR, RDI, RLEN, RSPP). ZDO ZDO switch control. Selection of the output signal of the ZDO switch.

ZIZN ZIZN switch control. Selection of the output signal of the ZIZN switch.

AP ZAPA switch, ZAPB switch, AP adder control. Selection of the ΖΑΡΑ and the ZAPB switch output signal and the AP adder function, which are based on these output signals is applied. ZLN (3) (Type A = 3) ZLN switch,

030024/0883

RLN register bank control. Selection of the ZLN switch output signal and the ZLN register, in which the relevant output signal is written in.

Bits 79-83 ZLN (4)

(Type A = 4) ZLN switch, RLN register bank control.

Selection of the ZLN output signal and of the RLN register into which the relevant output signal is written.

Bits 80-81 RAAU RAAU / RE register scan.

Selection of the registers RAAU and RE by controlling different Switches and adders in the unit 722 to be keyed in data.

Bits 82-83 AP (3) ZAPA switch, ZAPB-

(Type A = 3) switch, AP adder control.

Selection of the ZAPA and ZAPB switch output signals and the AP adder function applied to them.

Bit 84 ZRSC ZRSC switch control.

(Type A «0)

Selection of the output signal of the ZRSC switch.

Bits 85-86 N / A

Bit 86 RLEN RLEN scan control.

(Type A = 3)

The RLEN samples are also controlled by hardware or by the MISCREG field.

Bit 87 FMT format identifier, which

indicates the type of Ibrmat.

030024/0883

Bits 88-89 TYPF the type of overlay fields 0000 No operation Shows 0001 Loading data at. Notepad storage address 0010 MOP process 00 = Drawing unit control 0011 individual comparison 01 = Multiplication / division 0100 double comparison 10 = steering 0101 Load register N / A 0110 Update CN 11 = For future use 0111 Undefined Bit 90 RFU reserved 1000 Set the RCH operation A Character unit operation 1001 Setting of RTF1 Bits 90-93 CHROP code. 1010 Setting of RTF2 Selection of the main operation carried out by 1011 Setting of RTF3 the drawing unit is to be executed, 1100 Setting of RCN1 and the interpretation given to the 1101 Setting of RCN2 CHSUBOP field is to be given. 1110 Setting of processing 0) Mark D. 1111 Deletion of the CH unit 2) RCH register entry 3) 4) 5) 6) 7) 8th) 9) 10) 11) 12) 13) 14) 15) RCH Bit 90

Scanning the 0P1-RCH register

Bit 90 RFU For future use

reserved.

030024/0883

TIOi

29A9787

Bits 91-97

Bits 91-93
Bits 9 ^ -97

SPA notepad storage address. It contains the address that can be used to address the ES notepad memory. N / A
CHSUBOP character unit sub

operation code.

Selection of the detailed function of the drawing unit; or they can contain a constant. The interpretation of this field is a function of the CHROP control, as shown below. CHROP = 0000 No operation CHSUBOP _0-3

XXXX No interpretation CHROP a 0001 Loading the data operation

CHSUBOP _0-1 (Suboperation) 00 Operation 1 loading through CN1 and FT1 01 Operation 1 load in reverse direction through CN1 and TF1 10 Operation 2 loading through CN2 and TF2 and test characters 11 Loading the sign CHSUBOP _2-3 (Filling control) 1X Leader characters loaded in ZCU X1 Filler characters loaded into ZCV CHROP = 0010 MOP run tune operation CHSUBOP _0-1 (, Suboperation) 00 MOP set by CN2 01 MOP process 10 Undefined 11 Undefined

030024/0883

Up to 99

Bits 99-106 Bits 99-106

Bits 99-106

CHUBOP _2-3

XX

CHROP »0101 CHSUBOP,

0-1

CHSUBOP

2-3

CHROP = 1011

2949737

No interpretation. Load register operation (selection of the output signal of RCH) (selection of the output signal of the ZOC switch) Set the RTF3 operation

CHSUBOP

0-1

CHSUB0P ₂ _, CHROP = 1110

CHSUBOP

0-3

1XXX

X1XX XX1X XXX1 Bits 94-97 RFU Bits 97-97 N / A Bit 98 TYPC

(Selection of data to be monitored for OO, display of a 9-bit character) (constant field) Setting the processing flag operation (constant selection flags to be set) Setting ES (end suppression)

Set SN (sign) Set Z (zero) Set BZ (empty if zero) Reserved for future use

Identifier type G This shows the type of the superimposed Fields.

0 «BRADRU field

1 - IND6 field

GO State of the condition

branching tests

BRADRU Branch High Address IND6FLD Display Control Select a display. Bit 99 ^a 0 defines a change display command.

03002A / 0883

29A9787

Bit 99 = 1 defines a set / reset display command (set or reset is indicated by the X bit as 0 or 1)
Bits 100-104 105 = 1 106 = 1 0000

Bits 107-112, bit 113

Bits 114-116

Bits 117-11B bits 119-123

Bit 124

1100X output 1 output 2 1101X output 3 N / A 1110X output 1 output 2 Ef f. Ef f.

BRADRL Lower branch address that contains the lower part of a for a Branch contains used ECS address.

EXIT Selection of the output switch control.

The selection of the output indicates the end of a microprogram. ZCSBRA ZCSBRA switch control. This selects the position to be selected in a control store branch address switch.
N / A
INDGRP Condition Branch Indicator

Group control.

The first two bits (119-120) select the "group" of microprogram displays the end. The last three bits (121-123) select the "setting" of the displays within each "group". TYPH type H field, which shows the type H overlaid fields.

030024/0883

0 = INDMSKU

1 = VCTR field

Bits 125-128 INDSMSKU Upper condition control

branch display screen. It contains the upper four bits of the Display mask in the field of type H = 0.

Bits 125-129 VCTR vector selection.

Selection of branch vectors RVB1 and RVB2 are groping in the register RVBO. The highest value bit (125) determines which of the two groups 0 or 1, 2 or 3 or 4 or 5 is keyed into the register RVBO, RVB1 or RVB2. The remaining three bits select the vector within the respective group.

Bits 129-132 INDMSKL Lower Condition Branch Display Mask .

The four lower bits of the display mask are included.

Bits 133-135 N / A

Bits 136-139 CNSTU high constant;

comprise the upper four bits of the constant field.

Bits 140-143 CNSTL lower constant. she

comprise the lower four bits of the constant field.

030024/0883

- 4Θ9 »-

Mr 29A9787

The control logic unit 704-1 is explained in more detail below. This unit comprises the sequence decode logic circuits 704-T0Q, as already mentioned, the outputs of which are fed to a plurality of I-cycle control state flip-flops of block 704-102. These flip-flops generate the various required I-cycle control states in response to signals from the circuits 704-100 and to microinstruction signals from the register 701-4 (DMEMRO38-40, which correspond to the MEM address field MEMADR according to FIG. 6b, It is assumed that block 704-102 further includes logic circuits ^e n which generate register hold signals (HOLDEOO, which are distributed in processor 700).

As can be seen from Figure 3c, the I cycle take control state flip-flops Control input signals via control lines, including a CPSTOPOO line, from the cache memory unit 750. As explained here, the state of the CPSTOPOO line determines whether the processor operation continues when the line carries a binary 0 signal. The hold or release signals for the I-cycle control state flip-flops and the other storage registers are also brought to the zero state. The stop signals, the signals HOLDIOO and HOLDEOO are processed in such a way that the state of processor 700 is retained or is held. Since the control store address cannot be incremented, the ECS control store reads the same microinstruction word. The signals HOLDI and HOLDE are made in accordance with the following Boolean expressions set: HOLDI «CACHE HOLD + TERMB (DREQ-IF-DIR) + HOLD REL, where the state of the CACHE HOLD signal corresponds to the state of the CPSTOP signal and where the signals TERMB (DREQ-IF-DIR)

030024 / 08β3

Binary signals are 1 during the control state FPOA, if the cache instruction is an I call or direct Operation is specified and the HOLD REL signal is a binary 1 until it passes through to a binary 0 the generation of a microprogram trigger signal is switched. Furthermore, HOLD E »HOLD I.

As is apparent from FIG. 3c, signals corresponding to the I cycle control states are input signals of a Plurality of control flip-flops of block 704-104, the decoder circuits of block 704-106, a number of Control gates of block 704-108 and a plurality of control flag flip-flops of block 704-110 fed. It should also be seen that the various display flip-flops of block 704-110 receive microinstruction inputs on lines MEMDO54-57 of FIG the sequence control unit 701-4.

As can be seen in Figure 3c, those generated by the hardware control logic circuits 704-108 fall Signals into one of three groups as a function of the units whose operations are being controlled. this means that the groups are given by the command

030024/0883

buffer control, through the hardware control and the Hardware memory control.

In either case, each group of signals is grouped or mismatched with corresponding or equivalent signals generated by other sources and then decoded. The other sources correspond to the fields within the two different formats of the microinstruction word according to FIG. 6a, which are loaded from the ECS output register 701-4 into the RCSR register 704-112.

One field corresponds to bits 32-83 of one format (CU long) and another field (CU short) corresponds to the Bits 32-41 of another format. These fields are converted into the records of the designated by the decoder 704-114 Bits are decoded and combined in decoders 704-116, 704-124, 704-126 and 704-128. Another decoding is made by the circuits of blocks 704-118, 704-135 and 704-120. The results of the decoding such fields are either distributed in processor 700 or they are stored in an RMEM register 704-130, an RSZ flip-flop 704-132, a FREQDIR flip-flop 704-136, and a FREQCAC flip-flop 704-134.

An additional decoding of the long and short CU fields and signals from the I-cycle state circuits of block 704-112 takes place via a decoder 704-106 and a decoder 704-107 · The decoder 704-106 generates control signals for loading different registers of the provided registers and for enabling various multiplexer selection switches within the processor 700. The decoder 704-107 operates to generate signals to set a pair (RBASB) of the base pointer B flip-flops 704-144. Other combinations of these signals are used to set or reset the descriptor

030024/0883

number flip-flops of blocks 704-1AO and 704-142 are used.

From Fig. 3c it can be seen that the decoder 704-116 receives a control signal EXHOO, which is from the decoder circuits of block 704-117 is generated. These circuits take signals from the RDESC register 704-140 on as well as signals from the dispensing flip-flops of the block 701-1. In accordance with the states of these signals, the respective circuits output the signal EXHOO as binary 0 to indicate the generation of a cache memory instruction to lock on the occurrence of an output condition. The signal EXHOOO becomes in accordance with generated by the following Boolean expression.

EXHOOO = DESCO · FE11 + DESC1. FE2 + DESC2. FE3.

The flip-flop FNUM is normally set upon the occurrence of the CCS-OP field of the microinstruction word. If the relevant flip-flop is set to binary 1, this indicates that the descriptor being processed is of the digit type or numeric type.

The various flip-flops of block 704-104 are explained in detail below. The flip-flop FCHAR causes changes in the control of address generation in detail. When the FCHAR flip-flop in the binary state 1 is set during the processing of its load command, which specifies a character modification, then the content of the RDI register is not changed under the influence of the hardware control. This makes possible, the RDI register of data under microprogram control prior to beginning the pipeline operation load. If the FCHAR flip-flop in the binary state 1 during the presence of a store command specifying a character modification is set, then also the execution address for this command under the hardware

030024/0883

Control modified to point to a unique address of the microinstruction sequence in the ECS control store according to which this type of instruction is to be processed.

The flip-flop FDT-FOUR leads to an additional control with regard to the reading of the address register (ZAR _0-19 ) of the block 704-304. The FADR-WD flip-flop provides additional control for the ZDO switch 704-340. If this flip-flop is set to a binary state, then a word address is selected in the ZAR position of the ZDO switch. The flip-flop FAD-B provides additional control with regard to the ZDO multiplexer switch. If this flip-flop is in the binary state 1, then a byte address is selected via the ZAR position of the ZDO switch. The flip-flop FNUM is normally set as a function of the CCS-OP field of the microinstruction word. When the relevant flip-flop is set to binary 1, this indicates that the descriptor being processed is of the numeric type. The FIG-LEN flip-flop provides additional control over the loading of the registers within the unit 722 (length register) and over the memory operations. If the relevant flip-flop is set to the binary state 1, the registers RXP and iiLN within the unit 722 are not loaded by the RSIR register 704-154 during certain states of the processor control states FROP.

The flip-flop FINH-ADR inhibits the operation of the address formation unit 704-3. If the flip-flop in question is in the binary state 1 is set, an address cycle (FPOA / FPOP) comprises adding the contents of a short-term storage register REA-T containing an effective address Zero. The REA-T register will be loaded with the address prior to executing an FPOA-FPOP cycle. The FABS flip-flop enables absolute addresses to be generated. If the relevant flip-flop has switched to binary state 1

. 030024/0883

sets 1st, becomes a 24-bit absolute address used. With regard to the identifier or the identifier of the flip-flop of block 704-110 notes that when the flip-flop FID is set to binary 1, it provides an indication of it, that an indirect address modification is required during an instruction with respect to the descriptor, the is loaded into the RSIR register.

When set (binary state 1), the FRL flip-flop indicates that the length is specified in a register associated with the instruction loaded into the various instruction registers. The three flip-flops FINDA, FINDB and FlNDC provide displays that are used to Processing of commands of the memory type can be used. The FINDA flip-flop is in a binary state 1 set if a length is specified in a register or if the flip-flop FAFI is in the binary state 1 is set. The flip-flop FINDB is set to a binary state 1 if the descriptor does not contain 9-bit characters. The FINDC flip-flop is set to a binary state 1 if the descriptor is 6-bit characters contains.

The FAFl flip-flop is set to a binary state 1 when the processor circuits determine that the Indicator bit 30 of IR register 701-41 was set to the binary state during execution of an EIS instruction which is characteristic of a middle command interruption (which is required for setting the pointer and the length values due to the interruption). The flip-flops FTRGP, TTNGO and FTRF-TST are connected set in binary states 1 with transfer commands. That In particular, the FTRGP flip-flop provides a microprogram indication of being set in the binary state 1 when the processor circuits read out a transfer-type instruction while executing a double-flow (XED)

03Q02W0883

or a repeat command. The FTNGO flip-flop provides a microprogram indication that it is set in the binary state 1 if the transfer condition signaled by the sequence control unit 701 was a NOGO transfer (which means that the Transfer does not take place). The output of this Flip-flops are fed to the NOGO line of the interface circuit 604. The FTRF-TST flip-flop of this group provides an indication when the relevant flip-flop is set to the binary state 1, which indicates that the instruction previously executed by processor 700 was a transfer type instruction; and that the I-cycle being executed depends on the presence of a Transfer GO (TRGO) signal from controller 701.

The circuits of block 704-110 also include a number of flip-flops which are used to execute indirect addressing operations under hard-wired control are exploited for different commands than for the EIS commands. These flip-flops include the FIR, FIRT, FIRL, and FRI flip-flops that are included in the binary states 1 are set as functions of different types of indirect addressing modifications which is required to be carried out. For example, the FRI flip-flop then signals a register with a indirect address modification, and the flip-flop concerned is switched to a blaring state 1 if a indirect · Register display (RI) is given by a binary signal 1. The FRI flip-flop is in a binary state 1 then switched when an indirect register display (IR) occurs as a binary 1. This flip-flop signals the beginning of an indirect, subsequent register address modification. The FIRL flip-flop is then turned into a Binary state 1 switched over if an indirect counter display (IT-I) is a binary 1 in indirect operation. This flip-flop signals a final indirect

Q3002A / 0883

29A9787

Surgery. Another TSX2 flip-flop provides an indication that is used when processing a transfer is, and sets index commands, while a flip-flop STR-CPR in the course of processing memory commands is exploited.

As can be seen from Figure 3c, the output signals are from the control flag flip-flops of the block 704-110 are provided as inputs to the branch indicator circuits of block 700-1. Also be the output signals from the control flag flip-flops the I-cycle flip-flops of the block as input signals 704-102 supplied.

The register area 704-150 is explained in more detail below. As can be seen from Fig. 3c, the control logic unit comprises 704-1 also has a register area 704-150. This area includes the basic instruction register (RBIR) 704-152, the secondary instruction register (RSIR) 704-154, a base pointer A register (RBASA) 704-156 which is used for Selection of one of the address registers RARO to RAR7 of block 704-304 is used, a read index register A (RRDXA) 704-158, which is used to select index registers within the range 704-5 (not shown) and which is used to select the output signals of the ZDO multiplexer switch 704-340 is used, as well as a read index A retention register (RRDXAS) 704-159 and a descriptor register (RTYP) 704-160, which indicates the type of data characters pointed to by the descriptor value (e.g. 9-bit, 6-bit, 4-bit). The selection area 704-150 also includes a 1-bit instruction / EIS descriptor register, which is designated R29 of block 704-162. The state of this bit in connection with the content of the register RBAS-A 704-158 is used to select the specific address register which is to be used for address formation is used. If the register R29 of the

030024/0883

Block 704-162 is set to binary 1 this indicates that none of the address registers of blocks 704-304 are used during address formation. The last registers of the area 704-150 comprise a data or data input register (RDI) of the block 704-164 and a read index register B (RRDXB), which points to registers that are processed by the execution unit to be used.

As can be seen from FIG. 3c, the RBIR register 704-152 is adjustable in two positions Switch 740-170 is loaded which is switched to receive signals from the indicated sources (These are a switch ZIB-B 704-172 and lines ZDI 0-35). The RSIR register 704-154 takes in corresponding signals from the ZDI lines and the switch 704-172. The RBASA register 704-156 takes signals from the ZDI line 0-2 in addition to signals from another switch ZBASA of the block 704-174. Take the RDDXA register and the RTYP register Signals from the ZDI lines as well as from switches 704-176 and 704-178, as illustrated is. The RRDXA register also accepts signals from the RRDXAS register 704-159.

Switch 704-172 is a two position switch that receives input signals from the switches ZIB or ZRESB from the cache memory unit 750 or from the execution unit 714. Of the Switch 704-174 is a three input switch that receives two inputs from the execution units 714 and the output signal of the ZIB switch of the Cache storage unit 750 here.

Switch 704-176 is a four input switch that receives two of its inputs from the sequencer 714 and a single input from the

030024/0883

Cache memory unit 750 is supplied. In the first position of the ZRDXA switch 3 704-176, the output signal of a ZRDXM switch 704-185 is selected. In a When this switch is set, a flag field value is obtained from bit positions 5-8, 14-17 and 32-35 of the RBIR register 704-152 or from bit positions 32-35 of the RSIR Reglsters 704-154 provided by the ZIDD switch 704-180 and a two-position ZMF switch 740-176 is selected.

In the second position of the switch 704-185, a constant value given by the output of the ECS output register 704-1 (CCM field 32-34). The ones from the lines Signals coming from ZIDD 27-35 are used as input signals to the control code flip-flops of the block 704-110 submitted. The switch 704-178 receives an input from the control store 704-2 as well an input from cache storage unit 750 and an input signal from the execution unit 714.

The data input register 704-164 receives a series of input data from a ZIDD switch 704-180, which is in series with a ZDIA switch 704-181, the output signal of which represents an input signal for a further switch 704-182, which goes directly into the RDI register 704-164 is loaded. The ZDIA switch 704-181 supplies a further input signal to a three-input switch 704-183, which has signals from the cache memory unit 750 and at the other designated inputs the drain unit 714 is supplied.

The ZIDD switch 704-180 receives an effective address via switch 704-186 from address formation unit 704-3 and input signals from the RBIR register 704-152, from RSIR register 704-154, and from one ZMF switch 704-187 adjustable in two positions

030024/0883

- 449-

fed. Positions 18 to 35 of the REA position of switch 704-180 are derived from ZDIA switch 704-181 as illustrated. The ZDIA switch 704-181 receives signals from the ZDI lines 0-35 as well as a constant value that is generated from the input signals for a first switch position, in addition to signals from the output of the ZIDD switch 704-80 and the ZRESB switch in the sequence unit 714. Switch 704-182 takes the output of the ZDIA switch and the signals from the ZDI lines 0-35 on. The RRDXB register 704-189 is activated by means of a switch that can be set in three positions 704-188 loaded. In a first position, the switch receives signals from an RRBG register, which is shown in the drain unit is included. The relevant switch takes a constant value from the control store 701-2 in a second position, and in a third position it picks up signals from the ZIDD switch.

Area 704-150 also includes a two-position switch 704-185 and a scratch pad memory pointer register 704-186, whose output signal is used by the unit 722 for this purpose, addresses for to provide access to the unit's notepad memory. In the first switch position, a constant value provided, which is selected under hardware control (FP0A.R29). In the second Switch position, the content of the RBASA register 704-156 is output as the output signal. This position is selected under both hardware control and microprogram control (i.e. FPOA * R29 or MISCREG field).

It should be noted that the necessary timing or clock signals for the operating area as well as for the other areas of the processor 700 and of the cache storage unit 750 from centrally arranged

030024/0883

Clock circuits are supplied. For example, in the preferred embodiment according to FIG. 1, the Clock circuits are housed in the input / output processor system. Such clock circuits can be used as in can be viewed as constructed in a conventional manner; they can use a crystal controlled oscillator and counter circuits include. The timing or clock signals from the clock circuits are conventional Way distributed to the various parts of the system according to Fig. 1 to achieve synchronized operation. Circuits provided in processor 700 conduct additional clock signals from such timing signals if necessary. This is discussed further below in connection with the explanation of the cache memory unit 750 according to FIG. 4 was received.

The address formation unit 704-1 is explained in more detail below. The address formation unit 704-3 comprises a number of registers and adders. The registers contain a number of basic registers (i.e. TBASEO through TBASEB) of block 704-300 used to store descriptor values of an instruction, two Short-term register for storing effective addresses (TEAO, TEA1) and two command counters (ICBA, ICBB), which are stored in the block 704-302, which is used to address the command buffer. Also are eight address registers (RARO to RAR7) of block 704-304 are used during the address formation operations. the Unit 704-3 also includes an instruction counter 704-310.

The adders include adder 704-312, which is used to update instruction counter 304-310 through switches 704-311 and 704-314, and two adders 704-320 and 704-322. The adder 704-322 is used to generate an effective address value which is stored in a register 704-342 and as an input to the control unit 704-1

Q30024 / 0883

is delivered. The effective address is generated from a number of sources using a ZY switch 704-326, its output signal via a number of AND gates of block 704-327, selected address registers of block 704-304 or selected short-term address registers TEAO and TEA1 of block 704-302, the address output via a further switch 704-328 takes place. The sources in question can, however, also include index address signals ZXO-20 from the unit 704-5. In addition, the adder 704-322 is used to calculate the contents of the instruction counter of the cache memory instruction buffer to update.

As can be seen from Fig. 3d, the output signals of the adder 704-322 are also used as inputs to the Adder 704-320 supplied. The adder 704-320 becomes is used to use the base value stored in any one of the short-term base registers TBASEO to TBASEB with the address signals ACSOSO-19 from adder 704-322 to combine. The bits obtained in this way are used as an input variable for a further adder network 704-320 supplied, which generates a link address that through an adder 704-321 to lines ASFAO-36 is delivered. This adder sums the operand input signals with the carry input signals from blocks 704-300 and 704-320. The effective address is used for this, an absolute address to be obtained when the system is operated in a paging or paging mode. Because this operation is not important to the present invention, it is not explained further here. For further information reference is made to US ^ PS 39 76 978 with regard to address formation.

The temporary storage base registers called temporary registers of block 704-300 are loaded via switch 704-332. The switch receives a

03002A / 08Ö3

Input signal from the execution unit 714 and the output signal from block 704-300. The execution unit 714 gives further input signals to the registers of block 704-302 via a switch 704-334 and to the address register of block 704-304. An output multiplexer (ZDO) switch 704-340 gives the selection of the various registers within the addressing unit 704-3 and a unit 704-5 for the transfer of the contents of the respective units to the execution unit 714 free via the lines ZDO 0-35. In addition, the ZDO switch 704-340 shows the content of the various Register and control flip-flops of the unit 704-1 free to be read out via a fourth position (ZDO-A) to become. In the fifth position are the states of the various displays within the control memory circuits of block 701-1 released for the purpose of selection for the purpose of checking.

The following is the data / address output area 704-4 viewed in more detail according to FIG. 3e. This area includes the registers and switches that are used to transfer Instructions and data to cache memory 750 are used will. Such transfer operations typically require at least two cycles, one to send out one address and another for sending the data. Bits 5-8 of a command word are used by the output signal of a 4-position switch 704-40. This switch receives a first constant value Via a first switch position, the content of an RZN register 704-42 Via a second position, a second constant value via a third position and a third constant value Value over a fourth position.

Bits 1-4 of a command are used by the circuits of block 704-1 to an OR circuit 704-44 supplied together with bits 5-8. The OR gate 704-44 also receives the ZADO switch 704-46

03002A / 0883

Bits 1-8 of a RADO register 704-48 are supplied. That RADO register 704-48 is an address and data output register which, in a first position, is a ZADOB switch 704-48 a (virtual) link address from the address creation unit 704-3 via the Lines ASFAO-35 and data output signals from the unit 714 via the lines ZRESBO-35. The settings of the ZADOB switch 704-48 are made under the control of the FMTD field for a small amount CU format and under the control of the RADO field in the case of a large CU format.

As can be seen from FIG. 3e, either the bits ZZN1-8 or the ZADO bits 1 to 8 are used as output signals delivered to the RADO / ZADO lines as a function of the state of the control signal RADO-ZADO. the Bits 0 and I always carry binary ones, while bits 10-35 are provided by RADO registers 704-46.

Another piece of information regarding the other areas of the processor 700 and with regard to the areas according to FIGS. 3a to 3e is the one mentioned at the beginning another place.

In the following, the cache memory unit 750 is shown in FIG Fig. 4 explained in more detail. The cache storage unit 750 is divided into five main areas: a transit buffer and an instruction queue area 750-1, one Cache memory area 750-3 »an address list and Hit control area 750-5, an instruction buffer area 750-7, and an instruction counter area 750-9.

The following is the transit buffer and command queue area 750-1 a closer look. This area comprises, as main elements, a four-word write command buffer 750-100 and a four-word transit block buffer

030024/0883

A% 5 2949767

Read command buffer 750-102. These buffers are addressed via two counter circuits 750-104 and 750-106. In addition, the area concerned includes an instruction queue 750-107 with associated input and Output address pointer and comparator circuits of blocks 750-108 through 750-110. The write buffer 750-100 provides for the storage of a double single write or a single double write command during the Transit block 750-102 can store up to four read commands. The transit block buffer 750-102 also stores information associated with such read commands and used to control the Writing of memory data words inpuget Areas of the cache memory area 750-3 are used (these are the levels). The four registers allow up to to sequentially execute four memory reads at a given time.

The area 750-1 also includes a control area 750-112. This area contains rows of different Control circuits such as the command decoder and control circuits of block 750-113 and 750-114, the interface control circuits of blocks 750-115 and 750-116 and hold control circuits of block 750-117.

Decode the circuits of blocks 750-113 and 750-114

the commands issued by processor 700 over the RADO / ZADO lines of the interface circuit 604 are transmitted. In addition, the relevant circuits generate control signals in order to add entries to execute command queue 750-107 to retrieve values in the input pointer and output pointer circuits of the To increment or enlarge or set blocks 750-108 and 750-109. In addition, the circuits generate Control signals for storing commands are

03002A / 0883

29A9787

neither in write buffer 750-100 nor in transit block buffer 750-102.

The interface control circuits of blocks 750-115 and 750-116 generate signals to control the transfer from the data signals recorded by the system interface unit 100 into the area 750-7 or the transmission of commands comprising the transfer of such commands to the system interface unit. The latch circuits of block 750-117, which receive signals from the decoder circuit 750-113, generate Control signals for recording the execution or execution of commands in suitable situations (e.g. Address list area occupied) and to control the loading of data in the area 750-7.

From Fig. 2 it can be seen that the transfer of write command control words starting from the buffer 750-100 and via the third position one in four positions adjustable ZDTS switch 750-118, a data register 715-119 and the first position of the in two Positions adjustable switch 750-120 runs. The write data words are stored in the buffer 750-100 to the system interface unit 100 via a write data register 750-121 and the second position of the switch 750-120 are transmitted. The RWRT position of the switch 750-120 is used for one clock interval (single write command; or for two clock intervals (double write command) selected to receive a signal from the system interface unit 100 over the ARA line, in FIG Dependent on the fact that a signal on a line AOPR from the cache memory 750 for the transmission of a Write command is issued. Read commands are taken from the read command part of the transit block buffer 750-102 of the System interface unit 100 via the fourth position (ZTBC) of the ZDTS switch 750-118, the

030024/0883

2949797

Register 750-119 and the first position of the switch 750-120 transferred.

via the multi-port identification lines RMITS the zone bit signals are received through an RMITS register 750-124 and one in two positions adjustable switch 750-125 with respect to the second data word in the event that a double write command is present. As can be seen in the figure just under consideration, this switch receives signals from the instruction queue 750-107 and the processor 700. This means, that when the cache memory 750 issues a read command, the transit block number signals from the Queue 750-107 must be loaded into bit positions 2 and 3 of the RMITS register 750-124.

The transit block number signals are processed by the system interface unit 100 is fed back to the MIFS lines with the read data word. These signals are in an RMIFS register 750-127 via a multi-position switch 750-126 loaded. After that, the content of bit positions 2 and 3 becomes one in two via the first position Positions of adjustable switch 750-128 on two address input connections of the transit block buffer 750-102 submitted. A second DMIPS - <- register 750-129 is used the short-term or intermediate storage of the transit block number signals for multiple word transfers (i.e. for four read commands).

The output signals from the switch 750-128 are also applied to the control input terminals one in four Positions of adjustable ZTBA switch 750-130 issued to select the address signals in question, which are to be applied to the cache memory area 750-3 for storing the data words. Of the Address content of the transit block buffer 750-102

080024/0883

also a number of input terminals of a particular comparator circuit of a group of Comparator circuits 750-132 to 750-135 supplied to there a comparison with the address range of a to make the next command to a second row of input connections of the comparator circuits the RADO / ZADO lines are supplied. The comparison signal generated by a NAND gate 750-136 is on the hold control circuits of block 750-117 are issued.

As can be seen from FIG. 4, the zone bit signals of the ZAC command which are sent to the ZADOB lines 5-8 issued in the case of a single write command or an even word of a double write command is loaded into an RZONE register 750-140 when the write command into the write command data buffer 750-100 is loaded. The output of the RZONE register 750-140 goes to the first position one in two Adjustable ZONE switch positions 750-144 released. The zone bit signals ZDZDO-3, which are sent to the Lines DZDO-3 issued from processor 700 for the odd word of the double write command are loaded into an RDZD register 750-142. The output signal of the RDZD register 750-142 is on the second position of the ZONE switch 750-144 is released. The output signals ZONEO-3 are sent to the circuits of the area 750-9 for the control of the writing of processor data in the cache memory 750-300, as will be explained later.

The cache area 750-3 will now be considered in more detail. This area includes the cache memory 750-300 with 8192 (8K) 36-bit word storage locations in 128 rows are organized by eight eight-word blocks. The unit 750-300 is made up of bipolar memory chips with optional

Q3Q024 / 0883

Access built in a conventional embodiment.

The cache memory unit 750-300 is defined by a 10-bit address RADR 24-33 addressed via any of a number of 4 X 4 crossbar switches (e.g. 750-302a), which are of conventional construction. The addressing takes place address registers associated with the relevant switches. As can be seen from the present figure, the crossbar switch accepts address signals from various sources covering the range 750-5, the ZTBA switch 750-130 and range 750-7. Those occurring at the output of the crossbar switch Address signals are temporarily stored in the associated address register and sent to the address input connections the cache memory unit 750-300.

During one write cycle of operation, the four sets of write control signals (WRT00100-WRT70100 to WRTO31OO-731OO) generated by the area 750-9, to the cache memory unit 750-300 and used for this purpose, clock signals to the write scan input terminals of the memory chips or to deliver them to them. This allows one to four bytes either a data word from the processor 700 via the ZADO / RADO lines or a memory data word from Write area 750-7 into an addressed one of eight levels of cache memory unit 750-300. at Processor data, the write signals are generated by decoding the signals ZONEO-3 from the switch 750-144 will. In the case of memory data words, all zone signals are converted into binary signals 1.

The level in question is determined by the states of the signals RTBLEV0100-2100 from the transit block buffer 750-102

030024/0883

73r 29A9787

set if there is write memory data, and by the hit level, by the address list circuits of block 750-512 is determined when there is write processor data. These signals are through a decoder circuit 750-303 decodes when enabled by a signal ENBMEMLEV100 from the area 750-9 ago.

During a read cycle of operation, the 36-bit word of each of the eight blocks (levels) is asserted as an input delivered a 1-out-of-8 ZCD switch 750-306. The choice of the word in question is made by the states a series of hit level signals ZCD010-210 generated by area 750-5. These signals are delivered to the control input terminals of the ZCD switch 750-306.

As can be seen from the present figure, the selected word is sent to two registers 750-308 and 750-310, to a 1-out-of-8-ZDI switch 750-312 and to a 1-out-of-4-ZIB switch 750-314. the RIRA and RIRB registers 750-308 and 750-310 give their contents to different positions or positions of the ZIB and ZDI switches 750-312 or 750-314. The ZIB switch 750-314 selects commands that are sent to the Command bus (ZlB) of the processor 700 are issued, while the ZDI switch 750-312 data or operands which are output to the data input bus line (ZDI) of the processor 700.

In addition to the output of the command word signals read from the cache memory 750-300, the ZIB switch 750-314 also command word signals that it has received from the area 750-7 to the processor 700. The ZDI switch 750-312 is also there Data signals that he receives from the ZCDIN switch 750-304 and received the range 750-7 to the processor

ÖS0024 / 0883

away. The states of the control signals ZIB010-110 and ZDI010-210, which are delivered to the control input connections of switches 750-314 or 750-312 to select the sources of the commands or data words that are sent to the processor 700 by the relevant switches are to be transferred. The control signals are generated by the circuits of section 750-9.

The signals ZIB010-110 are coded in such a way that the Position no. 2 of the switch 750-314 is selected for a first command transmission, namely to the Determination of an address list hit with regard to an I-fetch 1 command or an address list hit with respect to an I-fetch-2 instruction, which is an I-fetch-1 instruction for the last word in a block follows. The control signals are coded for the RIRA position No. 1 is selected for subsequent command transmissions following an address list hit following a I-fetch-1 or generated in response to an I-fetch-2 command will.

In the case that the I-fetch 1 instruction or the I-fetch two-way instruction leads to an address list dodging, the signals ZIB010-110 are coded to the switch position No. 3 of the ZIB switch 750-314 for the transmission of command words that are included from the range 750-7.

With regard to the ZDI switch 750-312, it should be noted that that the ZCD position no. 1 depending on the determination is selected from address list hits and signals that are sent to the RDIBUF / ZDI line upon occurrence an address list hit that is generated for an LDQUAD command. Storage data words are sent to the processor 700 via the ZDIN position no. 3 of the switch 750-312 following an address

830024/0883

Transfer list avoidance. Following on from holding on of the processor 700 with respect to a command call from the main memory, the signals ZDI010-210 coded to the ZDIN position of the switch 750-312 for select the transmission of the first command to its inclusion by area 750-7. The rest of the orders are transmitted via the ZIB switch 750-314.

The ZCDIN position no. 2 of the switch 750-312 is used for Diagnostic purposes used to transmit signals from the ZADO-B / RADO lines. The remaining Positions or positions of the ZDI switch 750-312 are used for display purposes (these are the positions RIRB, ZRIB and RIRA). In addition, the RIRB position selected to transfer data words to processor 700 in the event of an LDQUAD command, if there is an address list hit there.

The address list and hit control area 750-5 are considered in more detail below. This area comprises an 8-level control address list 750-500 and an address list 750-502 associated with an 8-level set. The address list 750-502 contains 128 memory locations, each of which has a 14-bit associative address for each level contains. A ZDAD switch 750-530, adjustable in four positions, supplies memory addresses for random memory access (RAM) for the purpose addressing the address lists 750-500 and 750-502, in addition to addressing the cache memory unit 750-300.

During an address list lookup cycle, switch 750-530 selects under the control of signals SELZDADCO100-1100 made by the circuits within of block 750-526 are generated, the RADO position 0 off. This makes the 14-bit address signals one ZAC command from processor RADO 24-33

030024 / 0e83

to the output connections of the ZDAD switch 750-530 submitted. These signals are applied to the address input terminals of address lists 750-500 and 750-502. During the search cycle, the content of the eight block / level addresses is read out and sent to each as an input variable Comparator circuit output a group of eight comparator circuits 750-536 to 750-543. Any comparator circuit compares its block / level address with bits 10-23 of the ZAC command to determine if it is present determine a hit or evade condition. Those generated by circuits 750-536 through 750-543 Result signals are sent to the corresponding inputs of a group of AND gates 750-545 to 750-552. Each comparator circuit consists of up to four areas, with the results of these areas in an AND gate of the AND gates 750-545 to 750-552 be combined. The final result hit signals ZHT0100 to ZHR7100 are sent as input signals Hit / fall back network circuits of block 750-512 submitted, as will be explained below.

The ZAC address signals are also in an RDAD register 750-532 retained when no hit condition is detected (i.e. when the HOLD-DMEM from the unit 750-112 is a binary signal 0). During the address list allocation cycle, which is the search cycle follows, in which an evasive state was determined, the signals SELZDADCO100-100 select the RDAD position 1 of the ZDAD switch 750-530. An RDRIN register 750-534 is also used with the 14-bit associative address signals from the ZADO-B lines 10-23 when the address list search cycle for the Writing to the address list 750-502 has ended.

The control address list 750-500 also has 128 memory locations, each of which has a specific number of bit positions for storing control information.

030024/0003

Such information includes the full / empty (F / E) bits for the eight levels and recirculation (RR) count bits in addition to parity check bits (, not shown).

The full / empty bits indicate whether the specified address list addresses have any meaning (i.e. are valid). For a cache hit to occur, the F / E bit appear as a binary 1. A binary 0 indicates the presence of a blank block or space in the relevant area. The circulating bits result in a counter that shows which block was last was replaced. This counter reading is usually when it is over one of the two rows of AND gates the block 750-400 into the register 750-506 is read out is increased by an incrementing adder circuit 750-508. The resulting signals NXTRR0-RR2 are written into the address list 750-500 to designate the next block to be replaced.

As can be seen from the figure just considered, the F / E bit content of the memory location is determined by the position a ZFER selection that can be set in two positions

and
switch 750-506 read / output as an input variable to the address list hit / alternative and hit control circuits of block 750-512. The ZFER switch 750-506 selects which half of a group of F / E bits is to be used by the circuits of block 750-512 for an evasive hit indicator and which half of the group of F / E bits is to be used by such circuits are to be used for another hit determination. An address bit signal ZDAD31 controls the selection of the switch positions.

The circuits of block 750-510 comprise a multi-range multiplexer circuit, which the output signals FEDAT0100 and FEDAT1100 as a function of the hit and Alternate data pattern generated. Accordingly, these become

Signals set depending on the ALTHIT signals of block 750-512. Two decoder circuits 750-520 and 750-521 operate in such a way that they decode the level information signals ZLEV0100-2100, appropriate series of write enable scan signals R / WFE010-210 and R / WLV010-710 for the controller address list 750-500 or for the address list 750-502 to generate. Accordingly, the level (ZLEV) switch 750-522 is operated so that the The level in which the F / E bits are set or reset is controlled, and the level in the address list 750-502 in which new addresses are written during an address list allocation cycle of operation will.

As can be seen from the present figure, in the selected first position of the ZLEV switch 750-522 output the 0LDRR010-210 signals from the address list 750-500. In the selected second position of switch 750-522 are output terminal signals RLEVR0-R2 from a level register 750-524 submitted. The level register 750-524 is used for this, the last row of hit level signals to be retained by the hit / dodge level network circuits of block 750-512 can be generated. This enables the hit level value to be distributed to other areas of the cache memory 750 for subsequent utilization (these are the signals RHITLEVO-2).

In the selected third position of the switch 750-522, the signals from its output connections LEVR0-R2 generated by the circuits of block 750-512. The switch 750-522 is controlled by signals from control flip-flops contained in block 750-526 (that is, the Signals FBYPCAC and DIRBUSYJ. As from the relevant

030024/0883

As shown in the figure, the complement values of the level signals corresponding to the signals RHITLEVO10-210, which are stored in the register 750-524, via a group of AND gates to the control circuits within of the area 750-9.

During the search cycle of operation, the hit / fall-back level network circuits determine which level, if any, contains an address that matches the ZAC address matches. In the event of a match, it will Signal RAWHIT100 occur as binary signal 1, and this becomes the series of hit level signals ZCD010-210 and HITLEVC7010-7210 generated via a coding circuit. The signals are in accordance with the states of the F / E bits signals ZFE010-710 generated. This means that for the purpose of occurrence of a cache hit at a certain level the F / E bit must be a 1 bit. As mentioned above, a binary 0 indicates its presence an empty block level. Each coding circuit includes AND / OR gating circuits of conventional construction the level signals according to the following Boolean

Create expression ~.

Li = _{e = 0} ^ | E _{d = 0} ZHTJ. ZFEj.

In addition, the signals ZCD010-210 can also generated from the level signals ZNICLEVOOO-2100, those through the range 750-9 during command calls to be provided.

The block 750-512 also contains another hit network which is also in the allocation an 8-word block can be used by generating another hit signal ALTHIT100 and by sending a series of signals ALTHITLEV0100-2100 to the Load into register 750-504 is generated instead of the circulation assignment signals C7RR0100-2100. To the Purposes of the present invention can be such

030024/0063

Arrangements are considered to be implemented in a conventional manner. In this context, however to the US-PS 38 20 078 pointed out.

As can be seen in the drawings, the circuits of block 750-512 generate other hit signals HITT0TB100, HITT0C7100 and HITT0IC100. These signals are made up of the RAWHIT100 signal according to the following Boolean expressions derived:

1. HITT0C7100 = RAWHIT100. BYPCACOOO

2. HITT0IC100 = HITT0C7100

3. HITT0TB100 = RAWHIT100 * BYPCA000 + PRERD100.BYPCAC100.

The circuits of block 750-512 take the cache bypass signals BYPCACOOO and BYPCAC100 from block 750-526. As mentioned earlier, contains this block a number of control state flip-flops, the signals to sequentially pass region 750-5 through the various required operations that are used to process the various types of commands. In addition, the block contains 750-512 logic circuits to generate the required Control signals during such operations. For the purposes of the present invention, these Circuits can be carried out in a conventional manner. To simplify the description are therefore here just a brief description and the Boolean expressions relating to certain control state flip-flops and control logic circuits are given insofar as this is necessary for an understanding of the operation of the present Invention is required.

The control state flip-flops are considered in more detail below. The FJAM1 flip-flop will respond to the occurrence a hit state at the end of an address list search cycle for a double read command. The flip-flop

030024 / Ö8Ö3

holds the lower address bits in the register or registers) 750-32, which allows access to the second word from the cache storage unit 750-300 in the Is enabled in the case of a double read command. In addition, the flip-flop reacts to the occurrence of a single write command set to effect the selection of the RRAD position of the ZDAD switch 750-530 so the same address is issued or made available to the cache storage unit 750-500 for another Clock interval or another cycle to be delivered. In the absence of a hold state (.Signal HOLDDMEM = I) the FJAM1 flip-flop remains set for one cycle, in accordance with the following Boolean expression: SET = FJAMI «REQCOMB · RAWHIT.BYPCAC. (. RDDBL + WRTSNG) + HOLDDMBM · FJAM2 + H0LDDMEM · FJAM1.

The FJAM2 flip-flop is triggered for the presence of a hit status at the end of an address list search cycle for a Double write command set. Setting the FJAM2 flip-flop causes the FJAM1 flip-flop to be set at the end of the next clock interval. The control state of the FJAM2 flip-flop together with the FJAM1 flip-flop, the selection of the RDAD position of the ZDAD switch 750-530, to provide the correct address for writing data into the cache memory unit 750-300.

The FJAM2 flip-flop also remains set during one cycle in accordance with the following Boolean expression:

SET = F JAM2 = REQC0MB0 RAWHIT BYPCAC WRTDBL + HOLDDMEM FJAM2.

A flip-flop NRMPTC1 directly controls the ZDAD switch 750-530; it is set in accordance with the states of signals generated by the other control state flip-flops be generated.

030024/0883

29 ^ 9787

The NRMPTC1 flip-flop normally stays during of a cycle in accordance with the following Boolean expression:

SET = NRMPTCI = (WRTDBL REQCOMBO RAWHIT. BYPCAC ¹ ) + FJAM2 + SETFJAM1 + REQCOMBO. (RDTYPE BYPCAC + RDTYP RAWHIT) (FJAM1 FJAM2 + HOLD).

The FDIRASN flip-flop specifies an address list operational allocation cycle, in which an associative address entry in the address list 750-500 in the case of Cache bypass operations alternate states for read commands.

The FDIRASN flip-flop is set for one cycle in accordance with the following Boolean expression: SET = FDIRASN = REQCOMBO RDTYP. (BYPCAC + RAWHIT).

The FICENAB flip-flop enables loading of the instruction register; it will occur for one cycle of a 1/2 T clock pulse according to the following Boolean equation: SET = FHTIOO.

The FRCIC flip-flop is on the occurrence for one cycle of a 1/2 T clock pulse according to the following Boolean expression: SET = FJAMZNICLEV.

The control link signals are considered in more detail below.

1. The ALTHIT signal indicates the presence of a pseudo hit condition.
ALTHIT = ALTLEVO + ALTLEVI + ... ALTLEV7.

2. The signals ALTHITLEVO, ALTHITLEV1 and ALTHITLEV2 form a 3-bit code that specifies the level at which a pseudo-hit condition occurred.

030024/0883

29A9787

The signals are coded as follows:

a) ALTHITLEVO = ALTLEV4 + ALTLEV5 + ALTELV6 + ALTLEV7.

b) ALTHITLEV1 = ALTLEV2 + ALTLEV3 + ALTLEV6 + ALTLEV7.

c) ALTHITLEV2 = ALTLEV1 + ALTLEV3 + ALTLEV5 + ALTLEV7.

3. The signals ALTLEVO to ALTLEV7 indicate which of the eight levels, if any, determined a pseudo hit condition.
aj ALTLEVO = ZHTO-ZFeO.

b) ALTLEV7 = ZHT7'ZFE7.

The DIRADDE signal is an enable signal for the Decoder 750-521, which enables the generation of write strobe signals to be sent to the address-address list 750-500 are delivered. FDIRASN.

5. The DIRBUSY signal indicates when the address lists 750-500 and 750-502 are occupied. DIRBUSY = FLSH + FJAM2 + FJAM1 + FDIRASN.

6. The FEDCODE signal is an enable signal for the Decoder 750-520, which enables the generation of write strobe signals which are sent to the control address list 750-500 are delivered. FEDCODE = FDIRASn · NÜGÖ ".

7. Dae FORCEBYP signal indicates the flow of a cache bypass operation free. FORCEBYP = FSKIPRRfFBYPCAC.

Θ. The GSRCH signal indicates when a search duty cycle should occur.
GSRCH = RDDBLZCDE FICENAB FRCIC.

03002A / 068 3

9. Form the signals HITLEVC70, HITLEVC71 and HITLEVC72 a 3-bit code specifying the level at which a hit condition occurred.

a) HITLEVC70 = HITLEV4 + HITLEV5 + HITLEV6 + HITLEV7.

b) HITLEVC71 = HITLEV2 + HITLEV3 + HITLEV6 + HITLEV7.

c) HITLEVC72 = HITLEV1 + HITLEV3 + HITLEV5 + HITLEV7.

10. The signals HITLEVO through HITLEV7 indicate which of the eight levels, if any, have a hit condition has determined.

a) HITLEVO = ZFEO-ZHTo.

b) HITLEV7 = ZFE7 * ZHT7.

11. The RAWHIT signal indicates the detection of a hit condition.

RAWHIT = HITLEVo + ... + HITLEV7.

12. The signals HITT0C7 and HITTOIC each show the Determination of a hit condition for certain circuits within the range 750-9. HITT0C7 = HITT0IC = RAWHIT.BYPCAC.

13. The HITTOTB signal indicates the detection of a hit condition or a pre-read command, if work is carried out in bypass or bypass operation for the transit block buffer circuits.

HITTOTB = RAWHiT.BYPCAC + PRERD · BYPCAC.

14. The LDRAD signal indicates the loading of the RDAD register 750-532 free.

LDRDAD = HOLDDMEM.

03GÖ2WÖ883

15. The LDRDRIN signal indicates the loading of the RDRIN register 750-53 ^ free.

LDRDRIN = FDIRASn.

16. The RDDBLZCDE signal is used, the ZCD switch 750-306 in the event of a double read command to release.

RDDBLZCDE = FICENAb.tFDIRASN + FJAM1 + FJAM2).

17. The REQCOMBO signal indicates the presence of a Cache request.

REQCOMBO = IiUSU. HOLDDMBM CANCELC. DREQCAC

18. The signals ZCDO, ZCD1 and ZCD2 are used to control the operation of the ZCD switch 750-306 steer.

a) ZCD0 = ZCDL4 + ZCDL5 + ZCDL6 + ZCDL7 + ZNICLEV0.

ZCDICENAB + RDDBLLO.

b) ZCD1 = ZCDL2 + ZDEL3 + ZCDL6 + ZCDL7 + ZNICLEV1

ZCDICENAB + RDDBLL1.

c) ZCD2 = ZCDL1 + ZCDL3 + ZCDL5 + ZCDL7 + ZNiCLEV2.

ZCDICENAB + RDDBLL2

the respective expression ZCDLi is given by ZCDLEVi.

19. The ZFEDATWT1 signal is a data write strobe signal, that for writing the F / E bit signals FEDAT0100 and FEDAT1100 into the address list 750-500 serves.

ZFEDATWT1 = FE1RASN · ZDAD31.

20. The FEDATOIOO signal corresponds to the first full / empty bit.

FEDAT01OO = FBYPCACOOO + FALTHIT100.

21. The FEDAT1100 signal corresponds to the second

030024 / Ö881

Full / empty bit.

FEDAT110O = FALTHITI00 + FBYPCACOOO.

22. The SELZDADC1 signal controls the operation of the ZDAD switch 750-530.

SELZDADCI = NRMPTC1.

23. The RWRR signal is a circular write signal which is used to rewrite the RR bit signals in the address list 750-500.

RWRR = FDIRASN NÖGÖ.SCLOCK.

It should be seen from the drawings that the various decoded command signals are generated by decoder circuit 750-528 in response to the occurrence of signals provided by processor 700 on DMEM lines 0-3. The decoder 750-528 is enabled by a signal from the DREQCAC line. The decoded command signals (e.g., WRTDBL, WRTSNG, PRERD, RDTYPE ) are provided as inputs to the circuits of block 750-526 along with other control signals such as the HOLDDMEM, FSKIPRROO and those signals on the CANCELC and BYPCAC lines.

The instruction buffer area 750-7 is explained in more detail below. This area takes memory data and commands from the DFS lines that lead to the processor 700 via the ZDI switch 750-312 or the ZIB switch 750-314. The memory signals are stored in an RDFS register 750-702 via a position of a switch that can be set in two positions 750-700 loaded.

The storage data, which as a result of a faulty state or alternate state to corresponding

030024/0083

29A9787

Admission to be picked up at the ZDI counter 750-312 via the RDFS position no. 0 of a 1-out-of-A position r (ZDIN) switch 750-708 delivered. In the case of a four-load command, the save data is stored in the quad space (LQBUF) buffer 750-706 is loaded, when the signal LQBUF occurs as logic signal 1. The read / write address signals WRTBUFO10-110 / RDBUF010-110 from the area 750-112 control the writing and reading of data to and from the Storage locations of the buffer 750-706.

The memory data stored in the LQBUF buffer 750-706 is then transferred to RLQBUF position # 2 of the ZDIN switch 750-708 transferred to the ZDI facility.

In the event of a double read command, the even-numbered word of the word pair is stored in a REVN register 750-710 transferred. Then the even-numbered word is sent to the ZDI switch 750-312 via position no. 1 of the ZDIN switch 750-708 for execution an odd double read command request or the inclusion of an RD-EVEN signal from the processor 700.

As can be seen from the drawings, each memory data word is also loaded into RDFSB register 750-712 and then written into the cache memory unit 750-300 via the ZCDIN switch 750-304, namely in the Level specified by the contents of the RADR register 750-32.

In the case of instruction or command transfers, each command recorded from the memory in one of the four memory locations of a specified (IBUF1 / IBUF2) Command buffer of two command buffers 750-715 and 750-717

030024/0883

loaded. The IBUF1 and IBUF2 buffers 750-715 and 750-717 are used to buffer up to two four-word blocks that are accessed from the Memory can be obtained, namely on I-Abruf-1- or I-fetch-2 instructions for which an alternate condition has been determined.

The commands are written into the memory location of one of the IBUF1 and IBUF2 buffers 750-715 and 750-717. The buffer in question is controlled by the WRTBUFO100-1100 signals under the control of write strobe signals IBUF1 / IBUF2 specified. The read control signals RDBUF0100-1100 read out such commands free for transmission to the processor 700 if the memory location IBUF1 or IBUF2, which is determined by the signals ZEXT0100-1100, contains an instruction. The command is sent to the processor 700 via the Position 1 or 2 of a switch 750-720 that can be set in two positions and via the ZRIB switch position of a ZIB switch 750-314.

The IBUF1 and IBUF2 buffers give 750-715 and 750-717 valid output signals IBUF1V100 or IBUF2V100 to the IBUFREADY circuits of block 750-722. These Circuits drive the IBUFRDY line to binary 1, indicating that at least a command is addressed in the I-buffer (present command block). As can be seen from the drawings, take the IBUFREADY circuits input signals (for example USETBRDY, IFETCHRDY) from the control circuits within of the range 750-9.

The instruction counter area 750-9 is explained in more detail below. This area stores cache address signals (24-33) to indicate the next command to be accessed. This storage takes place in one of two command address registers

03002 ^ / 0803

(RICA / RICB) 750-900 and 750-902. The cache address signals 24-33 are loaded into the RICA / RICB instruction register, which is not used when an IFETCH1 instruction received from processor 700 will. The cache memory address is set via the RIDO position of the ZDAD switch 750-530 and via a ZDAD position no. 0 one adjustable in four positions ZICIN switch 750-904.

Whenever the processor 700 accesses an instruction, the contents of the instruction register RICA / RICB, which has one position of the ZIC switch 750-906 is read, increased by 1 by means of an incrementing circuit 750-908. The increased content is in the command register RICA / RICB is returned via the RNIC position no. 1 of the ZICIN switch 750-904.

As can be seen from the drawings, each instruction register stores two level fields, first and second Fetch command blocks upon occurrence of the IFETCH1 and IFETCH2 commands. The two pairs of plane field signals are set to different switch positions one in four positions Crossbar switch 750-910 released. The selected Level signals ZNICLEV0100-2100, which are used as input signals are sent to the block 750-512, are used to control the operation of the ZCD switch 750-306, to access the instructions specified by the RICA / RICB instruction register. The plane field signals correspond to the signals HITLEVC70100-2100, generated by the circuitry of block 750-512. These signals are stored in one of the command registers loaded onto an address list arbitrator s cycle out.

030024/088 ^

Ml

the

In addition to the level field signals, the RICA and RICB instruction address registers store other signals, which are used for various control purposes, to the extent required below is received.

The ones arriving from the ZDAD switch 750-530 Cache memory address signals are incremented by 1 by means of a further incrementing circuit 750-912. the increased or incremented address signals are activated via the INC position no. 3 of the ZICIN switch 750-904 loaded into the RICA / RICB command register. The two Least significant bits 32-33 of the cache memory address form the IBUF1 or IBUF2 address (these are the signals ZEXTO100-1100) to read command blocks from the memory to which an access has been made.

It should be noted that the two level field signals LEV1 and LEV2 from other outputs of the switch 750-910 are given as input signals to two comparator circuits 750-912 and 750-914. the Circuits 750-912 and 750-914 compare the level signals LEV1 and LEV2 of the current command block from the switch 750-910 with the input level signals C7RR0100-2100, which correspond to the circulation counter setting for the next available block. The comparator circuit also takes 750-912 as inputs the memory level signals RTBLEV0100-2100 and the command level signals ZNICLEV0100-2100 from the Switch 750-910 forth to make a comparison in addition to the comparison with the level signals ZIC0100-2100 with the signals C7RR0100-2100. The cache address signals are incremented by four by an increment circuit 750-918 and as inputs to wraparound jump control circuits of the block 750-916 delivered. These circuits take the input cache memory address as a further input signal pair.

030024/0683

signals 24-30 from the ZDAD switch 750-530 and the Cache address signals of the current instruction block from the ZIC switch 750-906, to make a comparison through the existing circuits.

The results of the signal pair comparisons of the cache address signals and the level signal are combined or linked in further circuits that included in the wrapper jump control circuits of block 750-916. Generate the circuits of block 750-916 on the occurrence of the decoded signals from a decoder circuit 750-922 output control signals, which avoid address conflicts. A further explanation of the operation of such circuits can be found in other place mentioned at the beginning.

The output control signals of block 750-916 are provided as inputs to the circuits of IC control block 750-920. In addition, the control circuits of block 750-920 receive the result signals of the decoding of the command signals which are output by the decoder circuit 750-922 to the DMEM lines when this circuit is enabled by a signal from the DREQCAC line. Along with the other signals from areas 750-1 and 750-5 to block 750-920, the control circuits of block 750-920 generate address and control signals for flow area 750-9 over the required operating cycles to accommodate certain types of instructions to process (for example the commands IFETCH1, IFETCH2 and LDQUAD).

The block 750-920 contains a number of control state flip-flops and logic circuits for generating the required control signals. From the same

030024/0883

CX) PY

Reasons mentioned in connection with the area 750-5 will only be a brief explanation and given the Boolean expressions relating to certain state flip-flops and control circuits.

The control state flip-flops are considered in more detail below. The FABCURLEV1 flip-flop defines the straight present level for the RICA / RICB command register. This flip-flop is triggered on the occurrence of a T clock signal in accordance with the following Boolean expressions set or reset. The set state corrects the reset state. When the FA / FBCURLEV a binary signal is 1, then level 1 is selected, and if the signal in question is a binary signal 1, then level 2 is selected.

SLT ·· DECUDEIFI-F-PPIMEIs- [HOLDDMEM- [CANCELC-ZDAuO8-ZDALiO9 · UIT-FACTVRICIOO / OOO + ZEXTO i; EXTl RDIBUF-IIOLDEXECRDIBUF-FA / FBCURLEVOOO-

ULCOLELDQUAD · FLDQUAD · DECODEEIS · FACTVRICIOO / OOO · NUbU + ZEXTO · ZEXTl · FLDQUAD · RDIBUF · HÖLDEXECRDIBUF • FACTVRIClOO / OOO -NÖGÖ.
RESET- DECODEIFl · PPPiMEIS · (HOLDDMEM · [CANCELC · FACTVRICIOO / OOO + DECODELDQUAD · (HÖLDDMÜM · [CANCELC-FACTVRICIOO / OOO + ZEXTO-ZEXTl-DECODELDQUAD.FLIBDQUAD- DECODELDQUAD.FLIBDQUAD- DECODEIFL. Lower Austria ".

030024/0083

OOPY

The FACTVRIC flip-flop defines the currently active command register RICA / RICB. When the flip-flop is set to the 1 state, the RICA register is specified; if the relevant flip-flop is set to the zero state, the RICB register is designated. The relevant flip-flop is set or reset in response to the occurrence of a T clock pulse signal in accordance with the following Boolean expressions.

FACTVRIC »FACTVRIC-TGLACTVRIC TGLACTVRIC - DECODEIFl "THOLDDMEM- [CANCÜLC ·

FTPIMEIS + FNEWIFl-NOGO. FACTVlUC = FACTVRIC * TGLACTVRIC

TGLACTVRIC = (DEC0DEIF1 + [HOLDDMEM + [CANCELC + FFPIMEIS) * (FNtWIF1 + NÖ "CO).

The FCPUWRTREQ flip-flop sets the time period or the Set the time during which processor data are to be written into the cache memory. That in question Flip-flop will respond to the occurrence of a T clock pulse in accordance with the following Boolean expressions set or reset

SET «(DECODEWRTSNGL + DECODEWRTDBL) -HIT-THOLDDMEM

[CANCELC.

RESET- FWRTDUL-HÖLDCÄCHECPUWRTSEQ.

The FDBLMISS flip-flop defines a double read fallback state; the ZDIN position of the ZDI switch 750-312 during the cycle is used for this purpose that follows the data recovery. The flip-flop in question will respond to the occurrence of a T clock pulse out in accordance with the following Boolean expressions set or reset.

03002 ^ / 00 0 3 QOPY

SET =

(DECODKRDDBL + DECODEHDRMT) · [HOLDDMEM-

[CANCELC-MISS.
RESET * FRDMISS.

The FEVENODD flip-flop determines which word of the two word pair processor 700 is waiting when a single read fallback condition occurs. The flip-flop also determines the order in which the data words to processor 700 in the event of a double read fallback condition.

In addition, the flip-flop will turn off during a double read hit condition used to access the second data word. This flip flop is on the occurrence of a T clock pulse in accordance with the following Boolean expressions are set or reset,

.SET = (DECODERDCNGL + DECODEIFl. FFPIMEIS) [HOLDDMEM ". [CANCELi-ZDADOQ + DECODERDDBL ·

ιHOLDDMEM JL AWCZLC DSZ1.
RESLT- (DECODERDSNCL + DECODEIFl) IHOLDDMEM.

[CANCELC · ZDAD09 + DECODERDDBL · [HOLDDMEM · [CANCELC-DSZl + DE CO DE RDRMT · IHOLDDMEM · [CANCELC.

The FFPIMEIS flip-flop specifies that the last processor state was an FPIMEIS state, meaning that the IF1 command on the DMEM lines was a request after additional EIS descriptors. This flip-flop is triggered upon the occurrence of a T clock pulse set or reset according to the following Boolean expressions.

030024/0683

SET = FPIMEIS.

RESET = DECODEIFI. CANCELCHOLDDMEM.

The FH0LDIF1 flip-flop determines when the processor 700 is held due to the presence of an IF1 evasive state, so that when the command is received from the Store the register RICA / RICB used for the present instruction updated by the FDATARECOV flip-flop can be. The flip-flop becomes according to the following Boolean when a T clock pulse occurs Expressions set or reset. SET = DECODEIFI IFPIMEIS.HOLDDMEM.CANCELC.MISS. RESET = FNEWIFI.NOGO + FDATARECOV.

The FINHRDY flip-flop is used to signal an IBUFRDY state to the processor 700 to lock if there is a conflict between the command (IC) level and the memory data level at the time Z "to which the processor 700 has taken over the command, which is loaded from the cache into the register RIRA / RIRB has been. The flip-flop in question is set upon the occurrence of a T clock pulse and it will on the occurrence of the next T clock pulse set if there is no set status. The setting is made in accordance with the following Boolean expression.

. '• ΚΙ · - * SET I RTERm · ukam .ι mim · ¹ · ΓποϊΤ) ΠΜΠΜ · ΝΟδο. wherein üktiktlhm * · cmpuataicj.kv ♦ MfiMWRTrtEQ-

\ ZtXTO · ZEXTl · IF2 · TCÄTJCELCMD + DECODEIFl · FFPIMEIS + FINHRDY). RESET = »SET.

The FJAMZNICLEV flip-flop is used to generate the level signals ZNICLEVOOO-2100 of the next command to the control input connections of the ZCD switch 750-306 (these are the signals ZCD010-210), in response to the occurrence of an IF1 instruction which did not designate the last word in the block. That Flip-flop is activated upon the occurrence of a T clock pulse in accordance with the following Boolean expression set; it is reset upon the occurrence of the next T clock pulse. SET = DEC0DEIF1.FFPIMEIS.HIT.HOLDDMEM.CANCELC CANCELC (ZDAD08 · ZDAD09).

The FNEWIF1 flip-flop defines the cycle after which one IF1 command from processor 700 is received. The relevant flip-flop is activated for one cycle on the The occurrence of a T clock pulse is set in accordance with the following Boolean expression: SET = DEC0DEIF1 FFPIMEIS.HOLDDMEM.CANCELC.

The FRDIBUF flip-flop is used to determine that a signal is on the RDIBUF line from the processor 700 ago during the last cycle of operation. This flip-flop is made in accordance set with the Boolean expression given below; it will be during the next cycle reset in the absence of a set status. SET = RDIBUFc HOLDEXECRDIBUF.iJÖGÜ.

The FRDMISS flip-flop is used to hold of the processor 700 to cause an alternate condition to be determined with respect to any read command. This flip-flop is activated upon the occurrence of a T clock pulse in accordance with the following Boolean expressions set or reset.

Ö3002A / 0883

29A9787

SET = (DECODERDSNGL + (DECODEIFl-FFPIMEIS) + DECODERDRMT + DECODERDCLR + DECODERDDBL) - [HOLDDMEM- [CANCELC-MISS.

RESET = FDATARECOV + FNEWIFl-NOGO.

The FRDREQ flip-flop determines when the second on one an RDDBL instruction is to read out a word called for a hit status from the cache memory. The flip-flop in question is activated in response to a T clock pulse in accordance with the following Boolean expressions set or reset. SET = DECODERDDBL Hi T.HOLDDMEM CANCELC.

RESET = HOLDDMEM.

The FDATARECOV flip-flop disables the RICA / RICB command register from being incremented if the IF1 command for the last! ”Continues in the block and if the IF2 command is cleared. The relevant flip-flop is set or reset in response to a T clock pulse in accordance with the following Boolean expressions:

SET «DATARECOV-FLASTINST- [HOLDDMEm- [CANCELC + DATARECOV • FLASTINST · [CANCELC- [HOLDDMEM ♦ DATARECOV FLASTINST.

RESET = [HOLDDMEM- FDATARECOV.

Q30024 / 0S83

The control link signals are considered in more detail below.

1. The FA / FBLEV1VAL signal is used to determine the state of a first valid bit position of the RICA / RICB command register. This flip-flop is set or reset in response to a T clock pulse in accordance with the following Boolean expressions. The reset state corrects the set state.

a. FA / FBLLV1VALSET ■ = ÜLCODEIFl · FFPIMEIS · IHOLDDMEM-

[CANCELC · FACTVRICl00 / 000 + DECODEIFl

• FFPIMEIS- IHOLDDMEM- [CANCELC · EISTfT-FACTVRICOOO / IOO + DECODELDQUAD

• [HOLDDMEM [CANCELC FACTVRIC100 / 000.

b. FA / FBLEVIVAIRESET = DECODEIFl-FFPIMEIS IHOLDDMEM

TCÄNCELC · HIT «ZDADO8 · ZDADO9 · FACTVRIClOO / 000 + ZEXTO * ZEXTl-DECODEIFl · DECODELDQUAD · FLDQUAD-RDIBUF-HOLDEXECRDIBUF · FACTVRICOOO / .lOO-FA / FBCMPLEVOOO-FföSO + ZEXTO-ZEXTl-FLDQUAD-RDIBUF · HOLDEXECRDIBUF • FACTVRICIOO / OOO No7! Ö \

where RICA = FACTVRIC = 1 and RICB = FACTVRIC = 1. 2. The FA / FBLEV2VAL signal is used to determine the state of a second valid bit position of the RICA / RICB command register. This flip-flop is set or reset in response to a T clock pulse in accordance with the following Boolean expressions, a. FA / FBLEV2VALSET ■ DEC0DEIF2 · IHOLDDMEM- [CANCEL «! ·

FACTVRICOOO / lOO-NöGö + DECODEIFl · FFPIMEIS-IHOLDDMEM- [CANCELC · FACTVRIC000 / 100-EISIF2.

03002 ^ / 0883

b. FA / FDLLV2VALRESET = DECODEIFl · FFPIMEIS · [HOLDDMEM ·

[CANCELC • FACTVRIC100 / 000 +

DECODELDQUAD .Tk ^- OLDdTuEm- [can ce lc

• FACTVRICIOO / OOO + ZEXTO-ZEXTl-DECODEIF1-DECODELDQUAD · FLDQUAD · FA / FBCURLEV-FACTVRICOO0 / 10O

RDIBUF-HOLDEXECRDIBUF-NOGO.

where RICA = FACTYRIC = 1 and RICB = FACTVRIC = 1.

3. The signals ZIBO and ZIB1 control the ZIB switch for instruction transfers from cache 750 to processor 700 over the ZIB lines. a. ZIBO = IFETCHRDYcPNEWIFI.

b. ZIB1 = IFETCHRDY.

4. The ZDIO, ZDH and ZDI2 signals control the ZDI switch for instruction transfers and data transfers from cache memory 750 to processor 700 over the ZDI lines. A binary unless items 4 to 7 are used for display purposes. a. ZDH = DATARECOV + FEBLMISS + RDEVEN.

b. ZDI2 = RDIBUF / ZDI. (HITTOIC + FRDREQ).

5. The signals ZICINO and ZICIN1 control the ZICIN switch, to address signals in the RICA or RICB command address register 750-900 or 750-902 to load.

a. ZICINO = ALTCHMD100 FDFN2HT HOLDDMEM.

b. ZICIN1 »FDFN1HT-FNEWIF1 + FDFN2HT.

6. The signals ENABRIC1 and ENABRIC2 are used to enable the loading of the registers RICA and RICAB.

Oä0024 / ÖÖ83

ο. KNABHICl «FllCLD ?: FI-FNEWi Fl-l \ J AMZNICLEV-

[HOLDDMEM · FDATARECOV + FHOLDIFl · OATARECOV.

b. ENABRIC2 »FINHRDY · SETINHRDY · DFN2HT wherein SETINHRDY - DFN2T · [MEMWRTREQ

(ZEXT0-ZEXT1-EXECIF2- [CANCLCMD + FlNHRD Y. + PSUEDOIFl + PSUED0IF2) + CMPDATA / ICLEV].

7. The DATARECOV signal defines the point in time at which new data was loaded into the registers of the processor (e.g. RDI or RBIR) and for which the processor is enabled. This signal is generated by a flip-flop of the Area 750-1 is generated which is set to binary 1 when a T clock pulse occurs and a identical correspondence between the address signals designating the word which is to be accessed by the processor 700 is requested and the signals are present which identify the word which is in the cache memory unit 750 is transmitted. The comparison indicates that the signals DATA, MIFS2, MIFS3, MIFS1 and DATAODD are identical to the signals FHT, FHOLDTBO, FHOLDTB1, RADR32 or DOUBLEODD, whereby the following relationships apply

where signal FHOLDTBO = FRDMISS-LDTBVALID-

-FIF2ASSIGN-FTBPTRO; Signal FHOLDTBl = "FRDMISS · LDTBVALID-

FIF2ASSIGN · FTBPTRl;

Signal DOUBLEODD * FEVENODD-FDPFS; and. Signal DATA «FARDA + FDPFS.

030024/0883

-Λ $ 9

Area 750-1 will now be described in detail.

Various blocks of the blocks of area 750-1 are illustrated in more detail in FIG. 7a. It should be noted that for the purpose of facilitating understanding of the present invention the same reference numerals are used again as far as possible for corresponding elements in FIG. 4. In many cases a single block indicated in FIG. 4 comprises several groups of circuits for Control of their operation and / or to generate associated control signals. That's why some blocks with the appropriate reference numerals provided as part of the various blocks of area 750-1.

As can be seen from the drawings, certain areas of block 750-102 are in more detail shown. As shown, the transit block buffer 750-102 comprises a first group of circuits, the data words have ready that have been received from the memory on the occurrence of a four-way read command are. These circuits comprise a plurality of clock-controlled pairs of counting flip-flops which have a Four-bit register 750-10200, a multiplexer circuit 750-10202, a plurality of NAND gates 750-10204 to 750-10210 and a decoder circuit 750-10212. It should be noted that a counting flip-flop pair is provided for each transit buffer point.

In addition, the first group of circuits includes a plurality of clock-controlled transit block validity flip-flops, which form a 4-bit register 750-10214. The 1 outputs of the flip-flops are each with connected to a corresponding flip-flop of the four pairs of counting flip-flops, as shown.

Depending on the occurrence of a four-read command

030024/0083

a first pair of words is sent to the cache 750 sent out. This is followed by a gap, and then a second pair of words is added to the Cache memory 750 sent out. On the transit block buffer space associated pair of counting flip-flops are referred to by specifying by the states of the signals MIFS2110 and M1FS3110 takes place, this flip-flop then in the binary state 1 via a first AND element with the occurrence of T clock signal CLKT022 is asserted when the signal DATA0DD100 is output as binary signal 1 by the circuits of block 750-114. The RESETTBV100 signal is first a binary signal 0, and the decoder circuit 750-10212 gives one of the first four output signals SETPC0100 to SETPC3100 in agreement with the states of the signals MIFS2110 and MIFS3110 from switch 750-128.

The pair counting flip-flop is in the binary state 1 over the other input-side AND element held by a transit block validity signal, which occurs as binary signal 1. The associated one flip-flop of the transit block valid bit flip-flops, which is designated by the decoder circuit 750-10601 (these are the signals IN0100 to IN3100), is via a first AND element is then set to the binary state 1 when a switchover takes place to the INCTBIN100 to be converted into a binary signal 1 upon the occurrence of a T clock signal CLKT022.

Multiplexer circuit 750-10202 selects in accordance with the states of signals DMIFS2100 and DMIFS3100 from switch 750-128 the binary signal in question 1 of the four pair counting flip-flops to deliver it to the NAND element 750-10204. As a result, the NAND gate 750-10204 gives the signal LAST0DD100

030024/0883

as a binary signal O. This leads to the NAND gate 750-10206 outputs the signal LASTDTA0DD000 as binary signal 1.

When the next pair of data words is received, this causes NAND gate 750-10206 to signal LASTDTAODDOOO to be output as binary signal 0. This in turn causes the NAND gate 750-10210 to issue the reset signal RESETTBV1100 to be output as binary signal 1. The decoder circuit 750-10212 is activated by the signal RESETTBV100 causes a binary signal 1 to be output at one of the four output terminals 4 to 7. This in turn becomes that A flip-flop in question of the transit block validity bit flip-flops is reset via the other AND element. Once the TB validity flip-flop is reset it translates the paired counting flip-flop belonging to it its other AND element back. It should be understood that such a switch to the occurrence of the T clock signal CLKT022 takes place.

As can be seen from Fig. 7a, the first group of circuits of block 750-102 also includes a plurality from NAND gates 750-10216 to 750-10222, each of which is connected in such a way that it has a different output binary signal 1 from register 750-10214. The binary 1 output signals FTBV0100 to FTBV3100 are also the control input terminals of the transit block address comparator circuits 750-132 to 750-136 supplied.

The NAND gates 750-10216 through 750-10222 are also like that switched so that they each have a different signal of the signals IN0100 to IN3100 from the decoder circuit 750-10601 record here. The output signals of these logic elements are fed to an AND element 750-10244. the Signals VALIDOOO to VALID3000 are used to provide an indication when a transit block register location is available for a write operation.

030024/0883

29A9787

This means that if a selected transit block valid bit flip-flop is in the reset state, the AND gate 750-10224 the signal VAL1D1N000 as a binary signal 1 maintains.

The VALIDINOOO signal creates a further AND / NAND element 750-10226 causes a control signal RTB100 as binary signal 1 during the second half of an operating cycle (this is the signal FHT020 as binary signal 1) in Case of a read command (which means that the signal DREQREAD100 occurs as a binary signal 1) at the time to which an address list allocation is not made (that is, the signal FLDTBVALIDOOO occurs as binary signal 1).

As can be seen from Fig. 7a, the control signal RTB100 output via a driver circuit 750-10228 to a decoder circuit 750-10230. The control signal RTB110 causes the decoder circuit 750-10230 to produce a candidate output of the RTB0100 output signals to RTB3100, namely the output signal which is determined by the states of the signals FTBPTR0100 and FTBPT1100, which are output via two driver circuits 750-10232 and 750-10234. That in question The above-mentioned output signal then appears as a binary signal 1. This in turn sets the bit positions 24-31 one of the transit block register locations is loaded with address signals which are supplied via the RADO lines 24-31 will. The complement signal RTBOOO is provided as an input to block 750-107 to facilitate loading the command queue 750-107.

A second group of circuits of block 750-102, as illustrated in detail, includes the Transit block buffer identifier storage area 750-10238 of the buffer 750-102. This area as well as the area of the

030024/0803

Buffer 750-102 (not shown) consists of a simultaneously operated 4 × 4 double read / write memory. The memory is a 16-bit memory organized in four words of four bits each only three bits are indicated. The words can be taken independently from any two memory locations can be read at the same time that information is written in any memory location will. The FTBPTR0100 and FTBPTR1100 signals are applied to the write address terminals while the Read addresses are enabled by the VCC signal, which is applied to the connections G1 and G2. the Y-bit locations are allocated in accordance with the states of the read address signals MIFS3100 and MIFS2100 from the Switches 750-128 selected. The Z-bit places will be in accordance with the states of the signals DMIF3100 and DMIF2100 is selected by switch 750-128. Since these places aren't important, they won't be here further explained.

The memory can be of conventional construction and, for example, take the form of the circuits indicated in US Pat. No. 4,070,657. In response to the recording of memory data, the flag bit content of the transit block location, which is identified by the signals MIFS2100 and MIFS3100, is output to the Y output connections. These signals are in turn provided to blocks 750-102, 750-115 and 750-117 as illustrated. During the address list allocation cycle for a cache read fallback, the flag bit positions of the transit block location, identified by the signals Fi ¹ BPTROIOO and FTBPTR1100, are loaded with the signals FORCEBYPOOO, FRBQUAD100 and FLDQUAD100 which are generated by the circuits of blocks 750-5 and 750- 114 can be generated.

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Also referring to Figure 7a, block 750-102 also includes a set of command call flag circuits associated with the operation of the transit block buffer 750-102. These circuits include two sets of input AND gates 750-10240 to 750-10243 and 750-10250 to 750-10253, two multiplexer selection circuits 750-10255 and 750-10256, an IF1 register and an IF2 tag storage register 750-10258 and an output multiplexer circuit 750-10260. These circuits are shown in FIG Arranged way.

The binary output signals 1 of the individual IF1 and IF2 flip-flops are corresponding AND gates of the Rows of AND gates 750-10240 to 750-10243 and 750-10250 to 750-10253 are supplied. These AND terms also receive inputs from the circuits of block 750-106 responsive to the occurrence the input pointer signals FTBPTROOOO and FTBPTR1000 are generated, which are used to address the various Register locations within the buffer 750-102 are used, as has already been mentioned above.

The multiplexer circuit 750-10255 is connected so that that they use the signal FIF1ASSIGN100 as the control input signal from the FIFIASSIGN flip-flop 750-1418. The multiplexer circuit 750-10256 is connected in such a way that it uses the FIF2ASSIGN100 signal as a control input signal from the FIF2ASSIGN flip-flop 750-1410 picks up. This enables the setting and / or resetting of the flip-flops IF1 and IF2 of the register 750-10258 for the occurrence of the signals FIF1.ASSIGN100 or FIF2ASSIGN100. Switching takes place on the occurrence of the T clock signal CLKT022 while loading a transit block register location, if the control signal LDTBVALID100 via an AND gate 750-11428 is output as binary signal 1.

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It should be noted that register 750-10258 has an IF1 flag bit location and an IF2 flag bit location for each transit block register location. This means that the register flip flops FIF10, FIF20 to FIF13, FIF23 for the transit block register locations 0 to 3. Any of the binary 1 outputs of the IF1 and IF2 flag flip-flops is also fed to different input terminals of the output multiplexer circuit 750-10260. The circuit 750-11450 contains two areas. This enables the signals DMIFS2100 and DMIFS3100 to be sent to the Output control connections of the multiplexer circuit 750-10260 from the block 750-128 in order to be used as output or output. Input signals Signals from both an IF1 flag flip-flop and a 1F2 flag flip-flop to select. The selected signal pair in turn causes flag signals ZIF1FLG100 and ZIF2FLG100 which are passed to block 750-115. These signals become so used, the writing of a memory information into the IBUF1 and IBUF2 buffers 750-715 and 750-717, respectively steer. In addition, the complementary signals of the output signals of the multiplexer circuit 750-10260, which correspond to the signals ZIF1FLGOOO and ZIF2FLGO00, two input terminals of a multi-range comparator circuit 750-110 / 750-11435.

It should be noted that the last portion of each of the multiplexer circuits 750-10255 and 750-10256 in FIG Is connected in series to generate the enable transit block buffer ready signal ENABTBRDY100, which is passed to block 750-114. As shown, becomes the "0" input terminal of the last area the multiplexer circuit 750-10255 is supplied with a voltage VCC (which is indicative of a binary 1), while the "1" input connection to earth

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connected (which is indicative of a binary O). The output terminal of the last section of the multiplexer circuit 750-10255 is connected to the "0" input terminal of the last section of the multiplexer circuit 750-10256 while the "1" input terminal is connected to ground. The multiplexer circuits 750-10255 and 750-10256 work in such a way that the signal ENABTBRDY100 is a binary signal 1 is only issued after the end of an instruction call allocation cycle if the two signals FIF1ASSIGN100 and FIF2ASSIGN100 occur as binary signals 0. That's why the signals at the "O" input terminals are used as output signals from the multiplexer circuit 750-10255 and 750-10256 are selected, which results in the ENABTBRDY100 signal being output as a binary 1 signal. this illustrates the inadvertent generation of the IBUFRDY100 signal as explained here.

As can be seen from FIG. 7a, the circuits of the transit buffer in the pointer block 750-106 contain a clock-controlled one 2-bit register 750-10600 and a decoder circuit 750-10601. The register 750-10600 are a NAND / AND gate 750-10602 and a two-input AND / OR gate 750-10604 associated therewith; these Logic elements are connected to one another in a counter arrangement. This means that the NAND gate 750-10602 for the occurrence of a load signal FLDTBVALID111 from the block 750-114 and for the occurrence of the signal N0G0020 emits an incrementing signal INCTBIN100 as binary signal 1. This will put the in the register 750-10600 stored address value incremented or increased by 1. The increased signal INCTBIN100 is on the circuits of block 750-102 are delivered.

The highest value bit position of the register 750-10600 is set via the gating element 750-10604 set to binary 1, either on

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the occurrence of the signals FTBPTR0100 or on the appearance of the signals FTBPTR0100 / and FTBPTROOO as binary signals 1. The complementary binary 1 output signals of the register bit positions that represent the Signals FTBPTROOOO and FTBPTR1000 will correspond decoded by the decoder circuit 750-10601. This decoder circuit 750-10601 indicates the occurrence of the Signals FTBPTROOOO and FRTBPTR1000 send a binary signal 1 to one of the four pairs of output connections away.

Command control circuit block 750-114 includes a synchronously operated command call 2 search (FIF2SEACRCH) flip-flop 750-11400 of the D-type. The flip-flop 750-11400 is then activated in response to the occurrence of a T clock signal CLKT020 set to the binary state 1 if a two-input AND / OR gate 750-11402 and an AND gate 750-11400 a signal SETIF2SEARCH-100 as a binary signal 1 submit. This occurs when either an IF1 command is a so-called hit or when a 1F2 instruction is received from processor 700 during a 1F1 arbitration cycle.

If an IF1 command occurs, it is assumed that there is no hold state (which means that the Signal HOLDDMEMOOO from block 750-117 occurs as binary signal 1) and that by an address list lookup a hit signal has been generated (i.e. the signal H1T0TB100 occurs as a binary signal 1) indicating that the requested block of instructions is contained in cache memory 750-300. With respect to an IF2 instruction, it is assumed that there is an address list allocation cycle, de an address list scan follows, in the course of which there was an evasion or misconduct, namely on the IF1 command towards (this means that the signal FIF1ASSEGN100 occurs as a binary signal 1).

Q30O24 / 0883

In each of the situations mentioned, the logic gate 750-11402 outputs the signal SETIF2TIME100 as Binary signal 1. When the instruction call command was caused by a transfer or branch instruction that is not a NOGO command is acting (which means that the signal NOGOO30 occurs as a binary signal 1), so this shows indicates that the IF2 instruction that is currently applied to the instruction lines should be processed (i.e. that an indication by the / binary signal 1 occurring signal DREQCAC112 is present). There is also the AND element 750-11404 the signal SETIF2SEARCH100 as binary signal 1 away. This switches the flip-flop 750-11400 to the binary state 1 if the CANCEL012 signal as Binary signal 1 occurs.

As can be seen from FIG. 7a, the binary signal 0 occurring at the output of the flip-flop 750-11400 becomes the input signal applied to the hold circuits of block 750-117. The FIF2SEARCH000 signal is triggered by a Buffer circuit 750-11406 delayed and one input of a NAND gate 750-11408 of an instruction call two allocation (IFIF2ASSIGN) flip-flop 750-11410 supplied.

The signal FIF2SEARCH010, together with the signal EISIF2000 (which indicates a non-EIS command) that the NAND gate 750-11408 is the FIF2ASSIGN flip-flop 750-11410 in the binary state 1 on the occurrence of a logic or button signal SETBVALID100 and a T clock signal CLKT020 toggles. The state of this Flip-flops and the other elements are output as an output signal when the signal FLDTBVALID110 is on Binary signal is 1.

It should be noted that the FLTBVALID110

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via an AND gate 750-11412, via a clock-controlled one Flip-flop 750-11414 and through a delay buffer circuit 750-11416 is output as binary signal 1 in the event of an evasive or missed condition (which means that the signal HITT0TB010 is a binary signal 1). This state is dependent on an address list search generated with respect to a read command (e.g. IF2). It is assumed that no Hold is present (which means that the signal HOLDDMEMOOO is a binary signal 1). It is also assumed that in the case of a 1F2 command, the relevant status was not available due to a NOGO transfer (which means that the signal N0G0020 is a binary signal 1), and that there is no delete condition (which means that the signal CANCELC010 is a binary signal 1), and for a read operation that is decoded by the circuits of block 750-113 in response to the read command which is applied to the command lines (which means that the DREQREAD100 signal is a binary signal 1 where DREQREAD100 = READ100.DREQCAC112 applies).

Under similar conditions, an instruction fetch 1 grant (FIF1ASSIGN) flip flop 750-11418 via an AND gate 750-11420 on the input side for the occurrence of an IF1 command is set to binary state 1 (i.e. when the IF1100 signal is a binary signal 1 is), where an evasion or a suspension was determined (which means that the signal SETTBVAID100 as Binary signal 1 occurs). The load transit buffer valid flip-flop 750-11414 remains set until the SETLDTBVALID100 signal appears as a binary 0 signal. It should be noted that the binary 0 output signal FLDTBVALIDOOO is given to circuits which are provided as part of block 750-102.

The other pair of flip-flops 750-11422 and 750-11424 become in the event of an evasive or dropout condition

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set in response to the occurrence of the SETLDTBVALID100 signal. The load quad flip-flop 750-11524 is then set to binary 1 when the on the DMEM command lines command issued is decoded as LDQUAD command (which means that the signal LDQUAD100 from the decoder 750-113 is a binary signal 1) and that the ZAC command sent to the ZADOB lines is coded such that it requires a read quad operation (meaning that the signal ZAD0B04100 specified commands IF1, IF2, LDQUAD, PRERD and RDSNGLE occur as binary signals 1 set).

The RDQUAD flip-flop 750-11422 is via an AND gate 750-11426 then set to binary 1 if a signal CQIN1100 from those in the command queue block 750-107 contained circuits produce a binary 1 signal, creating a double precision command (which means that the signal ZAD0B02100 is a binary signal 1).

Referring to Fig. 7a, it can be seen that block 750-114 also a comparator circuit 750-11435 comprises. This circuit can be implemented in a conventional manner to be viewed as; it can, for example, take the form of circuits as described in US Pat. No. 3,955 are specified.

The comparator circuit 750-11435 is controlled by signals USETBRDY100 and DATA100 released. The USETBPDY100 signal indicates that the cache memory is on commands waiting to be loaded from memory into buffers IBUF1 or IBUF2. The DATA100 signal is from a NAND gate 750-11436 output as a binary signal 1, which is characteristic of the inclusion of information from memory. The comparator circuit comprises two areas. One area compares the command queue entry pointers signals and the output pointer signals from

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the blocks 750-108 or 750-109. This area gives the signals CQCMP100 and CQBMPOOO as binary signals or as a binary signal 0 when the pointer signals are the same. The range corresponds to block 750-110 in Fig. 4.

The other area compares the input signals at the connections A1, A2 and B1, B2 - being the control signals ZRIB100, ZIB010 are fed to the input connections A1, A2 - with the states of the! I-fetch-2-flag signals ZIF1FLGOOO, ZIF2FLGO00, which are applied to the connections B1, B2. If there is an equality, it indicates that the information is out added to memory at this point in response to either an I-fetch 1 or an I-fetch-2 command is or has been. It should be noted that the control signal ZRIB100 controls the ZRIB switch 750-720 controls.

The signals ZEXT0100, ZEXT1100 with the signals MIFS1100 and DATA0DD100, which are applied to the connections B4, B8. This will indicate whether the within the information addressed in the command buffer is the same as the information received. In particular the signals ZEXT0100 and ZEXT1100 through the circuits of block 750-920 of which the two The address of the instruction stored in the RIRA register, comprising least significant bits, is generated. This specifies the word memory location that is addressed within the I-buffer. The signal MIFS1100 is coded to determine whether the first half or the second half of the block is for the recording is used. The DATA0DD100 signal defines whether the first word or the second word of the first 2-word pairs is included. The DATAODD100 signal

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is generated by the AND gate 750-11437.

Finally, the comparator circuit 750-11435 compares a signal ENABTBRDY100 which the terminal A16 of is fed to block 750-102, with the voltage VCC, which is indicative of a binary 1 and the is fed to the terminal B16. If there is a actual correspondence between the two series of all six signals is given by the circuit 750-11435 outputs a binary signal 1. As a result, the IBUFCMPROOO signal appears as a binary 0 signal at the complementary output connection. This causes block 750-722 to output the IBUFRDY100 signal as a binary 1 signal.

In addition, the area 750-114 includes an AND gate 750-11417. During the first half of a cache cycle (i.e. when the FHT120 signal from the delay circuit 750-11810 appears as Binary signal 1) becomes the AND element when the FLDTBVALID flip-flop 750-11414 is in the binary state 1 750-11417 the control signal RTB5-8100 as binary signal 1 hand over. This signal is used as a clock sample input to the level storage area of the transit block buffer 750-102 supplied. This area consists of a simultaneously operated 4 X 4 double read / write 16-bit memory constructed in four words with a length of four bits similar to the memory device of block 750-10238 is organized and similar to the storage facilities that are used to build the 36-bit read command buffer area of block 750-102 and write command / data buffer 750-100 used are.

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In Fig. 7a it is illustrated that the data acquisition and control block 750-115 contains a plurality of NAND gates 750-11500 to 750-11510 and a plurality of AND gates 750-11511 to 750-11514, which are arranged in the manner shown are connected to each other to generate the control scan enable signals LQBUF100, IBUF1100 and IBUF2100 and the reset buffer signal RESETBUF100 and the write control buffer signal WRTBUF0100. These signals are used to control the operation of the buffer circuits of section 750-7. As can be seen from Fig. 7a, the other write control buffer signal WRTBUF1100 is generated by a buffer delay circuit 750-11515 in response to the occurrence of the signal FARDA010. The WRTBUF0100 signal is derived from the output of the dual input data selector / multiplexer circuit 750-128 which selects either the RMIFS1100 signal from register 750-127 or the RMIFSB1100 signal from register 750-129. The selection is made in accordance with the state of the FARADAOOO signal that is on

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the acceptance line ARDA of the data interface circuit 600 is generated. The multiplexer circuit 750-128 generates, in accordance with the state of the signal FSARDAOOO, the two series of signals MIFS2100, MIFS3100 and DMIFS2100, DMIFS3100, which are sent to the read address inputs of the buffer 750-102,

It should be noted that the area or section 750-115 also has a D-type flip-flop 750-11517 for contains double precision (FDPFSX), which in response to the occurrence of a clock signal CLKT020 via a first AND element on the input side is set to binary state 1 is, in accordance with the state of the signal PTXDPFS100, which the relevant AND gate fed from the DPFS line through the system interface unit 100 via an amplifier circuit 750-11518 will. When set, the DPFS line indicates that two data words from the system interface unit 100 have been sent out. The switchover takes place when the system interface unit 100 the Signal PTXARDA100, which you receive via an amplifier circuit 750-11519 from the ARDA line of the interface unit 6OO has been fed her, as a binary signal 1 emits. The ARDA line indicates that the the cache memory 750 on the DFS lines from the system interface unit 100 are present ,, The output signal of a FARDA flip-flop (not shown), which delays the signal ARDA by one clock period, is added to a second stop AND element fed together with the signal FDPFSX100. The FDPFSX flip-flop 750-11517 remains for two clock periods set. This means that the flip-flop 750-11517 in accordance with the number of Responses or response signals (DPFS signals) of the system interface unit is set. In the event of of a single read command generates the system interface

Q3Ö02W0883

Digit unit enables two response signals, each of which brings in a pair of words, in any case this is the writing of the two words in the cache memory if the signal RWRCACFLG1OO is a binary signal 1 occurs.

The binary 0 output of flip-flop 750-11517 is inverted by a NAND / AND gate 750-11521 and delayed by a buffer delay circuit 750-11522 before it is delivered to the AND gate 750-11512 will. The same binary O output signal becomes without inversion delayed by means of a buffer delay circuit 750-11523 and delivered to circuits which the states of the bit positions of a transit buffer valid bit register reset, which is part of the transit buffer 750-102.

It should also be noted that the double precision signal FDPF110 in a AND gate 750-11524 with a write cache flag signal RWRTCACFLG100 from the transit block buffer tag storage part of the buffer 750-102 is linked. The AND gate 750-1152 generates a memory write request signal MEMERTREQ100, which to the area or section 750-9 to store the writing of memory data into the cache to enable (i.e. to control the address switch selection).

As shown in Figure 7a, the release request control circuit block includes 750-116 an active output port request flip-flop 750-11600. This flip-flop is a clock-controlled flip-flop of the D-type, which has two input-side AND / OR logic circuits contains. The flip-flop 750-11600 is activated in response to the occurrence of the clock signal CLKT020

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then set to binary 1 when block 750-114 has two signals ENABSETA0PR100 and SETA0PR100 emits 1 as binary signals. If this flip-flop is set to the binary state 1, this leads again to that the AOPR line of the interface device 600 is set, whereby the system interface unit 100 a data transfer request is signaled. The binary signal 0 of the flip-flop 750-11600 is inverted by means of an inverter circuit 750-11602, by means of a delay buffer circuit 750-11604 delayed and fed to a hold AND gate. The flip-flop 750-11600 remains set until the signal FARA020 is converted into a binary signal 0 toggles. This indicates that the system interface unit 100 has met the cache memory request has accepted.

The hold control block 750-117 comprises, as shown, a lock transit buffer hit FINHTBHIT flip-flop 750-11700, an AND gate 750-11702 and a variety from AND / NAND gates 750-11704 to 750-11716. That Flip-flop 750-11700 has a first input-side AND element and a NAND element 750-11704 the occurrence of a T clock signal CLKT020 then in the binary state 1 is set if the signals INHTBHIT100 and TBHIT100 occur as binary signals 1. The NAND element 750-11701 outputs the INHTBHIT100 signal as binary signal 1 in the event of a delete condition (which means that the signal CANCELC012 is a binary signal 0 occurs).

From the complementary output side of the flip-flop 750-11700, the signal FINHTBHITOOO is taken as an input signal delivered to the AND gate 750-11702. An address list busy signal DIRBUSYOOO from block 750-526 becomes the other input of AND gate 750-11702

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fed. If the address list is not performing a search (i.e. the signal DIRßUSYOOO is a binary signal 1) and if the signal iNHTßHIl'100 is a binary signal 1, then the AND gate 750-11702 outputs the signal 1NHTBACMP000 as a binary signal 1. This causes, that the logic element 750-11704 emits the signal TBHIT100 as a binary signal 1 when the AND element 750-136 emits a transit block address comparison signal TBACMP100 as binary signal 1. At the same time there is Linking element 750-11704 sends the signal TBHITOOO as a binary signal 0.

The AND / NAND gates produce 750-11708 through 750-117110 the signals CPSTOPOOO to CPST0P003, which the processor to indicate the presence of a hold state. The other AND / NAND gates 750-11714 to 750-11716 generate the signals HOLDDMEMOOO to H0LDDMEM003, to indicate an internal hold state through which the other areas or sections of the cache memory prevented from executing the instruction issued by processor 700 on the instruction lines. If a hold command condition (i.e. the HOLDCMDOOO signal occurs as a binary 0), an evasive or Failure state (which means that the FRDMISS020 signal appears as a binary 0), a hold quad state from block 750-916 (which means that the signal HOLDLDQUADOOO occurs as binary signal 0) or a transit block hit condition is present (which means that the signal TBHITOOO as binary signal 0 occurs), then the logic elements 750-11708 to 750-11710 give their output signals CPST0P003 to CPSTOPOOO as binary signal 0 and the signals CPST0P103 to CPST0P100 as binary signals 1. This gets the processor causes the operation to stop.

Under appropriate conditions, in addition to

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a hold seek state (i.e., when the signal HOLDSEARCHOOO is a binary signal 0), as indicated by the AND gate 750-11712, the signal EARLYHOLDOOO asserted as binary 0, or in a hold cache state (i.e. that the Signal HOLDCCUOOO occurs as binary signal 0) the logic elements 750-11714 to 750-11716 give their Output signals HOLDDMEMOOO to H0LDDMEM003 as binary signals 0, while the signals H0LDDMEM100 to H0LDDMEM103 occur as binary signals 1.

From the drawings it can be seen that the timing circuits of block 750-118 are synchronously operated D-type flip-flops 750-11800 with two AND / OR input circuits. The flip-flop 750-11800 takes the 1/2-T clock signal CLKHT100 via the logic element 750-11802 and the inverter circuit 750-11804. A limit T clock signal DEFTCLK110 becomes one of the Data inputs are supplied through two delay buffer circuits 750-11806 and 750-11808. Every buffer circuit brings about a minimum delay of 5 ns.

The two signals CLKHT100 and DEFTCLK110 are generated by the common clock or timing control signal source. In response to the occurrence of these signals, the HaIt-T flip-flop 750-11800 switches to the binary state 1, namely on the trailing edge of the DEFTCLKHO signal. The relevant flip-flop switches to binary state 1 on the occurrence of the next CLKHTIOO signal (on the trailing edge ),

The signals FHT100 and FHTOOO are in addition to the Signals FHT120, FHT010 and FHT020 coming from the output terminals 1 and 0 of the flip-flop 750-11800 are derived to the remaining circuits of the range 750-1 as well as to the other areas (these are the areas 750-5, 750-9 and 750-114; distributed. The

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Signals FHT120, FHT020 and FHTO10 are transmitted via a another pair of delay buffer circuits 750-11810 and 750-11812 and a driver circuit 750-11814 distributed.

The T clock signals, such as clock signals CLKT020 and CLK.T022 taken from the common timing signal source are distributed in their "original" form to the various flip-flops of the registers. If there is a requirement to generate a 1/2 T clock signal, then the 1/2 T clock signal becomes CLKHT020 with the 1/2 T limit signal (FHT100) routed to the input of the flip-flop or register. The state of the FHT100 signal is used to define the first and second halves of a T cycle. If the signal FHT100 is a binary signal 1, then this sets a time interval corresponding to the first hold of a T clock cycle. If on the other hand the FHT100 signal is a binary 0, then this sets a time interval corresponding to the second hold of a T clock cycle.

In the context of the present invention, the data recovery circuits are considered to have been carried out in a conventional manner; they can for example take the form of the circuits described in the references cited. These circuits generate a data recovery signal for delivery to processor 700 by combining the 1/2-T clock signal FHTOOO with a signal which It is characterized by the fact that data are keyed into the processor register. This becomes the data recovery signal generated only during the second half of a T clock cycle when such data is in the Processor registers are keyed.

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In the case of the sections or areas 750-5 and 750-9, the signal FHT100 is used to switch over the other timing and control flip-flops to control how this is explained.

The area 750-3 will now be explained in more detail. In Fig. 7b, special blocks are the blocks of the area 750-3 illustrated in more detail. Corresponding reference symbols have been used as far as possible.

From Fig. 7b it can be seen that the decoder circuits of the Blocks 750-303 contain a decoder circuit 750-30300 which is responsible for operation by the signal ENBMEMLEV100 is enabled by the circuits of block 750-920. The signals from the non-inverting output terminals of the decoder circuit 750-30300 are connected to the input terminals of a first multiplexer circuit 750-30302 delivered. The signals appearing at the inverting output connections are sent to the Input terminals of a second multiplexer circuit 750-30304 output. The multiplexer circuit 750-30302 is always enabled for operation, while the multiplexer circuit 750-30304 is only enabled when when the ENBADR1100 signal passes through the circuits of the Block 750-920 is output as binary signal 1. It is assumed that the "0" positions of both multiplexer circuits always be selected.

Certain combinations of the two series of control signals ZADR01100 to ZADR71100 and the signals ZADR00100 to ZADR70100 are connected to the control input connections each of the eight crossbar address selection switches 750-302a through 750-302h are asserted. It is It can be seen that each crossbar switch has a number of sections, each of which includes three parts, indicated by solid lines

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are indicated between the relevant areas. For the sake of simplicity, the number of areas per switch is shown together . For the sake of simplicity, the control area of each section or area is also shown only once, since it is the same for all sections or areas that are required to form the switch.

As is apparent from the present drawing, depending on the states of the pairs, the control signals ZADROO1OO, ZADRO11OO to ZADR7O1OO, ZADR711OO the signals from one of the three sources are delivered to each row of terminals W, X, Y and Z at the same time.

The area 750-5 will now be explained in more detail. In Fig.7c specific blocks of the blocks of area 750-5 are shown in detail. As far as possible, appropriate Reference numerals used.

From Fig. 7c it can be seen that the address list hit / error control circuits of the block 750-512 contain a coding network, which consists of a plurality of NAND gates 750-51200 to 750-51220 and from a There is a variety of amplifier circuits 750-51224 through 750-21228. The NAND logic circuits are switched in such a way that the series of signals ZFE1100 through ZFE7100 from block 750-506 and the series of signals ZHT1100 through ZHT7100 from blocks 750-640 through 750-552 can be encoded into the 3-bit code used to control the operation of switch 750-306.

The GSRCH100 signal is generated by the circuitry of block 750-526. As explained, this signal is only emitted as a binary signal 1 during the second half of a T clock cycle. So that an output signal from one of the NAND gates 750-51200 to 750-51208 is generated only during this interval.

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In particular, the hit signal determined by the state of the full / empty bit causes one of the signals ZCDLEV1000 to ZCDLEV7OOO as binary signal 0 is delivered. This in turn puts the NAND gates 750-51216 to 750-51220 in the state that to generate the 3-bit code in question.

The signal ZCDICENAB100, which is also generated by the Circuits of block 750-526 is generated as a binary signal 1 only during the first half of a T clock cycle occur. This means that the output signals from the NAND gates 750-51210 to 750-51214 are only generated during this interval. This means that the instruction address level signals ZNICLEV0100 through ZNICLEV2100 from block 750-910 generate the signals ICLOOOO to ICL2000, which in turn generate the signals ZCD0100 to Z0D2100. Be on it pointed out that the signals ZCD0100 to ZCD2100 den Correspond to signals ZNICLEV0100 to ZNICLEV2100.

The signals RDDBLLOOOO to RDDBLL2000 are used for the second operating cycle for a read double command define. If any of the signals RDDBLLOOOO to RDDBLL2000 occurs as binary signal 0, a corresponding signal of the signals ZCDO100 to ZCD2100 will then appear as binary signal 1.

The signals ZCD0100 to ZCD2100 are sent to different Inputs of respective amplifier driver circuits 750-51224 to 750-51228 are output. These circuits send the control signals ZCD0100 to ZCD2100 to the control connections of the switch 750-3Ob.

Another block shown in detail in FIG. 7c is block 750-526. As already mentioned, the block 750-526 contains a number of address lists

030024/0883

Control flip-flops. The control state flip-flops contain, as shown, the Address List Allocation (FDlRSAN) control state flip-flop 750-52b00 and a plurality of timing flip-flops one Register 750-52610.

The flip-flop 75O - !? 2bOO is a clock-controlled D flip-flop, which in the binary state 1 via a first input-side AND element in the event of a command request (i.e. when the REQC0MB0100 signal is present as a binary signal 1) with regard to a read command (i.e. when the RDTYP100 signal is present as a binary signal 1) is when processor 700 is requesting data from memory rather than cache memory (i.e., the Signal BYPCAC110 is a binary signal 1). If there is no a hold state (i.e. when the signal HOUX) OO as a binary signal 1 to an AND gate 750-52602 is issued) as well as in the case of a further transmission (i.e. when a binary signal 1 occurs Signal N0G0021) and without an erasure state (i.e. that the CANCELC010 signal is a binary signal 1) and upon signaling of a request by the processor 700 (which means that the signal DREQCAC111 as Binary signal 1 occurs) the AND gate 750-52604 outputs the signal REQC0MB0100 as binary signal 1.

An AND gate 750-52606 outputs the signal SET0NBYP100 as Binary signal 1 in the case of a read from when the decode The circuit 750-528 outputs the signal RDTYP100 as a binary signal 1 and when the processor 700 receives the bypass cache memory signal BYPCAC110 as binary signal 1 gives away. The result of this is that the FDIRASN flip-flop 750-52600 toggles to binary 1, indicating an address list arbitration cycle of operation is.

030024/0883

The flip-flop 750-52600 will also have a second AND element on the input side is set to the binary state 1 in the event of a command request (i.e. that then the signal REQC0MB0100 appears as binary signal 1), and then, if an evasive or faulty state has been determined with regard to the block to be read is requested (which means that the signal SET0NMISS100 occurs as binary signal 1). The signal SET0NMISS100 becomes Output as binary signal 1 from AND gate 750-52608 when signal RDTYP100 occurs as binary signal 1 and when the RAWHITOOO signal from block 750-512 occurs as a binary 1 signal. The flip-flop 750-52600 will upon the occurrence of a clock signal CL0CK112 in the Binary state 0 reset; the relevant clock signal is from the common signal source in the absence of a Set output signal generated by the two AND gates on the input side.

A first flip-flop (FICENAB) of register 750-52610 becomes used to determine the time span within a T clock cycle, within the instructions or commands or operands are to be fetched from the cache memory 750.

This flip-flop is in the binary state 1 via a first AND element on the occurrence of a clock signal CL0CK120 switched when that by the timing control circuits of block 750-112 generated signal FHT100 as a binary signal 1 occurs. The clock signal CL0CKD120 from the common The time control signal source is provided via an AND element 750-52612 and an inverter circuit 750-52612 and an inverter circuit 750-52514. The FICENAB flip-flop is reset in response to the following clock signal when the FHT-100 signal occurs as a binary 0 signal.

Q3 002W0883

The second flip-flop of the register 750-52610, which is a bistable trigger element, is used to set an interval during which operands (not instructions) from cache 750 in sequence a special condition caused by an IF1 instruction that does not denotes the last word in a command block. The FRCIC flip-flop has a first input AND gate is switched to binary state 1 in response to the occurrence of the clock signal CLACKD120, if the Signal FJAMZNICLEVOOO occurs as binary signal 1. That FRCIC flip-flop is reset on the occurrence of the following clock pulse when the signal FJAMZNICLEVOOO occurs as binary signal 0.

As shown, the signal appearing at the zero output terminal of the FICENAB flip-flop corresponds to the Linking half-T clock signal GATEHFTCHLK110, which is distributed to the circuits of block 750-920.

The signal FICENABOOO is combined with the signal FRCICOOO and the signal RDDBLZCDEOOO in an AND gate 750-52616 combined to generate the GSRCH100 signal. The RDDBLZCDEOOO signal comes from the decoder circuit. As a result, the GSRCH100 signal will appear as a binary signal 1 during the second half of a T clock cycle, when operands are fetched (which means that the signal FICENABOOO occurs as a binary signal q), with an exception in the case of a read double command (i.e. when the signal RDDBLZCDEOOO occurs as binary signal 1).

The binary output signal appearing at the zero output of the FICENAB flip-flop is converted into a NAND element 750-52618 linked. This NAND link is there

the signal ZCDINCENAB100 as binary signal 1 during of the first half T interval when commands are fetched (i.e. when the FICENABOOO occurs as binary signal 0) or in the case of the IF1 command described above (i.e. when the signal FRCICOOO is a binary signal 0).

The circuits of block 750-526 also include a NAND gate 750-52620 and a plurality of AND gates 750-52622 through 750-52628 connected as shown. The relevant circuits generate a first enable control signal DIRADDE100 for controlling the operation of the decoder circuit 750-521. In addition, the relevant circuits generate a second release control signal FEDC0DE100 for Control of the operation of a decoder circuit 750-52000 of block 750-520.

During an address list allocation cycle (i.e., when the FDIRASN100 signal is a binary 1) in the absence of a state relating to a transfer and no transfer (i.e. when the signal N0G021 occurs as binary signal 1) the AND gate 750-52626 output the signal D1RN0G0100 as binary signal 1. if a signal FSKIPRROOO is issued by the circuits of block 750-916 as binary signal 1, then caused this the AND gate 750-52628, the signal DIRADDE100 output as a binary signal 1, whereby the decoder circuit 750-521 is approved for operation. If the signal DIRN0G0100 or the signal FSKiPRROOO as a binary signal 0 occurs, then this causes the AND gate 750-52628, the decoder circuit 750-521 to ineffective make the signal DIRADDE100 as a binary signal 0 occurs.

Q3002A / 0883

Under the same conditions, the AND gate gives 750-52624 the signal FEDC0DE100 as binary signal 1, whereby the Decoder circuit 750-52000 is released for operation. The AND gate 750-52030 causes an amplifier circuit 750-52532 to output the FORCEBYPOOO signal as binary signal 1 if both signals FSKIPRROOO and FBYPCACOO occur as binary signals 1. The FORCEBYPOOO signal is sent to the transit block identifier area of the block 750-102 delivered. The signal FBYPCACOOO is generated in a conventional manner, according to which the signal on the BYPCAC line by the processor 700. The signal is in a flip-flop (not shown) stored whose output signal occurring at the zero output corresponds to the signal FBYPCACOOO.

The circuits of the illustrated block 750-520 comprise the decoder circuit 750-52000 and two multiplexer circuits 750-52002 and 750-52004. It is assumed that these are normally connected to the "O" input terminals of the multiplexer circuits 750-52002 and 750-52004 are selected to be used as Output signals (this means that the signal sent to the G input is a binary signal 0 is). Accordingly, when the decoder circuit 750-520000 is enabled, the output signals FED0100 to FED7100 for generating the signals RWFE0100 to RWFE7100 upon the occurrence of the clock signal CLOCKOOO lead there.

In Fig. 7c, the register 750-507 is also illustrated in further details, which is a clock-controlled four-stage register 750-50400 and a variety of amplifier circuits 750-50402 bis 750-50602 contains. Register 750-50400 contains D flip-flops, the first three of which are flip-flops are connected to each other so that they are circulating signals 0LDRR0100

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save to 0LDRR2100. The fourth flip-flop is like this switched to indicate the presence of another hit condition caused by the circuits of block 750-562 (not shown) has been determined. This means that this flip-flop is in the 1 state is set when the ALTHIT100 signal occurs as a binary signal 1.

It should be noted that the flip-flops of the register 750-50400 only respond to the occurrence of a Clock signal CL0CK112 are enabled when the signal FDIRASNOOO occurs as a binary signal 1, which is indicative of the fact that there is no address list allocation cycle is executed (a hit state).

If a hit status is determined within the considered half of a block, the signal is ALTHITOOO output as binary signal 0. This causes the first three flip-flops of the register 750-50400 to have a first row of input-side AND gates with the circulation signals RR0100 to RR2100 from the block 750-500 loaded here. When a hit condition is detected within the other half (alternative half) of the block referred to, the circuits of block 750-512 assert the ALTHIT100 signal as binary signal 1. This causes the three flip-flops to have a second row of input AND gates with the other level signals ALTHITLEV0100 through ALTHITLEV2100 are loaded by the circuits of block 750-512 can be generated.

The binary 1 signals of the register 750-50400 are as inputs to amplifier driver circuits 750-50402 through 750-50406 for storage in the transit block buffer 750-102 supplied. The same signals are applied to the A operand input terminals of an adder circuit

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of the block 750-508 supplied. The adder circuit adds or increments the signals 0LDRR0100 to 0LDRR2100 to or by one by sending a binary 1 to the C1 terminal of the adder circuit.

The sum signals generated at the F output connections NXTRR0100 to NXTRR2100 are in the circulation area of the Registered tax address list 750-500.

Finally, signals 0LDRR0100 through 0LDRR2100 are used as inputs to another set of amplifier driver circuits 750-50408 through 750-50412 to be stored in one of the instruction address registers 750-900 and 750-902 shown in FIG. 7e will.

The area 750-7 will now be explained in more detail. This area is illustrated in detail in FIG. 7d. As can be seen from FIG. 7d, block 750-722 contains a plurality of NAND gates connected in series 750-72230 to 750-72234. The NAND gates 750-72230 and 750-72231 are connected in such a way that they command buffer validity and command control signals IBUF1V100, ZRIB010 and IBUF2V100, ZRIB100 from the I-buffers 750-715 and Record 750-717 and from block 750-920. The signals IBUF1V100 and IBUF2V100 indicate the command buffer into which information is loaded. this means that when the signal 1BUF1V100 occurs as a binary signal 1, it is determined that the I-buffer 750-715 is loaded. When the IBUF2V100 signal occurs as a binary 1, this specifies that the I-buffer 750-717 is loaded with a command word.

The control signals ZRIB010 and ZRIB100 define which command buffer validity bit is to be checked, what the addressed command buffer. This means that if the signal ZRIB010 is a binary signal 1,

Q30024 / 0883

the IBUF1 validity bit through the circuits of the Blocks 750-920 is specified. If the ZRIB100 signal is a binary signal 1, then the IBUF2 valid bit specified. If the signal IBUF1RDY000 or the signal 1BUF2RDY000 occurs as a binary signal 0, then the NAND gate 750-72232 outputs the signal TBIBUFRDY100 as a binary signal 1, which is characteristic of one Standby.

The circuits of block 750-920 give an enable signal USETBRDY100 as a binary signal 1 to the switchover of the I-buffer valid bit in question. This causes the NAND gate 750-72233 to output the signal TBRDYOOO as a binary 0 signal. This leads to the NAND gate 750-72234 emits the signal 1BUFRDY100 as a binary signal 1, which signals the ready state is.

It should also be noted that the NAND gate 750-72234 also outputs the IBUFRDY100 signal as binary signal 1 then emits when a command call ready signal IFETCHRDYOOO as a binary signal 0 from the circuits of the Blockes 750-920 is delivered. The signal IFETCHRDYOOO is a binary signal 0, apart from the fact that the instructions are taken out of a block in the cache memory. Finally, the NAND gate gives 750-72234 the signal 1BUFRDY100 is then off as binary signal 1 when a Command buffer comparison signal IBUFCMPROOO output as binary signal 1 from the comparator circuit 750-11435

The IBUF1 and IBUF2 areas 750-715 and 750-717 each contain, as can be seen from FIG. 7d, a plurality of simultaneously operated 4 × 4 double read / write memories. Each memory is a 1b-bit memory organized into four words of four bits each. Words can be made independently of one another

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- «^ 09 '-

any two locations at the same time read out how information is written into any memory location.

The signals WRTBUF0100 and WRTBUF1100 are sent to the Write address connections of the memory applied, while the signals ZEXT0100 and ZEXT1100 to other connections of the rows of read address terminals are applied along with the signal VCC. The read address inputs VCC signals are output through the G1 terminal Approved. The signals ZEXT0100 and ZEXT100O enable reading out the content from any memory location of the 4-bit memory locations to the 1AY output terminals.

The memories 750-71500 to 750-71503 of the block 750-715 are used with the signals RDFS (XO) 110 to RDFSP (X) OIO and the signal VCC upon the occurrence of the T clock signal CLKHT021 when the IBUF1 strobe signal IBUF1120 from block 750-715 occurs as binary signal 1. In addition, the contents of all memory locations of each memory are brought to zero or deleted, when the circuits of block 750-115 receive the IBUF1 reset signal Output RESIBUF1000 as binary signal 1. This means, that - as can be seen from Fig. 7d - the pairs of NAND gates 750-71504 connected in series and 750-71505 as well as 750-71704 and 750-71705 the reset signals RESIBUF1000 and RES1BUF2000 as binary signals 1 submit. In addition, a trigger signal INITOOO causes a binary signal 0 from the processor 700 the output of the signals RES1BUF1000 and RESIBUF2000 as binary signals 1.

In a corresponding manner, the memories 750-71500 to 750-71503 of the block 750-717 are provided with signals RDFS (XOj110 to KDFSP (X) OIO and the signal VCC

Ö30024 / 0883

the occurrence of the T clock signal CLKHT021 loaded when the 1BUF2 sample signal occurs as a binary signal 1. Since three additional groups of memories, such as memories 750-71500 through 750-71503, are included in each buffer to provide for the storage of four 36-bit instruction words, the (X ) designation is used for the input and output signals are used to provide an indication that such signals are identical or correspond to one another, with the exception of different values for (X). For example, XO has the values 00, 17, 18 and 35, while X8 has the values 08, 09, 26 and 27. Each byte memory location contains a valid bit memory location that is switched to the binary_status when information is loaded into the relevant memory location. The output signals from the respective valid bit byte storage location are, however, combined so that the arrangement can be viewed in such a way that each word storage location has a valid bit storage location.

The memories can be viewed as being implemented in a conventional manner and, for example, by memory circuits be formed as indicated in US Pat. No. AO 70.

08002W0883

The area 750-9 will now be explained in more detail. The individual blocks of the area 750-9 are shown in detail in FIG. 7e. Do this as far as possible corresponding reference numerals have been used.

From Fig. 7e it can be seen that the block 750-920 contains a first group of circuits of the block 750-92000 which the four rows of write control signals WRT00100 to WRT70100, WRT01100 to WRT71100, WRT02110 to WRT72100 and generate WRT0300 to WRT73100. As can also be seen from FIG. 7e, these circuits contain two multiplexer circuits 750-92002 and 750-92004, a register 750-92006 and four OktHl decoder circuits 750-92008 through 750-92014. These circuit devices are connected to one another in the manner shown.

Multiplexer circuit 750-92002 receives signals RHITLEV0100 through RKETLEV2100 from block 750-512 which are applied to the series of ^H O ^M input terminals while signals RTBLEV0100

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through RTBLEV2100 of the row of "1" input terminals are fed. During the first half of a T-cycle, if the signal FDFN2HT100 as Binary signal O is fed to the control connection G0 / G1, the signals RHITLEV0100 and RHITLEV2100 to the output connections fed. The relevant signals are clock-controlled in the upper three flip-flops of the register 750-92006 for the occurrence of the T clock signal CLKHT02 introduced. This allows the processor to cache operands into the 750-300 cache during the second half of the T clock cycle. During the second half of a T-cycle, when the signal FDFN2HT100 occurs as binary signal 1, the signals RTBLEV0100 to RTBLEV2100 are clock-controlled in the register 750-92006 introduced the appearance of the T clock signal CLKHT02. this enables memory data to be written into cache memory 750-300 during the first half of the next cycle.

The second multiplexer circuit 750-92004 receives signals Z0NE0100 to Z0NE3100 from the switch 750-144, which are delivered to the series of "O" input terminals while the MEMWRTREQ100 signal is from the Block 750-112 is asserted to the series of "1" input ports. When the signal FDFN2HT100 as a binary signal 0 occurs, the signals Z0NE0100 to Z0NE3100 are output to the output connections. the The relevant signals are clock-controlled in the lower three flip-flops of the register 750-9206 upon occurrence of the T-clock signal CLKHU.O2 introduced. During the In the first half of a T clock cycle, the NAND element 750-92005 outputs the ENBWRT100 signal as a binary signal 1, which makes it possible to output the previously loaded signals to the output terminals. This enables that Use processor zone bits to determine which operand bytes are to be updated when processor data

030024/0883

written to the specified level of cache memory will. If the FDFN2HT100 signal occurs as a binary signal 1, the MEMWRTREQ100 signal is clock-controlled introduced into register 750-92006. This causes all zone bits to appear as binary ones, whereby all bytes of the respective data word received from the memory in the designated level of the cache memory written during the first half of the next T clock cycle.

As can be seen from Fig. 7e, different Signals of the signals RWRTLEV0100 to RWRTLEV2100 to the enable input terminals of the octal decoder circuits 750-92008 to 750-92-14 issued. The signals RWRTLEV0100 through RWRTLEV2100 are applied to the input terminals Each of the octal decoder circuits 750-92008 to 750-92014.

Block 750-920 contains a second group of circuits from block 750-92020. These circuits generate the 1/2-T clock signal which is sent to the circuits of the Block 750-92000 is asserted, the enable memory level signal ENABMEMLEV100 and the enable address signal ENADR1100, which is connected to the circuits of block 750-303 is delivered. In addition, these circuits generate the series of control signals ZIC010, ZIC110 and RICA100, RICB100, which is connected to the circuits of the instruction address registers 750-900 and 750-902 in addition to the control signals RIRA100 and RICB100, which are fed to registers 750-308 and 750-310.

The circuits of block 750-92020 contain two half-level flip-flops of a register 750-92022, a group of three control flip-flops of the register 750-92024 and a clock-controlled flip-flop 750-92026. The circuits also contain a number of AND gates, NAND gates, AND / NAND gates and AND / OR

030024/0883

Links 750-92030 to 750-92041.

The connecting elements connected in series, namely the AND / NAND gate 750-92030, the AND / OR gate 750-92032 and the AND gates 750-92034 and 750-92035 generate on the occurrence of a signal FLDQUAD100 from device 750-916 to the occurrence of a signal FWFIDESC010 from processor 700 and on the occurrence of the signals FACTVRICOOO and FACTVRIC100 control signals from the register 750-92024 ZICOOO, ZIC010 and ZIC110. These signals are used to control the operation of the ZIC switch 750-906 and the various areas of registers 750-900 and 750-902 (e.g., the level valid bit storage and level bit storage) in addition to the associated registers.

The series-connected logic elements, namely the AND element 750-92036, the AND / NAND element 750-92037 and NAND gates 750-92038 to 750-92041 are operated in such a way that register scan signals RICA100 and RICB100 can be generated. These signals control the loading of registers 750-900 and 750-902. The AND element 750-92036 causes the output of the signal VALRDIBUF1Ü0 as a binary signal 1 if a hit condition in the case of a Read command has been detected (i.e. when the signal FRDMISSOOO occurs as a binary signal 1), if Furthermore, the transmission or the transfer was given by a transmission command (i.e. that the signal N0G0020 has occurred as binary signal 1) and if the signal CMPDATA / ICLEVOOO from the comparator circuit of block 750-912 is a binary signal 1.

The signal FRDMISSOOO is obtained from the zero output of the flip-flop (not shown), which - as mentioned - is set according to the following Boolean expression:

030024/0883

FRDMISS = (RDCMD.HOLDDMEM HITTOIC.CANCELC J.

The signals G00DFTCHA100 and G00DFTCHB1OO, which are sent by Circuits (not shown) are generated indicating whether the RICA register 750-900 or the RICB register 750-902 was in use at the time; the contents of the registers concerned are increased. So the signal G00DFTCHA100 becomes, for example, accordingly the following Boolean expression is generated: GOODFTCHA = INSTIFt · FLDQUAD · FACTVRIC · FDEN2HT + FDFN2HT »

FLDQUAD.FACTVRIC.

The GOODFTCHB signal is generated in a corresponding manner, except that the states the signals FACTVRIC and FACTVRIC are reversed.

It should be seen that when the EXECRDIBUF100 signal occurs as a binary 1, it is during this time the processor 700 the signal RDIBUF110 as binary signal 1 emits, the NAND gate 750-92039 causes the NAND gate 750-92041 to emit the signal RICA100 as a binary signal 1, if the signal G00DFTCHA100 occurs as binary signal 1. The signal ENBSTRBAOOO shows when! RICA register 750-900 is initially loaded. This means that if the signal ENBSTRBAOOO is a binary signal 0 occurs, the NAND gate 750-92041 the signal RICA100 as Output binary signal 1. The ENBSTRBA signal is specially generated according to the following Boolean expression:

ENBSTRBA = FLDQUAD FACTVRIC-FNEWIFl.FDFNlHT

+ FDFNlHT FACTVRIC FJAMZNICLEV FHOLDIFl + (INSTIFl + DCDLDQUAD) .FACTVRIC-FDFN2HT.lcANCLCMD ♦ FDFW2HT · [ZIC-INH2HT-ENAB2HT. Where sLlriENAB2HT = ENiBRICl + ENABRIC2

INH2HT «[CANCLCMD.FLASTINST.

Under any set of conditions the signals RICA100 and RICB100 scan their respective registers

080024/0883

free if they have been loaded first, or after an increment, as if Instructions are canceled or removed from the cache.

The NAND element 750-92042, the AND / NAND element 750-92043 and the NAND gates 750-92044 to 750-92049 are connected in such a way that register scan signals RIRA100 and RIRB100 can be generated in a similar manner as the register scan signals RICA100 and RICB100.

The NAND gate 750-92046 gives the signal RIRA100 as Binary signal 1 in the case of a new command request (i.e. when the NEWINSTOOO signal is a binary signal 0) or when processor 700 extracts an instruction from RIRA register 750-308 (i.e., then, if the signal TAKEINSTOOO is a binary signal 0). The NAND gate 750-92049 gives the signal RIRB100 im In the event of a new operand call (i.e. when the signal NEWDATAOOO is a binary signal 0) or then, when the processor 700 removes a data word from the RIRB register 750-310 (i.e. when the signal TAKEDATAOOO is a binary signal 0).

The AND gate 750-92050 and the AND / NAND gate 750-92051 generate the ENBMEMLEV100 signal during the second Half of a T clock cycle (which means that the signal FDFN2HT101 is a binary 1) when the circuits of block 750-112 receive the memory write request signal Output MEMWRTREQ100 as binary signal 1. The NAND gate 750-92052 generates the signal ENBADR1100 during the second half of a T clock cycle (which means that the signal FDFN1HT101 occurs as binary signal 0) or when the command counter is used becomes (which means that the signal USEICOOO is a binary signal 0).

030024/0883

With regard to the flip-flop register, it can be seen that the flip-flop of register 750-92026 is in the binary state 1 is then switched via a first AND gate when the AND gate 750-92053 is triggered, the signal INSTIF1100 to be output as binary signal 1, depending on the fact that an IF1 command has been passed through the decoder circuit 750-922 is decoded (which means that the signal DCDIF1100 is a binary signal 1). This Command or this process does not require any additional descriptors (which means that the signal FFPIMBIS020 from the processor 700 is a binary signal 1). In addition, the AND gate 750-92054 gives the signal CANCELCMDOOO as binary signal 1 for the presence of none Deletion state (which means that the CANCELC010 signal is a binary signal 1). Besides, there is no Hold, which means that the HOLDDMEM001 a binary signal is 0.

The flip-flop register 750-92026 is reset to the binary state via a second AND element provided on the input side, which the signals ENABNEWINSTOOO and NEWIF1FDBK100 from two NAND gates 750-92042 and 750-92043 and the AND gate 750-92055. The one occurring at the 1 output of the flip-flop register 750-92026 The output signal is fed to the NAND gate 750-92056. This NAND gate gives during the first Hold a T clock cycle (which means that the signal FDFN1HT100 occurs as binary signal 1) the signal USEICOOO occurs as binary signal 0 if the signal FNEWIF1100 occurs as binary signal 1.

The second flip-flop register 750-92022 contains the two timing flip-flops, both of which are in the binary state in response to the occurrence of the signal GATEHFTCLK100, which originates from the range 750-5, namely the appearance of the i / 2-T clock signal CLKHT021. the

090024/0883

Flip-flops of the register 750-92022 are in the zero state on the occurrence of the next 1/2 T clock signal CLKHT021 reset.

As already mentioned, the flip-flops of the register 750-92024 supply various status control signals. That first flip-flop (FRDIBUF) is switched to binary state 1 when the NAND gate 750-92060 the Signal SETRDIBUF100 as binary signal 1 on occurrence a read I buffer request signal from the processor 700 outputs (this means that the EXECRDIBUFOOO signal occurs as a binary signal 0) or if one is present Lock-ready state (which means that the FINHRDX010 signal occurs as a binary signal 0) when the AND gate 750-92061 outputs the signal ENABSETRDIBUF100 as binary signal 1. The ENABSETRDIBUF100 signal becomes issued as binary 1 in the case of an instruction that is not a load quad instruction (which means that the signal FLDQUADOOO is a binary signal 1) or in the case of an instruction call 1 command (which means that the signal G00D1F1000 is a binary signal 1). That The FRDIBUF flip-flop is activated one clock period later on the occurrence of the T clock signal CLKT021 via a second AND element on the input side reset.

The second flip-flop (FACTVRIC) of register 750-92024 is in accordance with the Boolean expressions given above via the NAND gates 750-92062 and 750-92064, set or reset via the AND gate 750-92063 and the AND / NAND gate 750-92065. The third flip-flop (FRDDATA) is switched to the binary state via a first AND element on the input side Occurrence of the signal SETRDIBUF100 set if the instruction is a load quad instruction (which means that the signal FLDQUAD100 is a binary signal 1). The FRDDATA flip-flop goes into binary 0 a

030024/0883

Clock period reset later, via a second AND element on the input side in response to the occurrence of the T-clock signal CLKT021.

The next group of circuits within block 750-920 comprises the circuits of the block 750-92070. As can be seen from Fig. 7e, these circuits comprise a first plurality of AND gates, AND / NAND gates and NAND gates 750-92071 bis 750-92086. These link elements are connected in the manner shown. They generate taxes signals SETACURLEV100, RICACNTL100 and RSTACURLEV2000, the setting and resetting of the existing level and level validity bit positions of the RICA register 750-900 in accordance with the states of the signals SETALEV1VAL100, RSTALEV1VALOOO and Control SETLEV2VAL100. These signals are generated by a further large number of AND gates and NAND gates 750-92087 through 750-92095.

A second plurality of AND gates, AND / NAND gates and NAND gates 750-92100 to 750-92116 generate signals SETBCURLEV100 in a corresponding manner, RSTBCURLEV200 and RICBCNTL100, through which the present Level and validity bits for the RICB register 750-902 are set and reset, respectively in accordance with the signals SETBLEV1VAL100, RSTBLEV1VALOOO and SETBLEV2VAL100. These signals are generated in a further large number of AND gates and NAND gates 750-92120 to 750-92125.

A variety of AND gates 750-92126 to 750-92129 generated on the occurrence of the signals SETALEV1VAL100, SETBLEV1VAL100, SETALEV2VAL100 and SETBLEV1VAL100 Control signals RICALEV1100 to RICBLEV2100 if the CANCELCMDOOO signal is a binary signal 1. These

030024/0883

- "200 -

UA 2949737

Signals are applied to the control input terminals of the level bit storage areas of the RICA and RICB registers 750-900 and 750-902 to control the loading of the hit level signals from the range 750-512 submitted.

Another variety of AND / NAND gates, AND / OR gates and NAND gates 750-92130 to 750-92137 are signals from the level validity bit storage and level storage areas of registers 750-900 and 750-902 the use transit buffer ready signal USETBDY100 and the control signals ZRIB010 and ZIB100, which are output to the circuits of block 750-114.

It can also be seen that block 750-92070 is a register 750-92140 comprising four D flip-flops, two AND gates 750-92141 and 750-92142, two AND / NAND gates 750-92143 and 750-92144 and two AND / OR gates 750-92145 and 750-92146 connected as shown. The flip flops of register 7 ^ 0-92140 with the content of the bit positions 8 and 9 of the RICA and RICB controllers 750-900 and 750-902 respond to the occurrence of the T clock signal CLKHT020 loaded under the control of the signals RICA100 and RICB100. This means that the top pair the register flip-flop is clock-controlled when the signal RCIA100 applied to terminal C1 is a binary signal 1 occurs, while the lower pair of register flip-flops are clocked when the Terminal G2 applied signal RICB100 as binary signal 1 occurs. The signals ZICOOO and ZHOO delivered to the connections G3 and G4 control independently of one another the generation of output signals from the top pair of the flip-flops or from the lower pair of flip-flops to the corresponding rows of output connections.

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294978?

The pairs of binary O output signals are determined by means of of AND gates 750-92141 and 750-92142 are linked to add address signals ZEXT0100 and ZEXT1100 to generate those signals that are required for generating the control signal NEXTLEVVA100, which is delivered to the control input terminals of the comparator circuit 750-912.

A final group of circuits comprises a flip-flop register 750-92150 and a large number of AND gates, an AND / NAND gate, NAND gates and AND / OR gates 750-92151 to 750-92156. These circuits are connected in such a way that the signal IFETCHRDYOOO is generated, which is given to the circuits of the range 750-114. The links 750-92153 and 750-92154 are connected so that timing control signals DFN2HT101 and DFN2HT100 are generated in response to the occurrence of a signal FHT010 from block 750-112. These Signals will appear as binary 1 signals during the second half of a T clock cycle of operation.

The flip-flop register 750-92150 is a first The AND element on the output side then changes to the binary state 1 set if the AND gates 750-92151 and 750-92152 the signals SETINHRDY100 and CANCELINHRDYOOO as binary signals 1 submit. The register in question is set to binary 0 via a second input-side AND element is reset when the NAND element 750-92155 outputs the signal RSINHRDYOOO as binary signal 0. The on The binary signal occurring at the zero output of the register 750-92150 is fed to the AND / OR gate 750-92156. if the signal FINHRDYOOO occurs as a binary signal 0, this causes the logic element 750-92156, the signal IFETCHRDYOOO to be output as binary signal 1.

In addition, FIG. 7e shows in detail the switch 750-910 and the comparator circuits of blocks 750-912

Ö30024 / 0883

and 750-914. The switch 750-910 is a crossbar switch that operates in the manner described above. The W output signals select one of the two sets of signals delivered to terminals AO and A1 in accordance with the state of the signal ZIC110. The X output signals choose one of the two series of signals applied to terminals A3 and A4, in correspondence with the state of the signal ZIC110. The output signals Y and Z select one of the four rows from signals applied to terminals A0-A4 in accordance with the states of the signals ZIC110, ZN1CLEV100 and ZIC110, ZCURLEV100.

The output signals ZNICLEV0100 to ZNICLEV2100 from the The Y output terminals of the circuit 750-910 become the B input terminals of the comparator circuit 750-912 for comparison with the signals RTBLEV0100 to RTBLEV2100 from the range 750-102. The comparator circuit 750-912 is enabled when decoder circuit 750-922 decodes an IF1 instruction (which means that the DEC0DEIF1010 signal occurs as binary signal 1) and when the NEXTLEWAL100 signal appears as Binary signal 1 occurs. The comparison leads to the generation of signals CMPDATA / ICLEV100 and ZMPDATA / ICLEVOOO.

The other comparator circuits of blocks 750-912 and 750-914 operate in a corresponding manner to generate signals CMPC0RLEV100 and CMPALTLEV100. Of the other area of the circuit 750-912 compares in detail the signals ZICLEV0100 to ZICLEV2100 with the Signals C7RR0100 to C7RR2100. If there is a match, the signal CMPCURLEV100 becomes a binary signal 1 submitted. This area is via a NAND element 750-91202 enabled when either the ZLEV1VAL000 signal or the ZLEV2VAL000 signal occurs as a binary 0 signal.

03002 ^ / 0883

The comparator circuit 750-914 has two sections that are defined by pairs of signals ZCURLEV100, ZLEV1VAL100 and ZCURLEVOOO, ZLEV2VAL100 be released. The first area compares the level 1 signals ZLEV10100 to ZLEV12100 with the circular signals C7RR0100 to C7RR2100. If a match is found, what appears on port A = B becomes Output signal occur as a binary signal 0, whereby the NAND gate 750-91402 is caused, the Signal CMPALTLEV100 to be output as binary signal 1.

In a corresponding way, the second area compares the level 2 signals ZLEV20100 to ZLEV22100 with the Circulating signals C7RR0100 to C7RR2100. If a match is determined, the output signal occurs as a binary signal 0, whereby the NAND gate 750-91402 causes the signal CMPALTLEV100 as a binary signal 1 to submit.

Ö30024 / 0883

Referring now to Figures 1 through 7e, the operation of the preferred embodiment will now be described Invention explained in more detail.

As noted, the cycle arrangement in the preferred embodiment divides a T clock cycle into a first half and into a second half. This means that if the signal KHT1OO as a binary signal 1 occurs, the first half of a T clock cycle is fixed. If the signal FHT1OO is a binary signal 0 occurs, the second half of a T clock cycle is fixed.

During the first half of the T clock cycle, commands are either called, fetched, or are Store data is written into the cache memory 750-300. In both cases, the level has already been determined to which access is made. In terms of commands, this means that the level is either in the RICA or stored in the RICB instruction address register at the time for which an IF1 instruction or an IF2 instruction has been executed by the processor 700 has been recorded. With regard to memory data, the level in one of the register locations of the Transit block buffer 750-102, due to the fact that the circuits of the block 750-520 have detected an error status, in the course of which the cache memory 750 was initiated, retrieve the requested data from memory. Takes place during the second half of a T clock cycle either an access to operand data from the cache memory, or processor data is in the cache memory in accordance with the results of an address list search.

030024/0883

To illustrate the operation of the preferred embodiment of the present invention, let for example, assume that processor 700 is executing a first branch or a transfer instruction, whereby switching from a first sequence of commands to a second sequence of commands takes place, where the first instruction in the relevant block / sequence is a further branch instruction. In in each case it is assumed that the toggled block or sequence of instructions is not is contained in the cache memory 750-300 and must therefore be fetched from the main memory 800. Furthermore is with respect to each transmit command, assume that it is a "GO" continue command.

Further information regarding the transfer commands can be found elsewhere (see the publication "Series 60 (Level 66) / 6000 MACRO Assembler Program (GMAP)" from Honeywell Information Systems, Inc., Copyright 1977, order number DDOBB, Rev. O).

As indicated herein, processor 700 performs various operations during cycles I, C, and E of FIG Processing of commands or instructions. This leads to the issuance of cache memory commands by the Processor 700 to cache storage unit 750.

When processor 700 receives the first transmission or the executes the first branch instruction, this results in the generation of an IF1 instruction followed by an IF2 instruction. It is assumed that the processor 700 fetched instructions from the cache memory 750-300 prior to the transfer instruction using the address and level information stored in RICB register 750-902 is included.

03002A / 0883

The operation of the cache memory unit 750 with regard to the handling of the IF1 and IF2 instructions will now be explained in more detail. The IF1 instruction is decoded upon receipt by the cache memory unit 750 by means of the decoder circuits 750-922. The decoder circuits 750-922 cause the circuits of block 750-920 to generate signals to load the other instruction address register, which is believed to be the RICA register. Signals corresponding to the incremented value of the address contained in the IF1 instruction are loaded into this register. This means that during the first T clock cycle the addresses are incremented by 1 from the switch 750-530 by means of the circuit 750-912 and into the address bit positions of the RICA instruction address register 750-900 upon the occurrence of the 1/2 T clock signal CLKHT100 can be loaded when the RICA100 signal is a binary signal 1. The signal RICA100 is output by the circuits 750-920 as binary signal 1 when the signal ENBSTRBAOOO according to FIG. 7e occurs as binary signal 0 during the first half of the first T clock cycle.

The IF1 instruction address is also used as an input signal to the address list circuits of block 750-502 via the ZDAD switch 750-530 for the execution of a search cycle submitted. Since the instruction block is not contained in the cache, the circuits generate of block 750-512 the relevant hit signals RAWHITOOO, HITT0TB010 and HITT0IC010, the are indicative of a fault condition and are sent to areas 750-1, 750-5 or 750-9.

In the event of an error condition, the circuits of block 750-526 according to FIG. 7c switch the address list assignment flip-flop 750-52600 in the 1 state to the occurrence of the signal RAWHRTOOO as a binary signal 1.

03002W0883

The signal ALTHITOOO, which is a binary signal 1, causes the from the address list 750-500 read out circular bit signals to be loaded into the register 750-50400. The concerned Circular signals are incremented by 1 to indicate the next level for exchange. These signals are then rewritten in the address list 750-500 in the addressed memory location.

In addition, the circular signals from the register 750-50400 as signals TBRR0100-2100 to the transit block buffer 750-102 for subsequent loading into this Buffer released.

In addition, the full / empty bits and the more significant Bits of the IF1 instruction address (these are bits 10-23) in the address lists 750-500 and 750-502 are written into the memory space that is replaced by the lower-order Bits of the IF1 address (these are bits 24-33J. Upon the occurrence of the next T clock signal the FDIRASN flip-flop goes into the zero state reset, which causes the address list allocation cycle is completed.

It should be understood that due to the faulty state decoding of the IF1 instruction results in the level 1 valid bit and hit / miss positions of the RICA instruction address register 750-900 to a binary state 1 or 0 can be set (which means that the hit signal HITT0C2100 is a binary signal 0). Accordingly the level signals placed in the level 1 bit positions of the RICA instruction address register 750-900 are loaded are disregarded since the processor 700 is accessing the block of instructions, which respond to the IF1 command from the IBUF1 area 750-715 have been called and not from the cache

030024/0883

"" Too ■ ·

M £ 949787

memory 750-300 (which is signaled via the lines IBUFRDY and USETBRDYj.

Before switching over the FLDTBVALID flip-flop 750-11414 according to FIG. 7a, before the address list assignment cycle the write address signals FTBPTRO100-1100 of of the pointing device 750-106 is decoded. This leads to, that the IF1 instruction address is written into the next available memory location of the transit block buffer 750-102 will. This means that when the T clock signal occurs, the address list search process ended, the IF1 address signals in one of the transit block storage locations of the buffer 750-102 as a result of the Faulty state to be loaded. At this point there will be a corresponding space in the command queue 750-108 loaded with the necessary control information that is required for the transmission of the IF1 command to the Memory is needed.

Since the requested block of instructions is not contained in the cache memory 750-300, the signal occurs FRDMISS020 from the control miss flip-flop of the area 750-9 (not shown) as binary signal 0, while the Signal FRDMISS120 from the same flip-flop as binary signal 1 occurs. As can be seen from Fig. 7a, the signal FKDMISS020 causes the AND / NAND gates 750-11708 to 750-11710, to output the CPU stop signals CPSTOPOOO-005 as binary signals 0, which is effective for stopping the processor operations on the subsequent T clock or be held. At the same time, the signals FRDM1SS120 and FlF2SEARCHOOO and the NAND gate 750-11706, that the signal HOLDSEAkCHOOO is output as a binary signal 0. This signal in turn causes the AND / NAND gates 750-11714 to 750-11716 output the internal hold signals HOLDDMEMOOO-003 as binary signals 0. Through this The execution of further operations by the cache memory areas 750-1, 750-5 and 750-9 is allowed for as long

030024/0883

held until the IF1 address list mapping is complete is and until it is determined whether the IFI command is on. '. declined a transfer command and whether it was in the continue or GO state or in the stop state (NOGO).

During the period of time that the processor 700 is being held, the address list assignment is terminated, and the above statement is made. In the event that the IF1 command is based on a transfer command is what is signaled by processor 700 as a NOGO command, that will be in the transit block buffer 750-102 stored IF1 instruction deleted as explained will. In this case the other RICB command register 750-902 becomes the command address register used, and the address contained in this register, which is not incremented, is used for access to the next instruction into cache 750-300 when the next 1/2 T clock signal occurs.

Since it has been assumed that the IF1 instruction refers to a Transfer Command, which is a Transfer GO command indicating that the IF2 command is to be carried out, the decoding of the IF2 instruction causes the AND / OR gate 750-11402, the signal SETIF2TIME100 to be output as binary signal 1 (which means that the NO-GOO30 signal is a binary signal 1). aside from that the signal SETIF2SEARCH100 is output as binary signal 1. This sets the FIF2SEARCH flip-flop 750-11400 to the 1 state in the absence of a delete command signal, which is received by the processor 700 (which means that the signal CANCELO12 is a binary signal 1 is).

The flip-flop 750-11400 causes the output of the signal FIF2SEARCH000 as a binary signal 0, whereby the NAND-

030024/0883

Element 750-11706 the signal H0LDSEARCH000 as a binary signal 1 gives up. This means that the internal operations of the cache memory areas are held on again 750-1, 750-5 and 750-9 avoided.

At this point the FLDTBVALID flip-flop becomes 750-11414 set to the 1 state because the HOLDMEMOOO signal is on Binary signal is 1 with the occurrence of the T clock signal. This means that in the event of a fault, the signal HITT0TB010 causes the FLDTBVALID flip-flop 750-11414 according to FIG. 7a to respond to the occurrence of the T clock signal to switch to the binary state 1 when the FDIRASN flip-flop is set. On the occurrence of the The next T clock signal causes the contents of the input pointers 750-106 and 750-108 can be increased by 1 during the formation of the next command. The tax code bits in question are set and written into the buffer tag area of the transit block buffer 750-102.

As can be seen from FIG. 7a, the decoding of the 1F1 command causes the AND gate 750-11420 to form the FIK1ASSIGN flip-flop 750-11418 switches to binary state 1 in the event of an error state (which means that the signal SETLDTBVALID100 is a binary signal 1). On the decoding of an IF2 command, the FIF2ASSIGN flip-flop 750-11410 switches to binary state 1 upon occurrence of the FIF2SEARCH010 signal as binary signal 0 or of the EISIF2000 signal as binary signal 1 (operation of a Special type). In addition, the AND gate switches 750-11426 the FRDQUAD flip-flop op 750-11410 as a result of a fault condition to the binary state 1.

The write tag and read quad tag bit positions of the license plate memory 750-10238 are converted into binary ones, with a view to

030024/0883

that the signals FORCEBYPOOO and FRDQUAD1OO as binary signals 1 occur. The FORCEBYPOOO signal is generated by AND circuit 750-52630; it is usually a binary signal 1. The signal FRDQUAD100 is generated by the FRDQUAD flip-flop when the FLDTBVALID flip-flop 750-11414 switches to the binary state 1.

On the occurrence of the T clock signal of the address list assignment or allocation cycle, the IF1 command is taken from the transit block buffer 750-102 upon occurrence the output pointer address signals from instruction queue 750-107 into RDTS register 750-119 via the ZTBC position of the ZDTS switch 750-118. The level signals TBRR0100-2100 respond to the occurrence of the 1/2 T clock signal held in the addressed transit buffer space. The IF1 command is on the DTS lines Transferred via the switch 750-102 according to FIG. 4 to the system interface unit 100. The one in question Incoming memory identification signals are loaded into RMITS register 750-124 and control signals are issued loaded into the control register (not shown). These signals are sent to the MITS or SDTS lines. For further information regarding the generation and use of control signals, refer to the US-PS 40 06 466 pointed out.

As mentioned earlier, each transit block location is an I-call-1 and an I-call-2 flag flip-flop associated. As can be seen from Fig. 7a, during the I-call-1 arbitration cycle, the I-call-1 flag flip-flop, which corresponds to the memory location designated by the write pointer signals FTBPTROOOO-1000, which are decoded by the decoder circuit 750-10601 are set to the binary state 1. Be at the same time reset the other three I call 1 flag flip-flops to binary 0 states. This means that then, if the input pointer points to memory location 0,

030024/0883

the signal 1N0100 is a binary signal 1, while the Signals 1N1100-31 binary signals are 0. This has the consequence that the F1F10 flip-flop in the binary state 1 is set and that the FIFH-13 flip-flops into the Binary states 0 are reset. The multiplexer circuit 750-1255 is triggered by the signal FIF1ASS1GN100 controlled in such a way that as output signals the signals IN0100-3100 can be selected, which are output to the position 1 connections. this leads to to the fact that the I-call-1 flip-flop, which the relevant Storage space is assigned to the binary state 1 is set. When the signal FIF1ASSIGN100 switches and occurs as a binary signal 0, then the multiplexer circuit 750-10255 is caused as output signals select the signals HOLiX) 100-3100, the are delivered to their position-O-connections. This Action causes the I call 1 flag flip-flop to be held in the binary 1 state.

The execution of the IF2 instruction by the cache storage unit 750 is similar to executing the IF1 instruction. The IF2 address is used as an input to the address list circuits of block 750-502 via the ZDAD switch 750-530 for a search cycle of operation.

Before the address list allocation cycle (i.e. when the FLDTBVALID flip-flop 750-11414 is in the binary state 0) the write address signals FTBPTRO100-1100 decoded by the input pointer device 750-106, resulting in the IF2 instruction in the next available Storage space of the transit block buffer 750-102 is written.

Upon the occurrence of the next T clock signal, the FLDTBVALID flip-flop 750-11414 set back to the 1 state, together with switching the

030024/0883

FDIRASN flip-flops. In response to the next T clock signal becomes the contents of the input pointer devices 750-106 and 750-108 in the course of forming the next Command increased by 1. In addition, the tax code bits in question are set and stored in the Buffer flag area of the buffer 750-102 is written in the manner described above.

During the address list allocation cycle, the signals from the circulating register 750-50400 are incremented by one and rewritten in the address list 750-500. In addition, the circulating signals are used as signals TBKR0100-2100 delivered to the transit block buffer 750-102 for subsequent loading into that buffer. Beyond that the full / empty bits and the more significant bits of the IF2 address (these are bits 10-23J in the address lists 750-500 or 750-502, namely in those memory locations that are replaced by the lower-order Bits of the Ii? '2 address are designated (these are bits 24-;.

Due to the presence of the faulty state, the decoding of the 1F2 command also has the effect that the level 2 validity bit and hit / miss positions of the RICA instruction address register 750-900 are a binary 1 and binary, respectively lead (which means that the hit signal HITT0C7100 is a binary signal 0). The level signals that are in the level 2-bit positions of the RICA command address register 750-900 are also disregarded, since the processor 700 removes the command block called in response to the IP2 command from the IBUF2 area 750-717 and not from the cache memory 750-300.

As can be seen from Figure 7a, during the I-RUI-2 arbitration cycle - which is determined by the fact that the FIF2-ASSIGN flip-flop 750-11410 on an IF2 command is switched to binary state 1 (which means that

030024/0883

- 29A9787

the signal FIF2SEARCH010 is a binary signal O) - the l-call-2-tag flip-flop corresponding to the Storage location designated by the write pointer signals FTBPTROOOO-1000, which are indicated by means of the Circuit 7X> -10601 are decoded into the binary state 1 set while the other three I call 2 flag flip-flops reset to binary 0. This means that the signal FIF2ASSIGN100 causes multiplexer circuit 750-10256 to select position 1 signals IN0100-3100 as output signals. The I-call-2 flip-flop, which the IF2 instruction containing memory location is switched to binary state 1, while the remaining three flip-flops can be reset to binary 0.

Upon the occurrence of the T clock signal of the address list allocation cycle, the IF2 command is read from the transit block buffer 750-102 on the occurrence of the output pointer address signals from the command queue 750-107 and into the RDTS via the ZTBC position of the ZDTS switch 750-118 -Register 750-119 read in _o The level signals TBRR0100-2100 are loaded into the addressed transit buffer memory when the 1/2-T clock signal occurs. The IF2 command is transmitted to the system interface unit 100 in the same manner as described above.

It should be understood that each of the instructions placed in the RDFS register 750-702 respond to a T clock signal be loaded, which is based on the occurrence of the IF1 command Ies has been recorded, is loaded into one of the memory locations of the IBUF1 area 750-715, which by the signals WRTBUF0110-1110 on the occurrence of the subsequent 1/2-T clock signal are designated.

Q3002W0883

Specifically, when the system interface unit 100 begins to transmit information, the circuits in block 750-115 output the memory write request signal as a binary 1 signal. This means that the system interface unit 100 outputs a binary signal 1 on the DPFS line, which indicates that the first two words are being transferred to the cache memory unit 750. A binary signal 1 is also output on the ARDA line, which indicates that the requested information appears on the DFS lines. The presence of these two signals together with the write-cache flag signal which has been read from the buffer 750 to 102 to a binary 1 causes the circuits of block 75O-115 _f dispense the memory write request signal MEMWRTREQ100 a binary. 1 At this point, the system interface unit is outputting signals on the MIFS lines, and bits 2 and 3> which correspond to the signals MIFS2100 and MIFS3100. This causes the transit block buffer 750-102 to read out the address and level signals contained in the memory location containing the IF1 instruction stored. As a result, the two words transferred to the RDFSB register 750-712 are written into the cache memory 750-300 upon the occurrence of the T clock signal. These signals also address the corresponding memory location within the identifier area that read the write cache identifier signal associated with the IF1 instruction.

Referring also to Fig. 7a, it can be seen that those corresponding to signals DM1F2100 and DM1F3100 Bits 2 and 3, respectively, cause the multiplexer circuit 750-10260 to select the pair of I-call-1 and I-call-up 2 flag flip-flops corresponding to the transit block memory location storing the IF1 instruction

030024/0883

are. The outputs of these flip-flops supply the identification signals ZIF1FLG100 or ZIF2FLG100, which are sent to the Circuits of block 750-115 are delivered.

As can be seen from FIG. 7a, the signals ZIF1FLG100 and ZIF2FLG100 as binary signals 1 cause the NAND gates 750-11508 and 750-11509 the signals IBUF1100 or IBUF2100 as binary signals 1 during the output the first half of a T clock cycle (i.e. when the FHT100 signal is a binary 1). These Signals enable the IBUF1 and IBUF2 areas 750-715 and 750-717. The write address signals WRTBUF1100 and WRTBUF0100 are generated when signals FARDA010 or RMIFS1100 occur. Address these signals one of the storage locations of the IBUF1 and IBUF2 areas for writing the into the RDFS register 750-720 contained command word on the occurrence of the 1/2-T clock signal. This operation is for everyone Command word repeated. This causes the circuits of block 750-114 to apply a binary 1 signal to hand over the line IBUFRDY.

Specifically, referring to FIG. 7e, the states of the signals ZLEV1L0C000 and ZLEV1L0C100 are the through the AND / NAND gate 750-92130 in accordance with the setting of the hit / miss bit position of the RICA instruction address register 750-900 - the AND / OR gate 750-92137 cause the USETBRDY100 signal to be output as binary signal 1. The same In addition, signals cause logic element 750-92156 to output signal IFETCHRDYOOO as binary signal 1 issue, indicating that instructions will not be fetched from cache 750-300. That Signal ENABTBRDYIOO is passed through the multiplexer circuits 750-10255 and 750-10256 respond to the completion of an instruction call dispatch cycle as binary signal 1 submitted. The FIF1ASSIGN100 signals appear at this point in time

030024/0883

and FIF2ASSiGN100 as binary signals O. The result This process consists in the NAND gate 750-72233 emitting the signal TBRDYOOO as a binary signal 0, whereby the NAND gate 750-72234 emits signal 1BUFRDY100 as binary signal 1. At this point the processor is loading 700 by sending a binary signal 1 to the line RDiBUF, the command word sent to the ZDI lines into its RBiR register for processing. At this point the processor 700 is enabled or restarted (which means that the FRDMISS020 signal is a binary signal 1).

When all four instructions of the block are written into cache 750-300, execution is of the 1F1 command completed. At this point in time, the validity bit display that corresponds to the 1F1 command containing transit block memory location is reset to the binary state 0.

It will be understood that if the first instruction is transmitted to the processor 700 immediately it is possible for both instructions 1F1 and IF2 to be executed when processor 700 takes another branch or executes a transfer command. In this case there are instructions for the two commands resp. Commands 1F1 and 1K2.

In the manner previously described, processor 700 processes the branch instruction, resulting in another pair of IF1 and IF2 instructions is generated, assuming the same assumption that the transfer an ongoing transmission is. These commands are used by the cache memory unit 750 is processed in the same manner as described above.

03002A / 08 8.3

til

29A9787

As soon as the circuits of the area 750-1 according to Fig. 7a have signaled that the IF1 instruction will be taken into account in response to a transfer instruction which is a continue instruction, and as soon as the FLDTBVALID flip-flop 750J1414 in the binary state 1 is set - at this point in time the new IF1 command is in one of the storage locations of the transit block buffer has been loaded - the circuits of block 750-114 set the relevant memory location associated I call 1 flag flip-flop to the binary state 1. At the same time, the remaining three I-call-1 flip-flops including the one flip-flop which responds to the previous IF1 instruction become has been set, is automatically set back to the binary states 0.

The circuits of the rely on the subsequent loading of the new IF2 command into the transit buffer 750-102 Similarly, blocks 750-114 the I-fetch 2-flag flip-flop to the binary state 1, which is associated with the relevant memory location. To the at the same time the remaining three I-call-2 flip-flops, including the one flip-flop that was set to the previous IF2 command, automatically reset to binary 0.

This completes the I-call allocation cycle. At this point in time, the signals FIF1ASSIGN100 and FIF2ASSIGN100 appear as binary signals 0 due to the fact that the FLDTBVALID flip-flop 750-11414 is switched to the binary state 0.

Accordingly, the instruction words included in the previous instructions IF1 and IF2 are not written into the IBUF1 and IBUF2 areas 750-715 and 750-717 as a result of the resetting of the I-call 1 and I-call 2 flag flip-flops . This means that

030024/0883

then if the MIFS bits 2 and 3 received by the system interface unit 100 are included, causing the multiplexer circuit 750-10260 to generate the output signals the I-fetch 1 and I-fetch 2 flag flip-flops which are associated with the transit buffer storage location storing the IF1 instruction, the Signals ZIF1FLG100 and ZIF2FLG100 as binary signals 0 be delivered. As a result, the release of the areas IBUF1 and IBUF2 is blocked. This means that the The command words called up by the IF1 command are not written into the command buffer, but are instead rather only in the cache memory 750-300 in the inscribed in the manner explained above.

The same also applies to the command words that are called or fetched in response to the IF2 command. Accordingly only the command words that are called up in response to the new IF1 and IF2 commands are included in the Command buffer as well as the cache memory 750-300 written.

Due to the arrangement of the present invention, the cache storage unit 750 can dispatch the instructions Continue JLF1 / IF2 without waiting for the command words of a previously issued IF1 / 1F2 command are included. Indeed, the arrangement enables the previous IF1 / IF2 instruction to be deleted. Accordingly a sequence of such commands can be issued without referring to the instructions, which have been called up in response to such commands or commands, which the processing of these command blocks that are called in response to a new IF1 / IF2 command.

According to the preferred embodiment of the invention, in the case of a branch instruction instruction, which is a stop command (NOGO), moreover the

030024/0883

Switching the Fü ^ SEARCH flip-flop into the binary state 1 prevented. Additionally, the N0G0030 signal prevents the FLDTBVALID flip-flop 750-11414 and the FDIRASN flip-flop 750-52600 are switched to the binary states 1. In addition, this is done in the FRDMISS control flip-flop contained in the area 750-9 to the binary state 0 by the signal N NOGOO30 switched. Accordingly, the valid bit indicator bit remains in the binary state 0, which belongs to the transit block buffer memory location in which the IF1 / IF2 command is to be loaded. Furthermore, the associated IF1 / IF2 flag flip-flops remain in binary states 0. Thus, the instruction is disregarded and the processor 700 is allowed to use the Continue processing operations. In addition, the cache storage unit 750 is capable of a new one Process the IF1 / IF2 command immediately (which means that no internal hold signals are generated).

Accordingly, the arrangement of the present invention facilitates the processing of the IF1 / IF2 commands by an overlap in the processing of such commands or commands and the issuance of new commands or commands Commands with minimal interruption of processor operations is enabled.

At any given time, only one of the areas 750-715 and 750-717 is enabled (which means that only one of the signals ZIF1FLG100 and ZIK2FLG100 is a binary signal 1). When the pairs of Command words of the block are transferred to the cache memory unit 750, will Bit 1 of the RMIFS line and the signals FAKDAOOO and FDPFS100 encoded to determine which pair (usually even / odd) where 0 = even = words 0,1 and 1 = odd = words 2, 3 mean) and which word of the relevant pair is transmitted.

030024/0883

From Fig. 7a it can be seen that the comparator circuit 750-11465 is enabled when the signals USETBRDY100 and DATA100 appear as binary signals 1.

Referring to Fig. 7e, it can be seen that the states of signals ZLEV1LUCOOO and ZLEV1L0C100, the through the AND / NAND gate 750-92130 in accordance with the setting of the Trefier / Miss bit position of the RiCA command address register 750-900 are generated, the AND / OR Ulied 750-92137 cause the signal USETBRDY100 to be output as binary signal 1. This through The signal generated by the circuits of block 750-920 indicates that the cache memory unit 750 is responding to instructions waiting to be written into the IBUF1 area 750-715 or the IBUF2 area 750-717.

In addition, these circuits emit the signals ZKIB100 and ZRIB010 in the appropriate states, to provide an indication of which I-fetch flag to compare (i.e. the I-fetch 1 signal ZIF1FLGOOOO or the I-fetch-2 flag signal ZIF2FLG0000). The signals ZEXT0100 and ZEXT100, those from bit positions 8 and 9 of the RICA instruction address register 750-900 generated by the circuits of block 750-920 are used with the Signals M1FS1100 and DATA0DD100 compared to a To get an indication of when the requested command word is that word which has been recorded is.

When the comparator circuit 750-11465 determines that the command word written in the IBUF1 / IBUF2 area is the same command word as requested, then circuit 750-11465 asserts the IBUFCMPROOO signal as binary signal 0 shortly before the occurrence of the 1/2 T clock signal. The TBIBUFRDYIOO signal is used as a binary signal 1 after the occurrence of the 1/2 T clock signal

030024/088 3

issued when the command word is or is written in the IBUF1 / IBUF2 area.

The ENABTBRDYIOO signal is sent as a binary signal 1 to the Completion of the I-fetch 1 and I-fetch 2 arbitration cycle of operations submitted. At this point in time, the valid bit positions are in each of the IBUF1 and IBUF2 areas 750-715 and 750-717 reset to binary states. Accordingly, the ENABTBRDY100 signal prevents an incorrect generation of the command buffer ready signal IBUFRDY100 by the valid bit positions before resetting them. Since commands or instructions are to be fetched from the command buffer and not from the Cache memory 750-300, the signal IFETCHRDYOOO as Binary signal 1 occur.

From Fig. 7d it can be seen that the signals ZEXT0100 and ZEXT1100 cause the various memory chips to simultaneously read out the contents of the designated one storage location of the storage location pair. When a command word is written into the addressed memory location, this is taken from the Relevant memory location read out possible valid bit signal as binary signal 1 (which means that the signal IBUF1V100 or the signal IBUF2V100 is issued). This in turn leads in addition, that a corresponding link of the NAND gates 750-72230 and 750-72231 the signal IBUF1RDYOOO or the IBUF2RDY000 signal as a binary 0 signal. Accordingly, the NAND gate becomes 750-72232 operated in such a way that it outputs the signal TBIBUFRDY100 as binary signal 1.

As already mentioned, the NAND gate 750-72233 emits the signal TBRDYOOO as a binary signal 0, which is the case results in the NAND gate 750-72234 emitting the signal IBUFRDY110 as a binary signal. Also will

030024/0883

the requested command or instruction word is transmitted to the processor 700 immediately.

In detail, it is assumed that the first command word recorded is the even-numbered word of the first Word pair is. When the signal sent to the ARDA line occurs, the even-numbered signal becomes Word of the first word pair in the RDFS register 750-702 loaded upon the occurrence of the T clock signal. on the occurrence of a first 1/2 T clock signal becomes the content of the RDFS register is written into the IBUF1 area, namely in the even-numbered memory location for the relevant word pair, which is determined by the states of the signals FARDAOOO, FDPFS100 and RM1FS1100 is designated. The validity bit for the relevant memory location is set to 1.

When processor 700 is waiting for the even command word, the circuits of block 750-114 enter Binary signal 1 to the IBUFRDY line. The command word identified by the signals ZEXT0100 and ZEXT1100, which is contained in the RDFS register 750-720 is selected via the ZDIN switch and via the position of the ZDI switch 750-312 clock-controlled into the RBIR register of the processor in response to the occurrence of the T clock signal, while the odd-numbered Command word of the first pair of words is introduced clock-controlled into the RDFS register 750-702. Thereafter the processor 700 is restarted or triggered upon the resetting of the FRDMISS flip-flop what is done by generating a data recovery signal.

Upon the occurrence of the second 1/2 T clock signal the contents of the RDFS register 750-702 are in the odd-numbered Storage space for the relevant word

030024/0883

pair and the valid bit position is set to binary 1. When the processor 700 is waiting for the odd-numbered command word, the circuits of block 750-114 output a binary signal 1 to the IBUFRDY line, and the word in question is entered in the RBIK register of the processor upon occurrence of the T-Taitsignal loaded through the RDFS register 750-702.

The operations explained above are repeated for the second pair of instruction words. If the odd Word of the second pair of words is written into the IBUF1 area, namely in those Storage space, which is indicated by the signals FARDAOOO, FDPFS100 and RMIFS1100, then this is the Transfer completed. At this point in time, the transit block validity indicator associated with the relevant command is displayed reset to zero. When the cache write flag for the instruction is set to 1, the instruction words become also into the cache memory 750-300 via the RDFSB register 750-712 for the occurrence of the 1/2 T clock signal enrolled. The remaining command words in the block are taken from the IBUF1 area via the ZRIB switch and position 3 of the ZIB switch pulled out.

in a corresponding manner, the instruction words of the IF2 block picked up from the main memory written to the 1BUF2 area locations and cache 750-300 if the cache write flag is set to 1 (which is usually the case). It should be noted that processor 700 is not stuck in view of this that the fault condition is determined on the IF2 command. However, if the processor 700

030024/0883

is recorded, since all commands are extracted from the IF1 block, and on the recording of the IF2 command block waits - as soon as the requested Command word has been determined to be written into the INUF2 memory locations - then the Processor 700 triggered or released on the subsequently occurring T clock signal, and the requested Command word is sent to the ZDI bus line, as explained above. The remaining command words are then transferred from the IBUF2 area added the ZIB switch.

It should thus be evident that the immediate transmission of command words increases the performance of the processor 700 increases.

The invention thus creates a data processing system which has a data processing unit which is connected to a cache memory unit, also to be referred to as a notepad memory unit, which is connected to a main memory. The cache memory unit concerned contains a cache memory which is organized in a plurality of levels, each of which stores blocks of information in the form of data and commands. The cache memory unit concerned also contains a control arrangement, ¹ an instruction buffer for storing commands or instructions which have been received from the main memory, and a transit block buffer with a plurality of storage locations for storing read commands or read commands. The relevant control arrangement comprises a plurality of groups of bit storage elements, the number of which corresponds to the number of transit buffer storage locations. Each group contains at least one pair of command call indicators that are normally operative with the controller

030024/0883

29A9787

of writing first and second instruction blocks into the instruction buffer. Every time if a read command, which calls for commands or instructions of either a first or a second Block designated, is received by the processing unit, the identifier storage element, which is associated with the transit block buffer memory location into which the read command is or will be loaded, in the binary state 1 is set while the corresponding Identifier memory elements that are associated with the other memory locations, which contain outstanding read commands store, which identify command calls, in binary states 0 must be reset. This allows only such instructions to be carried out from main memory the read command in question are included in a designated area of the command buffer are to be loaded in order to allow overlaps in the processing of different commands, the command sabrufoperati one n. The instruction buffer has first and second areas for storing Commands or instructions that are received from the main memory. Any command buffer area contains a plurality of word storage locations, each of which has a number of bit positions. A specific bit position of the respective memory location is used to then display a message deliver when a command word has been written into the relevant memory location. With Control arrangement connected to each of the buffer memory areas is effective in such a way that it contains all of the word memory locations in binary states 0 is then reset when a command or command that includes a command or Instruction block requests from the main memory, is ready for transmission to the relevant memory. The binary state is set when a command word is loaded into the memory location

030024/0883

is. Uefenlbuffer standby circuits contained within the control arrangement are caused by the states of the specific bit positions of the memory locations, output signals for the processing unit in order to transmit the requested instruction words to the processing unit as soon as these words are taken from main memory.

030024/0883

L e r s e i t e

Claims (1)

Claims Cache memory unit for use in connection with a data processing unit for the purpose of achieving fast access to data and instruction words which are called up from a connected main memory in response to instructions which are received by the data processing unit, characterized in that an instruction buffer with a plurality of addressable memory locations are provided which are used to store sequences of the command words, that a bistable command display device is provided which allows a group of displays to be stored, the number of which corresponds at least to the maximum number of read commands that can be processed at any point in time, that with the display devices, with the processing unit and the command buffer, a control device is connected which is operated in response to the occurrence of each read command in such a way that it sends signals for switching over one of the displays of the particular read command in question Type associated group of displays from a first state to a second state is generated simultaneously with the switching of the other displays of the group in question to the first state, and that the displays in question control the control device in such a way that the relevant command buffer is released for writing only that Command words which are transmitted in response to a last read command of the specific read command type. 030024/080 ORIGINAL INSPECTED ~ ² ~ 2- / 87 2. Cache storage unit according to claim 1, characterized in that that the first and second states correspond to the binary states O and 1, respectively. 3. Cache storage unit according to claim 1, characterized in that that the instruction buffer further comprises a number of areas, each of which the respective Has a plurality of addressable memory locations that are used to store a specific sequence of command words serve that the bistable command display means a plurality of rows of bistable Has elements whose number corresponds to the maximum number of read commands that the Control device on the occurrence of a read command of the specific read command type, its read command is coded in such a way that it specifies the retrieval of command words of one of the specific sequences, is operated in such a way that signals for switching a first bistable element one of the relevant Read command associated rows of elements from a first state to the second state simultaneously with the switching of the corresponding first bistable elements of the other rows of Elements are ready in the first state, and that the relevant control device by the relevant a number of the bistable elements is controlled so that the designated a range of the number of Provided rows are only released for a writing of those command words, which on the specific Read command type have been transmitted, which is determined by the states of the relevant first bistable Elements is designated. 4. cache memory unit according to claim 3> characterized in that that the number of areas concerned is two, that one of the areas for storage 03002 ^ / 0803 2949797 a first sequence of command words that the other area is used to store a second The sequence of command words ensures that the number of bistable elements in the relevant row is two is that the one bistable element of the row in question from the first state to the second State is switched to the occurrence of a certain type of read command that is encoded in this way is that it denotes the retrieval of command words of the first sequence of command words, and that the other bistable element of the relevant series of bistable elements from the first state to the second The state can be switched over to the occurrence of a certain type of read command which is coded in such a way that that it designates the retrieval of command words of the second sequence. 5. Cache memory unit according to claim 4, characterized in that the particular read command type in question, which is coded so that it is the request of the command words denotes the first sequence corresponds to an instruction fetch instruction 1 which is encoded so that he the transfer of command words of a first half of a block of command words in the relevant defines a range, and that the particular type of read command in question which encodes in this way is that it designates the fetching of instruction words of the second sequence, corresponds to an instruction fetch instruction 2, which is coded to allow the transfer of the second half of the block to the other area specifies. 6. cache storage unit according to claim 3 »characterized in that that the control device contains an addressing device which is individually assigned to each of the in a plurality of provided rows of bistable Elements is coupled, and that the addressing device generates signals through which the switching of the relevant one bistable element of a next available row in the second state the occurrence of the relevant specific read command type and the switching of the corresponding bistable Elements of the remaining rows in the first state is enabled. 7 «cache storage unit according to claim 6, characterized in that that each bistable element has an input terminal and an output terminal that the bistable command display device a first multiplexer circuit device / a first row of input terminals, each of which with the addressing device and the output terminal a first bistable element of a different series of bistable elements is connected, that the first multiplexer circuit means has a second series of input terminals, the are connected to the addressing device that the first circuit device in question a Having a plurality of output terminals, each of which is connected to the input terminal of the first bistable element Another series of bistable elements is connected to that of the relevant command indicator a second multiplexer circuit device with a first row of input connections, each of which with the addressing device and the output terminal of a second bistable Element of the relevant other series of bistable elements is connected that the second multiplexer circuit means has a second series of input terminals, each of which is connected to the addressing device that the second multiplexer circuit a plurality D30024 / Q883 of output terminals, each of which is connected to the input terminal of the second bistable element the other series of bistable elements in question is connected to that of the control device one with the first multiplexer circuit device and the second multiplexer circuit device contains associated sharing facility that accesses the Occurrence of the specific type of read command that causes the fetching of command words of the first or second Sequence denotes, first or second control signals to be generated by which the first or second Multiplexer circuit device to the relevant output connections the signals from the addressing device allowed to deliver, and that one of the first bistable by the signals in question Elements or the second bistable element of the relevant next available series of bistable elements Elements designated by the address signals enter the second state at the same time with the resetting of the first or second bistable elements of the remaining rows in the first state is switchable. 8. cache memory unit according to claim 7, characterized in that the first multiplexer circuit means a first input terminal which carries a voltage corresponding to the second state, a second Input terminal which carries a reference voltage corresponding to the second state, and an output terminal comprises that the second multiplexer circuitry a first input terminal connected to the output terminal of the first multiplexer circuit means is connected, a second input terminal carrying the reference signal, and an output terminal comprises that the first multiplexer circuit device and the second multiplexer circuit device in the absence of the first and second Q3002WQOÖ1 -6- £ 949787 Control signals are operated so that the voltage from the input terminal of the first Multiplexer circuit device to the output terminal of the second multiplexer circuit device can be issued to signal the termination of the command call-assignment operation cycle, and that the delivery of the voltage in question to the occurrence of a consequence of the particular in question Read command type is carried out, which designates the fetching of the first and second command word sequences, such that a subsequent transmission of the command words to the processing unit is enabled. Cache memory unit according to Claim 8, characterized in that the control device is an output multiplexer circuit device having a first number of input terminals, each of which connected to the output terminal of another bistable element of the first bistable elements is that the output multiplexer circuit means concerned has a second number of input terminals each of which is connected to the output terminal a corresponding different second bistable element is connected that the output multiplexer circuit device has a number of control connections which are used to receive a series of identification signals which denote the particular type of read command in question, command words from main memory upon occurrence to the cache memory unit, and that the output multiplexer circuit means has two output terminals, each of which is connected to one of the instruction buffer areas, wherein the output multiplexer circuit means for the occurrence of the relevant series of identification signals is controlled in such a way that it sends signals 030024/0883 from one of the first and determined by the relevant series of identification signals emits second bistable elements to the two output connections, with the relevant Signals indicates which command buffer area is to be released for writing the command words. 1Oo cache memory unit according to claim 6, characterized in that that a transit block buffer with a number of storage locations for storing the maximum Number of read commands is provided and that the transit block buffer with the addressing device is connected and upon the occurrence of the relevant signals, the storage of the specific Releases read command type into a next available space, that of the next available row of is associated with bistable elements. 11. Cache memory unit according to claim 10, characterized in that a buffer memory is provided which is organized in a plurality of levels, each of which has a number of views of the word memory locations, that the transistor block buffer has a first area with the maximum number of memory locations, each of which is used to store a block address and to store level signals which indicate the level or the block of word storage locations within the buffer memory into which a block of words retrieved from the main memory is to be written, so that the transit block buffer has a second area with the maximum number of memory locations, each of which contains a number of bit positions for storing a corresponding number of control identifier indicators that the first area and the second area are connected to and through the addressing device Addressing device can be controlled in such a way that the block address and the level defined by the relevant specific read command type is designated in the next available memory location of the first area can be written, and that a certain bit position of the number of bit positions the next available memory location of the second area can be switched to a specific state, in which an indication is provided that the particular type of read command in question has occurred on the occurrence command words retrieved in the relevant block and level of the buffer memory regardless of the states of the first and second bistable elements of the associated series of bistable elements Elements are to be inscribed. 12. Cache storage unit according to claim 11, characterized in that that the control device has an output selection circuit means for generating of control signals, which designate that command buffer area, which is used for the operation is to be released that the relevant output selection circuit means with the rows of the first and second bistable elements and the instruction buffer is connected and that the output selection circuit means upon the occurrence of a series of the memory identification signals from the main memory is operated such that the first and second stable elements of the relevant series of bistable Elements are selected by the relevant series of memory identification signals for the Generation of the control signals are designated. 13 · Cache memory unit according to claim 12, characterized in that that the control device also has bistable devices for signaling the termination of the Load the particular type of read command in question into 2149797 the transit block buffer contains that the respective bistable devices with the first and second bistable elements of the rows of bistable elements are connected that the bistable in question Devices from a first state to a second state upon the occurrence of the respective specific read command type can be switched when a signal is present that indicates that the instructions requested by the instruction in question are not stored in the buffer memory are, and that the bistable devices concerned in the second state the transit block buffer to terminate the saving of the command in the next available memory location and the Switching one of the first and second bistable elements determined by the particular read command type in question the next available row are designated, releases into the second state. 14. Cache memory unit according to claim 13 »characterized in that that the bistable devices have an input device connected to the processing unit for recording a stop signal (NOGO) is connected, which provides an indication that the designated by the particular read command type Command transmission does not take place that the bistable devices by the relevant stop signal are prevented from switching to the second state when the specific read command type occurs, and that the bistable devices concerned terminate the storage in the first state of the relevant command and switching the relevant one bistable element of the first and prevent second bistable elements of the next available row in the second state. 030024/0891 15. Cache storage device for use in conjunction with a data processing unit for the purpose of achieving quick access Data and commands that are sent from a connected main memory to the occurrence of commands retrieved, which are recorded by the data processing unit, characterized in that that an instruction buffer with a large number of addressable memory locations for storing Command word sequences are provided that a transit block buffer with a number of storage locations is provided for storing a maximum number of read commands in the course of a process at any time that the transit block buffer serve a multitude of bistable Facilities the number of which corresponds to the number of transit block buffer storage locations, and one Control device, which is connected to the processing unit, the transit block buffer and the command buffer, that the control device on the occurrence of a certain type of read command signals for storing the relevant read command into a next available memory location of the transit block memory locations and for switching one corresponding bistable element of the bistable elements provided in a plurality of the first State into the second state simultaneously with the switching of the remaining bistable elements into the generated first state, and that each bistable device in the second state the control device causes the command buffer to be released for writing in the command words which respond to the occurrence of a last read command of the particular type in question that was called by the Variety of bistable elements is designated. OJOU2WOÖ93 " ¹¹ - £ 949787 16. Cache memory unit according to claim 15, characterized in that that the instruction buffer has a number of areas, each of which has the plurality of addressable memory locations for storing a specific sequence of instruction words that contains the Plurality of bistable devices having a plurality of rows of bistable elements, whose Number corresponds to the number of transit block buffer storage locations that the control device on the Occurrence of any particular type of read command which is coded to allow the fetching of command words from the relevant particular designated a sequence, generates signals with the help of a first bistable Element of a series of bistable elements from the first state to the second state simultaneously can be switched to the first state when the first bistable elements of the remaining rows are switched over, and that the control device is controlled in this way by the relevant series of bistable elements becomes that the designated one of the number of areas for writing only those Instruction words are released to the cache memory unit upon the occurrence of the last read instruction of the particular type have been transmitted. 17. Cache memory unit according to claim 16, characterized in that that the number of said areas is two, that the first area for storing one The first sequence of command words is used, that the second area is used to store a second sequence of command words serves that the number of bistable elements within the relevant row is two, that the first bistable element from the first state to the second state on the occurrence of a certain Read command type is switchable out, which is coded so that it calls up command words of the first Sequence denotes, and that a second bistable 030024/0883 Element from the first state to the second state upon the occurrence of a certain type of read command is switchable out, which is coded so that it designates the retrieval of command words of the second sequence. 18. Cache storage unit according to claim 17, characterized in that that the particular type of read command in question which is encoded to cause the polling which designates instruction words of the first sequence corresponds to an instruction fetch instruction 1 which encodes in this way is that it allows the transmission of command words of the first half of a block of command words in denotes the relevant first area, and that the relevant particular read command type which so it is coded that it designates the fetching of the instruction words of the second sequence, an instruction fetch instruction 2 corresponds, which is coded so that it prevents the transmission of the second half of the relevant block referred to in the second area. 19 · Cache memory unit according to claim 16, characterized in that that the control device has an addressing device, which individually with Each of the plurality of series of bistable elements is coupled, and that the Addressing device generates signals through which the switching of a bistable element of a next available row in the second state upon the occurrence of the relevant particular read command type and switching the corresponding bistable elements of the remaining rows in the first State is released. 20. Cache memory unit according to claim 19, characterized in that that the bistable elements each have an input connection and an output connection have that the control device also has a 0JOÖ24 / OÖÖ3 first multiplexer circuit device having a first row of input terminals which each with the addressing device and the output connections of the first bistable element a different series of bistable elements are connected that the first multiplexer circuit means has a second row of input terminals connected to the addressing device are connected that a plurality of output terminals of the relevant multiplexer circuit device is connected to the input terminals of the first bistable element of the other series of bistable elements in question, that a second multiplexer circuit means is provided with a first row of input terminals is, each with the addressing device and with the output terminal of the second bistable Element of the other series of bistable elements are connected that the second multiplexer circuit means a second series of input terminals, each connected to the addressing device are, and has a plurality of output terminals connected to the input terminal of the relevant second bistable element of the other series of bistable elements in question are connected to that with the first multiplexer circuit device and the second multiplexer circuit device an enabling device is connected to the occurrence of the particular type of read command in question, which the Retrieval of instruction words of the first sequence or the second sequence denotes, a first or a second Control signal generated by which the first multiplexer circuit is enabled for the delivery of the Signals from the relevant addressing device to the output connections, and that through the relevant Signals one of the first bistable 030024/0883 Elements or one of the second bistable elements of the next available row of bistable elements Elements designated by the address signals enter the second state simultaneously with the Resetting the first or second bistable elements of the remaining rows of bistable elements can be switched to the first state. 21. Cache memory unit according to claim 20, characterized in that that the control means is an output multiplexer circuit means contains. 22. Cache storage unit according to claim 19, characterized in that that a buffer memory is provided, which is organized in a plurality of levels, each of which comprises a number of blocks of the word storage locations, and that the transit block buffer one has a first area and a second area each having a number of storage locations. 23. Cache memory unit according to claim 22, characterized in that that an output selection circuit means is provided for generating control signals which indicate which command buffer area is released for operation. 24. Cache memory unit according to claim 23, characterized in that that the control device contains a bistable device that terminates the loading of the specific read command type in one of the storage locations of the transit block buffer and the connected to the first and second bistable elements of the respective rows of bistable elements is that the bistable device in question changes from a first state to a second state the occurrence of any particular type of read command toggles in the presence of a signal which provides an indication that the The instructions requested by the command are not stored in the buffer memory and that the relevant bistable device in the second state the transit block buffer to terminate the storage of the command to the next available memory location and toggling one of the first and second bistable elements in the second state releases which element by the determined Denotes read command type of the next available row is. 25. Cache storage unit according to claim 24, characterized in that that the bistable device has an input device which is connected to the processing unit is connected and which serves to receive a stop signal that the bistable device through the relevant stop signal at the switchover to the second state when the relevant particular one occurs Read command type is prevented and that the bistable device in question is in the first state the termination of the storage of the relevant command and the switchover of the relevant one bistable element of the first and second bistable elements of the next available row of Elements in the second state prevented. 26. Cache memory system for use in connection with a data processing unit for the purpose of Achieving quick access to data and commands from a connected main memory are called up in response to commands received by the data processing unit, in particular according to one of claims 1 to 25, characterized in that first and second command buffers are provided can be seen, each of which has a large number of addressable memory locations for storing first and second sequences of command words have that a transit block buffer with a number memory locations are provided that are able to store the maximum number of read commands, which are processable at any point in time that a plurality of pairs of bistable Elements is provided, the number of which corresponds to the number of transit block storage locations that with the processing unit, the plurality of pairs of bistable elements, the transit block buffer and the command buffers are connected to a control device which responds to the occurrence of each command fetch read command hin, which denotes the retrieval of a first or second sequence of command words, generates signals, with the help of which each read command is transferred to a next available memory location of the transit block buffer memory locations storable and the relevant one bistable element of a corresponding pair of bistable elements, which is designated by the relevant command fetch command, of a first state to a second state simultaneously with the switching of the first bistable Elements of the remaining pairs of bistable elements can be switched to the first state, and that the control device in question is one of the two pairs of bistable elements in question Command buffer, designated by bistable elements, for writing the command words in the sequence of Releases command words. 27. Cache memory system according to claim 26, characterized in that that a first bistable element of the relevant pair of bistable elements from first state to the second state upon the occurrence of a first command call read command 030024/0883 is switchable, which is coded so that it calls up command words of the first sequence of instruction words, and that a second bistable element of the relevant pair of bistable elements from the first state to the second state upon the occurrence of a second command call read command is switchable, which is coded so that it calls up command words the second sequence of command words. 28. Cache memory system according to claim 26, characterized in that that the control device has an addressing device which individually with the first and second bistable elements of the respective pair of bistable elements connected and the signals to enable the switching of one of the relevant bistable elements of a next available pair of bistable elements to switch to the second state in the case allows the command fetch read command to occur and, through the signals concerned, the appropriate a bistable element of the remaining pairs of bistable elements in the first state are switchable. 29. cache memory system according to claim 28, characterized in that each of the bistable elements one Input connection and an output connection, that the control device comprises a first multiplexer circuit device having a first row of input terminals, each of which is connected to the addressing device and the output terminals the first bistable element of a different pair of bistable elements is connected, that the first multiplexer circuit means has a second series of input terminals connected to the 03ÖG24 / 0883 Addressing device are connected, and has a plurality of output terminals that are connected to the input terminals of the first bistable element of the other pair of in question bistable elements are connected that a second multiplexer circuit means with a first row of input connections is provided, each with the addressing device and the output terminal of the second bistable element of the other pair of in question bistable elements are connected, that the second multiplexer circuit means a second Series of input terminals, each of which is connected to the addressing device, and one Has a plurality of output terminals, each with the input terminal of the relevant second bistable element of the other pair of bistable elements are connected to that with the first multiplexer circuit device and the second multiplexer circuit device one Release device is connected, which on the occurrence of the command fetch read command, which denotes the retrieval of command words of the first or second sequence of command words, a first or a second control signal is generated by which the first multiplexer circuit means for output the signals from the addressing device is enabled at the output connections, and that by the signals in question one of the first bistable elements or one of the second bistable Elements of the next available pair of bistable elements identified by the address signals is designated, in the second state simultaneously with the resetting of the first or second bistable Elements of the remaining pairs of bistable elements can be switched to the first state. 030024/0083 30. Cache memory system according to claim 29, characterized in that the control device has a Output multiplexer circuit device having a first number of input connections, with a second number of - ^ input connections, with a number of control connections and with having a pair of output connections that the control connections for receiving a number of Serve identification signals, which designate the command fetch read command, upon its occurrence Instruction words are transferred from the main memory to the cache memory system, and that the two output ports are each connected to one of the command buffers. 31. Cache memory system according to claim 28, characterized in that the cache memory unit contains a cache memory which is provided in a plurality of levels, each of which has a number of blocks of word storage locations, that the transit block buffer has a first area and a second area each with a number of memory locations and that the relevant areas of the transit block buffer are connected to the addressing device and are controlled by this addressing device in such a way that the block address and the level identified by the command read command can be written into the next available memory location of the first area , while a certain bit position of the number of bit positions of the next available memory location of the second area in question can be switched to the second state. 32 ", cache memory system according to claim 31", characterized in that the control device has an output selection circuit device. 030024/0881 £ 949787 33. Cache memory system according to claim 32, characterized in that the control device is a bistable Includes means to complete the loading of the command fetch read command into a the memory locations of the transit block buffer signals that the bistable device in question is using the first and second bistable elements of the pairs of bistable elements is connected that the relevant bistable device from the first state to the second state in response to the occurrence of each command fetch read command can be switched over when a signal is present, which provides an indication that the requested by the relevant command Instructions are not in the cache and that the bistable device concerned in the second state, the relevant command is stored in the next available one Storage space and the switching of the first or second bistable element, which by the relevant Command fetch command of the next available pair is designated to complete in the second state allowed. 34. cache storage system according to claim 33i, characterized in that that the bistable device terminates the storage of the command in the first state and the switching of the relevant one bistable element of the first and second bistable elements of the next available pair of bistable elements into the second state. 35. Cache memory unit for use in connection with a data processing unit for the purpose of achievement quick access to data and commands from a connected main memory recorded by the data processing unit 030G24 / OÖ83 Commands are called up, in particular according to one of Claims 1 to 34, characterized in that that a command address register device with a number of bit positions is provided, which allow to store an address of a next command word to which an access by the Data processing unit is to be made that an instruction buffer is connected to the main memory which contains a number of areas, each of which has a plurality of addressable storage locations for storing a sequence of command words, each memory location has a plurality of Bit positions for storing a command word and at least one other connected bit position which switches from a first state to a second state in the event that a command word is written into the relevant memory location, and that with the command address register device, a control device is connected to the processing unit and to the instruction buffer, which on the occurrence of a signal corresponding to the second state from the relevant one bit position of a the relevant memory locations an output signal generated for the processing unit in the event that the next is determined to be by the concerned Instruction register device designated instruction word received and in one of the buffer storage locations of the relevant one area is enrolled. 36. Cache memory unit according to claim 35, characterized in that that the first state and the second state correspond to a binary state 0 and a binary state 1, respectively. 37. Cache memory unit according to claim 35 or 36, characterized 03002A / 0883 characterized in that with the main memory and with the instruction buffer a data register device each of the instruction words received from the main memory as input signals able to deliver to the instruction buffer, and that with the data register device and with the processing unit an output device is connected which receives the next instruction word from the data register device then able to transmit to the processing unit when the recording of the relevant Word has been determined. 38. Cache memory unit according to claim 37, characterized in that the processing unit has a command register connected to the output device, that timing control circuits are provided which output the T clock pulse signals to the data register device and to the command register of the processing unit , ~ that the data register device is controlled by such a T- Clock pulse signal is controlled in such a way that the register means concerned stores the next instruction word, and that the instruction register of the processing unit is controlled by the next T clock pulse signal in such a way that it stores the next instruction word loaded into the data register means. 39. Cache storage unit according to claim 37, characterized in that that the timing circuits are connected to each of the respective areas and 1/2 T clock pulse signals issue that occur with the T clock pulse signals out of phase by 180 ° that the areas concerned each have a plurality of data input connections connected to the data register devices and have a plurality of control connections which are connected to the control device 030024/0883 are connected and have an enable input terminal and a reset input terminal, that the control device sends a reset signal to the occurrence of a certain type of command to the reset input terminal of a designated area such that all storage locations of the relevant area are reset to the binary state O, and that the relevant Control device for the occurrence of signals emitted from the main memory, * the A release signal to the release input connection is characteristic for the transmission of command words of the relevant designated area outputs, in such a way that the command words on the occurrence the 1/2-T clock pulse signals out into those Storage locations are written in through the to the other row of control connections given signals are designated. AO. Cache memory unit according to Claim 39 »characterized in that that the number of areas is 2, that each instruction has an instruction code and an address includes that the command code of the particular type of command is encoded so that it calls for a first or second sequence of instructions, and that the address is a group of memory locations within of the main memory, from which the relevant sequence of commands can be called up. 41. Cache memory unit according to claim 40, characterized in that that the control device responds to the occurrence of the specific type of command with a command code which calls for the first sequence of command words denotes the respective signals to the reset input terminal and to the enable input terminal a first area of the intended 030024/0883 Releases areas in such a way that all storage locations are reset to binary states O or the writing of each of the command words of the first sequence is enabled. 42. Cache storage unit according to claim 41, characterized in that that the control device responds to the occurrence of the specific command type with a command code, which designates the retrieval of the second sequence of command words, the signals in question to the reset input terminal and to the enable input terminal of a second area of the provided areas in such a way that all memory locations are reset to binary states 0 and that the writing of each of the instruction words of the second instruction sequence is enabled. 43. Cache memory unit according to claim 42, characterized in that that the stevedore ports have a number of read address ports that are linked to the Control device for receiving address signals are connected, which of certain bit positions the command address register means that one adjustable in a variety of positions Failure device with two rows of input connections is provided, one row of which is connected to the first area and the other row is connected to the second area that the relevant switch device a plurality of output connections which are connected to the processing unit, and that the failure device is wired so that it can be controlled by the control device in such a way that each of the command words is transmitted to the output terminals from one of the areas that are based on the occurrence of the Address signals are read out, which of the 030024/0333 relevant row of read address connections of the relevant one area are supplied. 44. Cache memory unit according to claim 40, characterized in that that a buffer memory is provided, which is organized in a plurality of levels, each of which contains a number of blocks of word storage locations used for storing data and Instructions serve that the instruction address register means further a first register and a second Register contains that the first register contains the number of bit positions for storing the address, a number of rows of control bit positions for storing indications indicating the source of the command words set, and comprises a number of series of level signals representing the levels of the buffer memory specify to the first and second sequences of the command words simultaneously from the data processing unit is accessed, and that the second register the number of bit positions for Storage of an address which includes indications and the number of series of level signals that are on a sequence of the specific command types can be stored. 45. Cache storage unit according to claim 35, characterized in that that the control device is a comparator circuit device of a first series and a second series of input terminals and an output terminal that is a pair the first and second rows of the input connections are connected in such a way that signals are comparable, by which it is determined when the requested command word is that command word which consists of the main memory has been recorded that the comparator circuit means on the determination Ö30024 / Q883 a correspondence between those output to the first and second rows of input terminals Signals an output comparator signal is generated, and that with each of the instruction buffer areas and the comparator circuit means individually command buffer standby control means is connected, which is controllable by the relevant output comparator signal in such a way that the output signal when the relevant signal occurs from the relevant one bit position to one of the memory locations of said one area is generated. 46. Cache memory unit according to claim 45, characterized in that that another pair of the first and second rows of input terminals are so wired is that signals are comparable which designate the area into which those received from the main memory Command words are to be written in. 47. Cache storage unit according to claim 45, characterized in that that one connection of the relevant pair of the first row of input connections is wired in this way is that it receives a memory identification signal which is encoded to designate the transmitted instruction word pair, and that the other terminal of the relevant connection pair receives a coded signal, which provides an indication of which Command word of the word pair concerned is recorded. 48. Cache memory unit according to claim 47, characterized in that that a connecting device is provided, which the memory identification signal to the stevedoring device conducts, and that the control device is connected to the relevant connecting device and the command buffer connected logic device, which is responsive to the occurrence of the 030024/0883 Encountering memory identification signal generates a first write address signal, which that Half of the large number of memory locations in the relevant area in which the command word is inscribed. 49. Cache storage unit according to claim 48, characterized in that that a logic device is provided which is coded from the main memory in this way Receives control signals that there is an indication of the transmission of a word pair that the relevant Linking device generates a coded signal in response to the occurrence of the control signals, by means of which the relevant command word is designated, and that the control device contains a circuit arrangement, which is used to receive a specific control signal of the control signals and which a second write address signal which denotes that half of the multiplicity of memory locations into which the Command word is written. 50. Cache storage unit according to Claim 45, characterized in that that each area has a plurality of data input ports, of which at least a data input terminal is used to receive a voltage signal which is characteristic of a binary signal 1 that a plurality of write address connections are also provided, which are associated with the control device are connected, and that the relevant one bit position of that memory location that is through the Signals, which are output to the plurality of write address_connections, are addressed from the binary state 0 is switched to the binary state 1 in the event that the relevant command word is in other bit positions of the plurality of bit positions of the relevant memory location is written. 030024/0883 51. Cache memory unit according to claim 50, characterized in that that each area has a plurality of output data connections, of which at least an output data connection corresponds to the one bit position which is connected to the control device, that a plurality of read address connections are provided which are connected to specific bit positions of the command address register device are connected, and that one of the data output connections outputs a binary signal 1 to the control device in the event that a The command word is written into the memory location, which is denoted by the address bits contained in the particular bit positions indicated at the plurality of read address connections are applied. 52. Cache device for use in conjunction with a data processing unit for the purpose of achieving quick access to data and commands, the commands received by the data processing unit from a connected main memory are retrieved, in particular according to one of claims to 51 »characterized in that a command address register device is provided with a number of bit positions that are used to store an address serve, under which the data processing unit can access the next command word, that an instruction buffer is connected to the main memory, which has a first area and a second area comprises that the first area has a plurality of addressable memory locations for storing a first Sequence of command words contains that each memory location a plurality of bit positions for storing one Command word and at least one further bit position for storing a first command buffer validity indicator which provides signaling in the event that the relevant command word is in the memory location has been inscribed that the second area Ö3Ö024 / 0883 has a plurality of memory locations for storing a second sequence of command words, that each memory location has a plurality of bit positions for storing a command word and at least one further bit position for storing a second command buffer validity indication which provides a signaling in the event that the relevant command word is written in the memory space that a control device is provided which allows the operation of the buffer memory to be controlled, and the instruction address register device is connected to the first area, the second area and the processing unit, that the control device in question, upon the occurrence of each, a transmission of a Sequence of commands designating commands of a first or second specific command type to generate reset signals, by means of which each of the memory locations provided in a plurality of the first area or the second area into the first state it is feasible that a command buffer readiness control logic device is provided, which show the corresponding signals with the command buffer for receiving the first and second command validity, with the main memory for receiving signals that designate the command word which is transmitted to the relevant area and is connected to the instruction address register means for receiving signals which designate the next instruction within the one instruction sequence which is accessed by the data processing unit, and that the command readiness control logic means on the occurrence of the signals from the buffer, from the instruction address register means and the main memory is operated to generate an output in the event that it is detected 03002 ^ / 0863 is that the next command word is received and written into one of the memory locations of the buffer is, with the immediate transmission of the relevant word to the data processing unit is released. 53. Cache storage unit according to Claim 52, characterized in that that a data register is provided which communicates with the main memory and the instruction buffer areas is connected that the relevant data register each of the instruction words that it is from the Main memory has taken up as is able to deliver input signals to the command buffer areas, and that an output device is connected to the data register and the processing unit, the the next instruction word from the relevant data register to the processing device can then deliver when the inclusion of the relevant command word has been determined. 54. Cache memory unit according to claim 53, characterized in that that the processing unit has an instruction register connected to the output device includes timing circuits providing the T clock pulse signals to the data register and to the command register of the processing unit output that the data register by one of the T clock pulse signals is caused to store the next instruction word and that the instruction register of the processing unit caused by the next T clock pulse signal, the next instruction word from the data register forth to save. 55. Cache memory unit according to claim 53 »characterized in that that a buffer memory is provided, which is organized in a plurality of levels, that the instruction address register means includes a first register and a second register and that the first register contains the number of bit positions for storing the address, a number rows of control positions for storing indications indicating the source of the command words, which are requested by the processing unit, and a number of rows of Level signals defining the levels of the buffer memory, making up the first and second Sequences of the command words can be called up simultaneously by access from the data processing unit. 56. Cache storage unit according to Claim 52, characterized in that that the control device contains a comparator circuit device and that the command buffer ready shaft control logic device individually with the first and second areas of the Command buffer and the comparator logic device is connected and by the output comparator signal is controllable in such a way that an output signal can be generated in the event that one of the signals from the other bit positions of one of the memory locations of a corresponding area of the first and second area occurs. 57. Cache storage unit according to Claim 56, characterized in that that one input terminal of the pair of the first series of input terminals for receiving the memory identification signal is used. 58. Cache memory unit according to claim 57, characterized in that that a logic device for receiving the control signals from the main memory is provided and that the control device has a control signal recording circuit for generating a contains the second write address signal. Ü30024 / 0883 59 · Cache memory unit according to claim 56, characterized in that that the two areas provided each have a plurality of data input connections have, of which at least one data input connection is used to receive a voltage signal, which is characteristic of a binary signal 1 that also has a plurality of write address connections is provided, which are connected to the control device, and that the other concerned Bit position of the memory location addressed by the signals connected to the plurality of write address connections are applied, can be switched from binary state to binary state 1 in the case, that the command word in the other bit positions of the plurality of bit positions of the relevant Storage space is written. 60. Cache memory system for use in connection with a data processing unit for the purpose of Achieving quick access to data and commands from a connected main memory are called up in response to commands received by the data processing unit, in particular according to one of claims 1 to 59, characterized in that an instruction address register with a Number of bit positions is provided for storing control information and an address Serving a next command word to which is accessed by the data processing unit that a first instruction buffer with a plurality of data input connections for the inclusion of instruction words from the main memory is provided that the first Command buffer has a large number of addressable memory locations for storing a first sequence of the command words contains that each memory location has a large number of bit positions for storing an instruction G30024 / 0883 COPY f Word and at least one other bit position to store a particular indication for the event includes that the relevant command word is written in the memory location that a second Command buffer is provided with the plurality of data input terminals which are used to receive the Command words from the main memory serve that the second buffer the plurality of addressable Storage locations for storing a second sequence of the instruction words comprises that each storage location a number of bit positions for storing a command word and at least one further bit position for storing the particular display in the event that the command word is in the memory location is written that with the instruction address register, the processing unit and the first and second command buffers individually connected to a control device that is responsive to the occurrence a signal corresponding to the particular display concerned, an output signal for the Processing unit capable of generating, and that the relevant output signal generated in the case it is determined that the instruction word designated by the instruction address register of the main memory for the presence of a particular type of one of the instructions to the cache memory unit has been transferred and written into one of the memory locations in the command buffer, which memory location is designated by the particular type of instruction in question. 61. Cache memory system according to claim 60, characterized in that the first buffer and the second Buffers have a plurality of control connections which are connected to the control device and which an enable input terminal and a reset input terminal have that the control device 030024/0883 COPY a reset signal to the reset input terminal upon occurrence of a particular type of command a designated buffer for resetting all memory locations in binary states O, and that the control device responds to signals from the main memory which indicate the transmission of instruction words denotes, outputs an enable signal to the enable input terminal of the designated buffer, in such a way that each of the relevant command words is written into the memory locations, which are designated by the signals which are delivered to the other row of the control connections will. 62. Cache memory system according to claim 61, characterized in that the particular type of instruction in question is coded so that it is the transmission of a first sequence of command words denotes that the control device on the occurrence of the relevant specific type of command in a command code that enables the relevant first sequence to be called up denoted by command words, signals to the reset input terminal and to the enable input terminal of the first buffer, and that thereupon all storage locations in the first buffer are reset to binary 0 while writing each of the command words the first episode in question is released. 63. Cache memory unit according to claim 61, characterized in that that the control device responds to the occurrence of the particular type of command concerned an instruction code which designates the retrieval of the second sequence of instruction words, the signals to the relevant reset input connection and to the enable input connections of the second buffer, 030024/0083 in such a way that all storage locations are reset to binary states O and that writing of the respective command word of the second sequence is enabled. 64. Cache memory system according to claim 60, characterized in that that a data register with the main memory and with the data input terminals of the first and second instruction buffers connected that the data register of each of the main memory is able to output recorded command words as an input signal to the command buffer and that with the data register and an output device is connected to the processing unit which sends the next instruction word to be transferred from the data register to the processing unit after the recording has taken place. 65. Cache memory system according to claim 64, characterized in that the processing unit has an instruction register contains, which is connected to the output device, that timing control circuits are provided that emit the T clock pulse signals, and that the instruction register of the processing unit by the occurrence of the next T clock pulse signal is caused to store the next command word from the data register. 66. Cache memory system according to claim 61, characterized in that the control device has a row of read address connections which are connected to the control device and which are used for receiving of address signals from certain bit positions of the instruction address register means that a switch device adjustable in a plurality of positions is provided, the two rows of input connections, a number of which is connected to the first buffer and of which 080024/0883 COPY which the other row is connected to the second buffer that the switch means a plurality from output sans chilis s en that with the Processing unit are connected, and that the switch device by the control device in such a way it is controllable that each of the command words is sent to the output terminals from a designated buffer can be transmitted here, the relevant command words in response to the occurrence of address signals are read out, which are delivered to the relevant row of read address connections of a buffer are. 67. Cache memory system according to claim 60, characterized in that a cache memory is provided, which is organized in a plurality of levels, each of which has a number of blocks of word storage locations which are used to store the data and commands that the number of bit positions of the command address register a number of rows of bit positions for storing the scope of display » which determine the source of the command words, as well as a number of series of level signals, which determine the levels of cache memory from which first and second sequences of instruction words are simultaneously retrievable by access by the data processing unit, and that the cache memory unit also another register with the relevant number of bit positions for storing a Address, the indications and the number of rows of level signals, the relevant Storage takes place in response to a sequence of the specific types of commands. 68. Cache memory system according to claim 60, characterized in that the control device controls the 03002A / OÖ83 COPY has the same circuit with the two rows of input terminals and an output terminal and that the command buffer standby control means individually with each of the command buffers and the comparator circuit is connected and by the output comparator signal in such a way is controllable that an output signal can be generated in the event that the signal from the relevant other bit position of one of the memory locations of the relevant one buffer is present. 69. The cache memory system of claim 68, characterized in that a number of the pair of the first Series of input connections for receiving the memory identification signal. 70. Cache memory system according to claim 69 »characterized in that that the control device has a linking device associated with each of the Command buffer is connected and the on the occurrence of the memory identification signal out to Generation of the first write address signal is effective. 71. Cache memory system according to claim 70, characterized in that that a logic device for receiving control signals from the main memory is provided and that the control device has a circuit arrangement for receiving certain Contains control signals. 72. Cache memory system according to claim 68, characterized in that that at least one of the data input connections of the respective command buffer Leads voltage signal, which is characteristic for a binary signal 1 that each instruction buffer has a 080024/0883 COPY Having a plurality of SchrelbadressenanschlUssen, which are connected to the control device, and that the relevant further bit position of the respective memory location, which is addressed by the signals that are output to the plurality of write address connections, can be switched from binary state 0 to binary state 1 in this case that the instruction word in question is written into other bit positions of the plurality of bit positions of the memory location of an instruction buffer referred · 73. Cache memory system according to claim 72, characterized in that each instruction buffer has a plurality of output data connections that at least one of the data output connections is connected to the control device in accordance with the other bit position is that a plurality of read address connections are provided, which with specific bit positions of the command address register are connected, and that the further data output connection a binary signal 1 is applied to the relevant connections the control device is able to deliver in the event that a command word has been written into the memory location. ben, which is designated by the address bits which are contained in the specific bit positions, which are delivered to the plurality of read address connections. 030024/0883