DE2949571C2 - - Google Patents

Info

Publication number
DE2949571C2
DE2949571C2 DE19792949571 DE2949571A DE2949571C2 DE 2949571 C2 DE2949571 C2 DE 2949571C2 DE 19792949571 DE19792949571 DE 19792949571 DE 2949571 A DE2949571 A DE 2949571A DE 2949571 C2 DE2949571 C2 DE 2949571C2
Authority
DE
Germany
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19792949571
Other languages
German (de)
Other versions
DE2949571A1 (de
Inventor
Marion G. Phoenix Ariz. Us Porter
Robert W. Glendale Ariz. Us Norman Jun.
William A. Phoenix Ariz. Us Shelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/968,521 external-priority patent/US4208716A/en
Priority claimed from US05/968,312 external-priority patent/US4245304A/en
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Publication of DE2949571A1 publication Critical patent/DE2949571A1/de
Application granted granted Critical
Publication of DE2949571C2 publication Critical patent/DE2949571C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
DE19792949571 1978-12-11 1979-12-10 Cachespeichereinheit fuer die verwendung in verbindung mit einer datenverarbeitungseinheit Granted DE2949571A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/968,521 US4208716A (en) 1978-12-11 1978-12-11 Cache arrangement for performing simultaneous read/write operations
US05/968,312 US4245304A (en) 1978-12-11 1978-12-11 Cache arrangement utilizing a split cycle mode of operation

Publications (2)

Publication Number Publication Date
DE2949571A1 DE2949571A1 (de) 1980-06-19
DE2949571C2 true DE2949571C2 (el) 1988-06-30

Family

ID=27130509

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792949571 Granted DE2949571A1 (de) 1978-12-11 1979-12-10 Cachespeichereinheit fuer die verwendung in verbindung mit einer datenverarbeitungseinheit

Country Status (4)

Country Link
CA (1) CA1141040A (el)
DE (1) DE2949571A1 (el)
FR (1) FR2448189B1 (el)
GB (2) GB2037039B (el)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2474201B1 (fr) * 1980-01-22 1986-05-16 Bull Sa Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
SE445270B (sv) * 1981-01-07 1986-06-09 Wang Laboratories Dator med ett fickminne, vars arbetscykel er uppdelad i tva delcykler
DE3537115A1 (de) * 1985-10-18 1987-05-27 Standard Elektrik Lorenz Ag Verfahren zum betreiben einer einrichtung mit zwei voneinander unabhaengigen befehlseingabestellen und nach diesem verfahren arbeitende einrichtung
JPH07122868B2 (ja) * 1988-11-29 1995-12-25 日本電気株式会社 情報処理装置
US5058116A (en) * 1989-09-19 1991-10-15 International Business Machines Corporation Pipelined error checking and correction for cache memories

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3670309A (en) * 1969-12-23 1972-06-13 Ibm Storage control system
FR129151A (el) * 1974-02-09
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
US4070706A (en) 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system

Also Published As

Publication number Publication date
FR2448189B1 (fr) 1988-10-21
GB2037039A (en) 1980-07-02
GB2114783A (en) 1983-08-24
GB2114783B (en) 1984-01-11
DE2949571A1 (de) 1980-06-19
CA1141040A (en) 1983-02-08
FR2448189A1 (fr) 1980-08-29
GB2037039B (en) 1983-08-17

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Legal Events

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8110 Request for examination paragraph 44
8172 Supplementary division/partition in:

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D2 Grant after examination
8327 Change in the person/name/address of the patent owner

Owner name: HONEYWELL BULL INC., MINNEAPOLIS, MINN., US

8328 Change in the person/name/address of the agent

Free format text: BARDEHLE, H., DIPL.-ING. DOST, W., DIPL.-CHEM. DR.RER.NAT. ALTENBURG, U., DIPL.-PHYS. HOFFMANN, W.,DIPL.-PHYS. WALLINGER, M., DIPL.-ING. DR.-ING., PAT.-ANWAELTE PAGENBERG, J., DR.JUR. FROHWITTER, B., DIPL.-ING., RECHTSANWAELTE GEISSLER, B., DIPL.-PHYS.DR.-JUR., PAT.- U. RECHTSANW. KROHER, J., DR. KOWAL-WOLK, T., DR.-JUR., RECHTSANWAELTE, 8000 MUENCHEN

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee