DE2949198A1 - Integrated MOS circuit prodn. by silicon gate technology - with self-aligning overlapping source-drain contact using silicon nitride masking - Google Patents

Abstract

Prodn. of integrated MOS circuits is carried out by Si-gate technology, with self-aligning, overlapping source/drain contacts, using Si3N4 masking. Before prodn. of the source/drain zones by ion implantation, the gate oxide is removed in the region of the free substrate surface and oxidn. is carried out below 100 deg.C in a humid atmos., so that oxide films of different thickness form on the doped poly-Si regions and the weakly doped substrate. A Si3N4 film is applied for insulation between the poly-Si regions and the contact metal film. A great packing density is possible, since safety spacings are superfluous short circuits between the metallisation and adjacent doped regions in the Si substrate are avoided and over-large contact window for the source/drain contact can be opened over the gate oxide and the thick oxide zones.

Description

Method for manufacturing integrated MOS circuits

in silicon gate technology with self-aligned, overloading sources e iDrain contacts.

The present patent application relates to a method of manufacturing of integrated MOS circuits in silicon gate technology with self-designed, overlapping Sourc eiDrain contacts using silicon nitride masking.

In the manufacture of large-scale integrated semiconductor circuits one of the most important tasks in it, based on a minimal manageable Structure size as many components as possible (e.g. transistors) or functional units to accommodate per unit area. The inactive areas are particularly annoying the circuit, that is, those areas. that are not directly related to the circuit function contribute. This includes the unusable areas on the periphery of contact holes. These inactive areas are caused by so-called safety distances. To the Production of For MOS components, poly-silicon technology is preferred today used. With this technology, the gate electrodes of field effect transistors are used as well as conductor tracks for connecting such electrodes made of polysilicon. the There are significant advantages of this technology over a technology in which These electrodes and conductor tracks are made of aluminum, in that the interfering Gate-source and gate-drain overlap capacitances are kept very small can and that in the form of polysilicon an additional "conductor track" level is available.

With the n-channel and also with the p-channel silicon or

Double silicon gate technology must have contact holes in SiO2 layers both on n + - or p + -doped, monocrystalline, as well as on n + - or p + -doped, polycrystalline silicon areas are generated. It must be prevented that a contact hole with part of its area over the area to be contacted stands over, otherwise there would be the risk that the over the contact hole to be attached metallic conductor a short circuit to an adjacent p- resp. caused n-doped area of the single-crystal silicon base body. In the event of there is also a protrusion of the contact hole over a polysilicon structure the risk of undercutting the Si02 under the polysilicon structure an overhang of the polysilicon structure is generated, which leads to an interruption the overlying conductor path can lead.

To ensure that contact holes protrude over the areas to be contacted to prevent so-called safety clearances between the edges of the contact hole on the one hand and the edges of the doped silicon regions on the other hand will. These safety distances are necessary because the distance between two Structure edges from two different structure levels are not as precise as desired, but only with a certain tolerance, which is the current state of the art the technology is about + 2 / um, can be complied with.

In the literature one can find various suggestions for the described To make safety clearances on the periphery of contact holes superfluous.

In the DT-OS 27 23 374 a method is described in which with The help of nitride layers using their oxidation-inhibiting and etching-stop effect Contact holes are permitted, the base area of which extends over the polysilicon areas to be contacted protrudes. However, this method requires an additional contact hole mask; at the periphery of the contact holes between the monocrystalline n + - or p + -doped Areas and the metallic interconnects must still have safety clearances are provided and the contact hole slopes are very steep or even overhanging.

According to another suggestion (V. L. Rideout, J. J.

Walker, A. Cramer: RA one-device memory cell using a single layer of polysilicon and a self-registering metal-to-polysilicon contact ", International Electron Devices Meeting, Technical Digest, Washington, USA, Dec.

1977, p. 258) the polysilicon layer is removed in the few places where contact holes are to be created, with a double layer of silicon dioxide and silicon nitride, while the remaining parts of the desired polysilicon structures masked with a silicon dioxide layer. The uncovered parts of the polysilicon layer are etched away. This proposal also has the disadvantages of the DT-OS 27 23 374 described procedure, with the difference that the embankments of the Polysilicon structures (and not the contact holes) overhanging could be.

Another method was reported in a report by W. G.

Oldham, M. Tormey: "Improved integrated circuit contact geometry using local oxidation ", Electrochemical Society Spring Meeting, Seattle, USA, May 1978, p. 690 proposed. Here the oxidation-inhibiting silicon nitride layer is after the etching of the polysilicon layer applied. This nitride layer is etched so that it only stops where contact holes are to arise.

The disadvantage of this method is that the slopes of the polysilicon structures can be overhanging and that in the case of contact holes that are wholly or partially open Gate areas are arranged, the safety distances described above to the Poly-silicon edges are required.

A procedure that determines the safety distances at the periphery of the Contact holes between monocrystalline n + -doped areas and metallic ones DT-OS 25 stipulates that it is permitted to reduce interconnects or make them superfluous 09 315 known. In this process, dopant is added after the contact etch (Phosphorus or arsenic) into the contact holes. This prevents protruding Contact holes create a short circuit from the monocrystalline n + regions to the neighboring ones p-doped areas. The safety clearances on the periphery of the contact holes to the polysilicon structures are still required in this process.

The object on which the present invention is based exists in the manufacture of MOS circuits using silicon gate technology, in which 1. the safety clearances mentioned are superfluous and therefore a high packing density of the circuits pro Area unit is possible, 2. the short circuits between the metallic interconnects to be applied over the contact hole and the Adjacent doped regions produced in the silicon substrate are avoided and 3. Both the oversized contact hole used for the source / drain contact can be opened via gate oxide areas as well as thick oxide areas.

This task is carried out by a method of the type mentioned at the beginning solved in that according to the invention before the generation of the source-drain zones by Ion implantation removes the gate oxide in the area of the free substrate surface and an oxidation process at temperatures below 1000 ° C in a humid atmosphere is carried out, whereby on the doped polysilicon areas and on form oxide layers of different thicknesses on the weakly doped substrate, and that for insulation between the polysilicon areas and the contact metal layer a silicon nitride layer is applied.

In a further development of the inventive concept it is provided that Carry out oxidation at 700 to 10000C and set in relation to the time so that that on the doped polysilicon areas there is an oxide layer from 1000 to 3000 AO and on the weakly doped substrate an oxide layer of 200 to 500 AO trains. As a result of the very different oxidation times on, for. B.

Phosphorus-doped polysilicon and on z. B. the weakly p-doped Areas of the substrate at low oxidation temperatures can have this oxide layer can be used as an etch stop for contact hole etching.

It is within the scope of the invention, the thickness of the silicon nitride layer on 0.2 to 1.5 / µm, preferably to 0.6 / µm, and by thermal Decomposition of a gaseous compound containing silicon and nitrogen in the Low-pressure process or to produce by glow discharge.

Special refinements result from the sub-responses. So are according to an embodiment according to the teaching of the invention for production of integrated n-channel MOS circuits with silicon gate transistors with overlapping Source / drain contacts carried out the following process steps: a) Manufacture of structured SiO2 layers on a p-doped semiconductor substrate for separation the active transistor areas according to the so-called LOCOS or isoplanar method, b) Carrying out the gate oxidation by oxidizing the free p-substrate surfaces, c) Deposition of a full-area n + -doped polysilicon layer and structuring the polysilicon layer, d) removal of the gate oxide layer in the area of the free Substrate surface, e) all-over oxidation in a humid atmosphere at 850 to 9000C, f) Performing an ion implantation to produce monocrystalline n + -doped Source and drain regions in the p-doped substrate, g) implementation of a photo technique for structuring and Generation of contact holes (I) on the Poly-silicon areas, h) deposition of a full-area silicon nitride layer, i) Implementation of a photo technique for structuring and creating contact holes (II) for the formation of contacts between monocrystalline n + -doped areas and polysilicon areas or metallic interconnects, J) etching of the silicon nitride layer, k) etching of the silicon dioxide layer, 1) production of the metallic Leitbamnmuster.

In a manner analogous to that described for the silicon gate process, can also a double silicon gate process (= Si2 gate process) according to the invention Procedures are applied. In this case, between the procedural steps g) and h) a second polysilicon layer is deposited in a manner known per se, an ion implantation and oxidation for the load resistors contained in the circuit carried out and the second polysilicon layer doped and structured.

The inventive method results in contrast to that previously known process management the possibility of self-adjusting, overlapping Source / drain contacts both via gate oxide areas and via thick oxide areas to use. The packing density of static RAM (= random access memory) memory cells can be combined with the overlapping contacts produced by the invention and in addition with the use of polysilicon load resistors by a total of one factor 2 to 2.5 increase.

Further details and advantages of the invention will become apparent with reference to FIG Embodiments in the form of the application of the invention to n-channel MOS technology and FIGS. 1 to 18 are described in more detail. Show: Figures 1 to 7 the process control for n-channel silicon gate transistors with overlapping source / drain contact, Figures 8 and 9 illustrations on a scale of 2000: 1, from which the substantial space saving by the overlapping contacts produced according to the invention compared to the normal contacts can be seen, Figures 10 to 16 the process control for Poly-Si1 gate transistors and poly-Si2 load resistors with overlapping source / drain contacts, FIG. 17 shows the layout of a transistor with an overlapping source / drain contact and FIG. 18 shows the layout of the generated load resistance.

In all figures, the same reference numerals apply to the same parts.

The process sequence for a silicon gate process in n-channel MOS technology According to the teaching of the invention, the following is carried out, for example: a) Manufacture of structured SiO2 layers 1 (so-called field oxide areas approx. 0.7 / µm thick) on a p-doped (2 to 50 Ohm / cm) semiconductor substrate 2 <100> -oriented Silicon after applying a structured nitride layer and carrying out a Field implantation. The nitride layer is used to complete this so-called LOCOS process removed (the individual LOCOS process steps are not shown in the figures).

b) With reference to Figure 1 is now by oxidizing the free p-doped substrate surfaces 2, the gate oxide 3 is produced in a layer thickness of 40 nm.

c) FIG. 1 also shows the deposition of a 500 nm thick n -doped polysilicon layer 4 according to the CVD process (= Chemical Vapor Deposition) and their structure can be seen.

d) Removing the gate oxide layer 3 in the area of the free substrate surface (2) according to FIG. 2, e) carrying out an oxidation in a moist atmosphere at 805 to 9000C, whereby an oxide layer is formed on the doped polysilicon areas 4 5 from 1400 A0 and on the substrate surface (2) an oxide layer 7 from 300 to 400 AO (Figure 3), f) carrying out an arsenic ion implantation (see Arrows 8) in the transistor area for generating the single-crystal n + -doped source and drain zones 9 in the p-doped substrate 2 according to FIG. 4, g) implementation of a Photo technology for structuring and creating contact holes (I) on the polysilicon areas according to FIG. 5, h) deposition of a silicon nitride layer (10) over the entire area, i) Implementation of a photoresist technique for structuring and creating contact holes (II) for the formation of contacts between monocrystalline n + -doped areas 9 and poly-silicon areas 4 or

metallic interconnects (11), J) removing the silicon nitride layer in the area of the contact holes (II); the SiO2 layer 7 acts as an etch stop, k) Removal of the SiO2 layer 7 by reactive ion etching or wet chemical Ways. This creates the arrangement according to FIG. 6, and 1) performing a metallization and structuring of the contact metal layer 11 according to FIG. 7.

In Figures 8 and 9, in plan view and on a scale of 2000: 1, the conventional contacts regarding their space requirements with the self-adjusting, overlapping source-drain contacts. The hatched Areas 22 the size of the individual contact holes.

The packing density of static RAM lines can be determined with the in Figure 1 to 7 and 9 described overlapping contacts and additionally with the Increase the use of poly-silicon load resistors by a factor of 2 to 2.5, if According to the invention, the following process steps are used: a) Production of structured SiO2 layers 1 (so-called field oxide areas approx. 0.7 μm thick) on a p-doped (2 to 50 Ohm / cm) semiconductor substrate 2 made of <1OO> #oriented silicon Application of a structured nitride layer and implementation of a Field ion implantation. At the end of this so-called LOCOS process, the nitride layer is removed (The individual L0COS process steps are not shown in the figures).

b) With reference to Figure 10 is now by oxidizing the free p-doped substrate surfaces 2, the gate oxide 3 is produced in a layer thickness of 40 nm.

c) FIG. 10 also shows the deposition of a 500 nm thick n + -doped polysilicon layer 4, 14, 24 according to the CVD method (- Chemical Vapor deposition) and its structure can be seen. In the middle of the figure is the Development of the transistor structure (4), on the right side that of the load resistor (24) and on the left side that of the poly-silicon contact metal area (14) shown.

d) Removing the gate oxide layer 3 in the area of the free substrate surface (2) according to FIG. 11, e) carrying out an oxidation in a moist atmosphere at 850 to 9000C, whereby a Oxide layer 5, 15, 25 of 1400 A0 and an oxide layer on the substrate surface (2) 7 forms from 300 to 400 A0 (see FIG. 12), f) carrying out an arsenic ion implantation (see arrows 8) in the transistor area for generating the single-crystal n + -doped Source and drain zones 9 in p-doped substrate 2 according to FIG. 13, g) implementation a photo technique for structuring and creating contact holes (I) on the Poly-silicon areas 24 of the load resistance and the poly-silicon zium1 areas 14 according to FIG. 14.

h) With reference to FIG. 15, a poly-Si2 layer is now deposited 12, ion implantation of the load resistors (not shown), oxidation and patterning of the oxide 13 (load resistors) as well as doping and structuring of the poly-Si2 layer 12, i) deposition of a full-area silicon nitride layer (10), J) implementation a photoresist technique for structuring and generating contact holes (11) for Formation of contacts between monocrystalline n + -doped areas 9 and Poly-silicon areas 4, 14 or

metallic interconnects (11), k) removing the silicon nitride layer in the area of the contact holes (in); the SiO2 layer 7 acts as an etching stop (see Embodiment 1 method step J), 1) removal of the SiO2 layer 7 by reactive ion etching or by wet chemical means (see embodiment 1, step k) and m) Performing a metallization and structuring of the contact metal layer 11 according to FIG. 16.

From Figures 17 and 18 is the layout of a transistor with overlapping Source / drain contacts (Figure 17) and the layout of the load resistor (Figure 18) refer to.

The hatched areas 22 show the size of the contact holes at. In addition, the lines I and II limit the corresponding contact hole masks to see. Otherwise the same reference symbols apply as in the other figures.

5 claims 18 figures Blank page

Claims (5)

Patent applications. 1. Process for the production of integrated MOS shells in silicon gate technology, with self-aligned, overlapping source / drain contacts using Silicon nitride masking, d u r c h e k e n n n z e i c h n e t that before the generation of the source-drain zones by ion implantation, the gate oxide in the area the free substrate surface is removed and an oxidation process at temperatures is carried out below 10000C in a humid atmosphere, which affects the doped polysilicon areas and on the weakly doped substrate Form thick oxide layers, and that for insulation between the polysilicon areas and a silicon nitride layer is applied to the contact metal layer. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that the oxidation is carried out at 700 to 1000 0C and in relation to the time is set so that on the doped polysilicon areas an oxide layer of 1000 to 3000 AO and on the lightly doped substrate one Oxide layer from 200 to 500 AO forms. 3. The method according to claim 1 and 2, d a d u r c h g e k e n n z e i c h n e t that the silicon nitride layer has a thickness of 0.2-1.5 μm, preferably of 0.6 / µm, by thermal decomposition of a silicon and nitrogen-containing gaseous compound applied in the low pressure process or by glow discharge will. 4. Method of manufacturing n-channel MOS integrated circuits in silicon gate technology with silicon gate transistors with overlapping source / drain Contacts according to claim 1 to 3, g e k e n n z e i c h -n e t d u r c h the following process steps: a) Production of structured SiO2 layers on a p-doped semiconductor substrate for separating the active transistor areas according to the so-called LOCOS or isoplanar method, b) Carrying out the gate oxidation by oxidizing the free p-substrate surfaces, c) Deposition of a full-area n + -doped polysilicon layer and structuring the poly-silicon layer, d) removal of the gate oxide layer in the area of the free Substrate surface, e) all-over oxidation in a humid atmosphere at 850 to 9000C, f) Performing an ion implantation to produce monocrystalline n + -doped Source and drain regions in the p-doped substrate, g) implementation of a photo technique for structuring and creating contact holes (I) on the polysilicon areas, h) Deposition of a silicon nitride layer over the entire area, i) implementation of a Photo technology for structuring and creating contact holes (II) for training of contacts between monocrystalline n + -doped areas and polysilicon areas or metallic interconnects, j) etching of the silicon nitride layer, k) etching of the silicon dioxide layer, 1) production of the metallic interconnect pattern. 5. Method of manufacturing n-channel MOS integrated circuits with Si1 gate transistors and polysilicon2 load resistors with overlapping Source / drain contacts according to Claim 4, d u r c h g e k e n n -z e i c h n e t that in modification of the method for performing an Si2 gate process between the method steps g) and h) a second polysilicon layer in a manner known per se deposited, carried out an ion implantation and oxidation for the load resistors and the second poly-silicon layer is doped and structured.