DE2947502C2 - Circuit arrangement for the logical connection of functional groups - Google Patents
Circuit arrangement for the logical connection of functional groupsInfo
- Publication number
- DE2947502C2 DE2947502C2 DE19792947502 DE2947502A DE2947502C2 DE 2947502 C2 DE2947502 C2 DE 2947502C2 DE 19792947502 DE19792947502 DE 19792947502 DE 2947502 A DE2947502 A DE 2947502A DE 2947502 C2 DE2947502 C2 DE 2947502C2
- Authority
- DE
- Germany
- Prior art keywords
- output
- circuit
- logical
- circuit arrangement
- switched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00392—Modifications for increasing the reliability for protection by circuit redundancy
Description
nem zweistufigen Schalter 11, der über eine steuerbare Logik 21 vom Signalausgang L der vorgeschalteten Funktionsgruppe gesteuert wird, über einen nachfolgenden Serienwiderstand 12 auf den Ausgang der mit der Funküonsgruppe integrierten Schaltungsanordnung schaltbar sind. Dabei stellt die positive Versorgungsspannung die logische 1, die negative Versorgungsspanung die logische 0 und keine Versorgungsspannung oder Verbindung mit Bezugspotential, gemessen am .Schalterausgang 11, den Aus-Zustand oder einen Ausfall dar.nem two-stage switch 11, which is controlled via a controllable logic 21 from the signal output L of the upstream function group, can be switched via a subsequent series resistor 12 to the output of the circuit arrangement integrated with the function group. The positive supply voltage represents the logical 1, the negative supply voltage the logical 0 and no supply voltage or connection with reference potential, measured at switch output 11, the off state or a failure.
Die Schwelle für das Eingangssignal der nachfolgenden Stufe liegt bei Einteilung des Gesamthubs zwischen positiver und negativer Versorgungsspannung in 12/12 bei 7/12. Wie aus F i g. 2 ersichtlich ist, liegt der Bereich für die logische 1 zwischen 8/12 und 12/12, der für die logische 0 zwischen 0 und 6/12. Der Störabstand beträgtThe threshold for the input signal of the following When dividing the total stroke between positive and negative supply voltage, level is in 12/12 at 7/12. As shown in FIG. 2 is the area for the logical 1 between 8/12 and 12/12, that for the logical 0 between 0 and 6/12. The signal-to-noise ratio is
I ±1/12.I ± 1/12.
■§ F i g. 3 zeigt die iogische Verknüpfung von drei Funkle tionsgruppen 1,2,3. in denen der zweistufige Schäker 11 ■ § F i g. 3 shows the logical connection of three function groups 1,2,3. in which the two-stage teaser 11
II des schematischen Schaltbildes aus F i g. 1 aus 'zwei zu- 'φ sammengeschalteten Transistoren 14,15 beste!«, deren Tb gemeinsame Basis mit dem Ausgang eines Operationsg Verstärkers 13 verbunden ist Der Ausgang der jeweils '% einer Funktionsgruppe zugeordneten Schaltungsanordil nung wird aus zwei miteinander verbundenen Elektro- ;f den der parallel geschalteten Transistoren 14, 15 und S dem nachgeschalteten Serienwiderstand 12 gebildet ;t Die beiden anderen Elektroden der Transistoren 14 und :i 15 sind jeweils mit der symmetrischen Versorgungs- % spannung verbunden. L ist wieder der Signalausgang % der vorgeschalteten Funktionsgruppe. Aus Fig.3 ist i| ferner die Integration der erfindungsgemäßen Schal- :;; (ungsanordnung in die einzelnen Funktionsgruppen 1,2, ;. 3 ersichtlich. Die Verknüpfung der Funktionsgruppen '■'[. erfolgt außerhalb durch unmittelbare Verdrahtung.II of the schematic circuit diagram from FIG. 1 of φ sammengeschalteten transistors 'to-two' best 14,15 ', whose Tb is common base connected to the output of an amplifier 13 Operationsg The output of each'% a function group associated Schaltungsanordil voltage is of two interconnected electric;! F to the parallel-connected transistors 14, 15 and the downstream S series resistor 12 is formed; t the other two electrodes of transistors 14 and i 15 are each connected to the balanced supply voltage%. L is again the signal output % of the upstream function group. From Fig. 3 i | furthermore the integration of the scarf according to the invention: ;; (The arrangement of the individual function groups 1, 2,;. 3 can be seen. The function groups '■' [. are linked externally by direct wiring.
4040
5050
6060
6565
Claims (2)
logischen Verknüpfung von Funktion jgruppen.The invention relates to a circuit arrangement for operating modes:
logical connection of function jgroups.
und an deren Ausgängen ein der logischen Verknüpfungor different functional groups are connected, c) majority
and at their outputs a logical link
ergibt sich aus der Zusammenfassung aller Ausgangsan- 65 In Fig. I enthält die dargestellte Schallungsanordschlüsse der Eingangssignal-Grundkreise. Außerdem nung zur logischen Verknüpfung von Funktionsgruppen weist die bekannte Majoritätsentscheidungsschaltung zwei zu einem Bezugspotential symmetrische Vcrsoreine Reihe weiterer logischer Kreise auf, wodurch die gungsspannungen, die zweipolig abschaltbar und mit ei-to create an input connection. The output connection is a logical combination of three radio links of the logical majority decision circuit tion groups according to the invention,
results from the combination of all output connections. 65 In FIG. In addition, the well-known majority decision circuit has two Vcrsore, which are symmetrical with respect to a reference potential, and a series of further logic circuits, whereby the supply voltages, which can be switched off in two poles and with one
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19792947502 DE2947502C2 (en) | 1979-11-24 | 1979-11-24 | Circuit arrangement for the logical connection of functional groups |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19792947502 DE2947502C2 (en) | 1979-11-24 | 1979-11-24 | Circuit arrangement for the logical connection of functional groups |
Publications (2)
Publication Number | Publication Date |
---|---|
DE2947502A1 DE2947502A1 (en) | 1981-05-27 |
DE2947502C2 true DE2947502C2 (en) | 1985-05-02 |
Family
ID=6086856
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19792947502 Expired DE2947502C2 (en) | 1979-11-24 | 1979-11-24 | Circuit arrangement for the logical connection of functional groups |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE2947502C2 (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3792292A (en) * | 1972-06-16 | 1974-02-12 | Nat Semiconductor Corp | Three-state logic circuit |
US4091293A (en) * | 1975-12-30 | 1978-05-23 | Fujitsu Limited | Majority decision logic circuit |
-
1979
- 1979-11-24 DE DE19792947502 patent/DE2947502C2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2947502A1 (en) | 1981-05-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1191693B1 (en) | Circuit for monitoring the current through a power transistor | |
DE3215671C2 (en) | Programmable logic arrangement | |
DE1512403C3 (en) | Bistable circuit arrangement for complementary input signals applied in pairs | |
EP0048820A2 (en) | Binary MOS parallel comparators | |
DE1942420C3 (en) | Antivalence / equivalence circuit with field effect transistors | |
EP0589221B1 (en) | Semiconductor integrated circuit device | |
EP0252999B1 (en) | Clocked cmos circuit with at least one cmos switch | |
EP0048352B1 (en) | Binary mos-switched carry parallel adder | |
DE4308518A1 (en) | Combined bipolar transistor and MOSFET amplifier for ECL-CMOS level shifting circuit - uses two bipolar transistors with series MOSFETs between two opposing potentials providing amplifier inputs and outputs | |
DE2947502C2 (en) | Circuit arrangement for the logical connection of functional groups | |
DE2654575C2 (en) | Electronic touch switching device | |
EP1495542B1 (en) | Circuit arrangement and method for generating a dual-rail output signal | |
DE2156645A1 (en) | Counting device | |
DE2052519C3 (en) | Logical circuit | |
EP0218071B1 (en) | Adder cell for a carry ripple adder of the cmos technique | |
DE2824862C2 (en) | ||
DE941199C (en) | Relay chain circuit for counting devices with display of the absolute position, especially for axle counting devices in railway security | |
EP0822656B1 (en) | Circuit arrangement with an operational amplifier | |
DE1774301C3 (en) | Binary arithmetic element | |
EP0464239B1 (en) | CMOS amplifier circuit free of through current | |
DE1052719B (en) | Arrangement consisting of electronic switching means to create the exclusive or condition | |
DE2660842C2 (en) | Logical circuit arrangement designed as a comparator | |
DE2203526C2 (en) | Arrangement for evaluating signals of different priority | |
DE1463398C (en) | Arrangement for signal conversion and error monitoring for two-channel controls | |
WO2003005572A1 (en) | Method and device for switch-on current limiting in push-pull amplifying power stages |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: DEUTSCHE AEROSPACE AG, 80804 MUENCHEN, DE |
|
8339 | Ceased/non-payment of the annual fee |