DE2941702C3 - Synchronization facility - Google Patents

Description

The present invention relates to a synchronization device for a PCM system with at least one channel on which no signals are received at times, wherein each data signal packet contains a number of precursor pulses to derive a clock frequency therefrom derive.

When information is transmitted according to the principle of pulse code modulation (PCM), many the message systems on the receiving side with suitable Synchronization devices synchronized. In order to keep such synchronization facilities in To keep operation, periodic synchronization signals are continuously transmitted even if temporarily no information has to be conveyed. Such a synchronization device is known for example from CH-PS 6 07 475.

In the case of data and message transmission via satellite, it turns out to be due to the different Travel times of the electromagnetic waves for the various stations as necessary in the flow of information Insert pauses. The synchronization device known from CH-PS 07 475 is does not do justice to this requirement. In contrast, the invention shows a way of solving this problem.

According to the invention, this is achieved with a synchronization device as described in the claims is marked.

The invention is explained in more detail below with reference to drawings, for example. It shows

Fig. 1 shows a first embodiment of an inventive Synchronization facility,

2 shows a PCM system in which such a Synchronization device can be used,

3 shows an evaluation circuit of such a synchronization device,

4 shows a reset circuit of such a synchronization device,

F i g. 5 a timing diagram for various signals,

6 shows a second embodiment of an inventive Synchronization facility.

The synchronization device according to the invention according to FIG. 1 is used in a PCM system according to FIG. 2 which is first described below is used.

Via the antenna ANT of the system according to FIG. 2, the electromagnetic waves sent via satellite are received, which are processed in a known manner in the receiver station ES connected to it. The receiver station ES outputs the message signals received via satellite in the form of a digitized data signal Sd via a first output and a clock signal Sf of frequency / dab obtained from this data signal Sd via a second output.

The synchronization device SE is acted upon on the input side on the one hand with the data signal Sd and the clock signal St and on the other hand with a PCM clock 2i signal Sc of the local oscillator frequency ic of a first PCM station S1 and emits a synchronized PCM data signal Sds , which is sent to the first PCM station Sl is performed. The synchronization device SE is also supplied with the phase-locked jo subdivided PCM clock signals Sc 2 of frequency / L / 2 and Sc 4 of frequency / c / 16 as well as, for example, a multiplex signal Sp formed from signals from several voice channels,

A second PCM station S 2 is connected in a known manner to the first PCM station S1 via a transmission line L, which may be provided with some equalizers. For example, a PCM station can process 32 channels, 30 of which are voice channels and two are auxiliary channels. If the flow of messages received via satellite requires the transmission capacity of 16 channels, for example, a further 14 voice channels can also be transmitted with the multiplex signal Sp over the same transmission line L.

The synchronization device SE according to FIG. 1 has a data memory DS consisting of real memory cells SP1, SP2 ... SPS . The data inputs of these memory cells are connected to one another and are supplied with the digitized data signal Sd. The clock inputs Ai, A2 ... Ai ... AS of these memory cells are each connected to an output of a series / parallel switch SPU , which consists of a logic circuit EL that receives the three output signals x, y, ζ of a binary counter EC so that the following formula results for the cyclically controlled clock inputs Ai (J):

Ai (j) = \ for 7 = 4 * + 2y-t-z + l with Ai (J) = O for j / i

res GO are connected, and a second logic circuit AL exists. The AND gates Gl, G2 ... Gi ... GS each have two inputs, the first of which is connected to an output of one of the memory cells SPi, SP2 ... SPS and the second is each connected to an output of the logic circuit AL . The three output signals u, v, w of a binary counter AC are applied to this logic circuit AL , so that the second, cyclically controlled input signal S; (j) of the UN D gate Gi results in the following formula:

60

y, Z ^ = (OOO ₁ 001,010,011,100,101,110,111)

the binary counter FC being supplied with the clock signal Sf.

The outputs of the data memory DS are each connected to fe ^r> an input of a parallel / serial switch-PSU consisting of eight AND gates Gl, C2 ... G8 whose outputs with one input of an OR-To-Si (j ) " 1 for y = 4u + 2v + w + 1

(u. v, w) = (000,001,010,011,100,101,110,111)

the binary counter .AC being acted upon by the clock signal Sc 2 of the frequency fc / 2

The synchronization device SE according to FIG. 1 also has an evaluation circuit AW , the input side with the clock signals Sa Sc 2 and Sc 4 of the frequencies fc, fc / 2 and / c / 16 and optionally with the multiplex signal Sp and with the output signal Sg of the OR gate G. 0 is applied and at the output emits the synchronized PCM data signal Sds.

The synchronization device SE according to FIG. 1 also has a reset circuit AS connected on the output side to the binary counter EC , the first input of which is connected to the second input of the AND gate G5 and the second input of which has the clock signal Si applied to it.

The evaluation circuit AW according to FIG. 3 has a first shift register SPW operating as a series / parallel converter, the outputs of which are connected to the inputs of a second shift register PSIV operating as a parallel / series converter. The first shift register SPW has the output signal Sg of the OR gate GO (FIG. 1) applied to it via a signal input and the PCM clock signal Sc2 of frequency / c / 2 via a clock input. The second shift register PSW has the output signal Sb of a distribution circuit VS at its clock input and the clock signal Sc 4 of frequency / c / 16 operating as a transfer clock signal Ut at its control input. The second shift register PSW only responds to the rising edge of the clock signal Sc 4.

The distribution circuit VS (FIG. 3) has three AND gates G31, G32, G33, an inverter and an OR gate G34. A first input of the gates G 31 and G 32 and the input of the inverter J are supplied with the clock signal Sc4 of frequency / c / 16 and a first input of the gate G 33 is supplied with the multiplex signal Sp . The outputs of the gates G 33 and G 32 are combined via the OR gate G 34, which emits the synchronized PCM data signal Sds as an output signal. The second input of the gate G 32 has the output signal Se of the shift register PSW applied to it and the second input of the gate G 33 is connected to the output of the inverter /. The second input of gate G31 receives the PCM clock signal Seder frequency / c.

The reset circuit RS according to FIG. 4 emits a reset signal Sr via a monostable multivibrator MF ⁰ , to which the output signal of a latch LS is applied on the input side, the input side on the one hand with the output of an interference suppression circuit SU and on the other hand with the output of an UN D -Tore G 40 is connected.

The AND gate G40 has the output signal Sa of the logic circuit AL (FIG. 1) applied to it on the one hand and the output signal SAr 'of a delay circuit DL on the other hand. The inputs of the interference suppression circuit SU and the delay circuit DL are connected to the output of a clock detector <~ D , to which the clock signal St is fed on the input side.

The clock detector CD in the reset circuit RS according to FIG. 4 has a comparator KP , whose first input, connected to a reference potential via the parallel connection of a resistor R and a charging capacitor CL, has the clock signal St applied to it via the series connection of a first diode D 1 and a further capacitor C , the one with the capacitor C connected terminal of the diode D 1 is connected to the reference potential via a second diode D 2. The second input of the comparator KP is connected to a reference voltage source U _re r . The output of the comparator KP emits the signal S *.

The delay circuit DL (FIG. 4) has a monostable multivibrator MFl to which the signal Sk is applied via a clock input 42, G 43 is connected to the clock input of the flip-flop MF1, and the output of which emits the delayed signal SJt '.

The locking circuit LS (FIG. 4) has a first NOR gate G 44 connected on the output side to the monostable multivibrator MFO, the first input of which is connected to the output of a second NOR gate G 45 and the second input of which is connected to the output signal Sh of the interference suppression circuit SU is applied. The first input of the second NOR gate G 45 is connected to the output of the UN D gate G 40 and the second input is connected to the output of the first NOR gate G 44.

The interference suppression circuit SU (Fig. 4) has a monostable multivibrator MF2, the inverted output of which with the first input of a UN D gate G 46 and its clock input on the one hand with the output of a first inverter G 47 and on the other hand, possibly via the series connection of a an even number of further inverters G 48, G 49 is connected to the second input of the AND gate G46, the output of which emits the signal SA. The input of the first inverter G 47 has the output signal Si: of the clock detector CD applied to it.

The flip-flop MF2 of the interference suppression circuit SU has a time constant which is smaller than the time constant of the flip-flop MFI of the delay circuit DL. The interference suppression circuit SU can optionally be omitted by short-circuiting it

The synchronization device according to FIG. 1 to 4 now works as follows:

The data signal Sd and the clock signal St arrive at the same time or both are not present. The first pulses of the data signal Sd are in each case precursor pulses without information content, which it is assumed that they may be too jittery.

In Figure 5, the signals Sd, St. Sk. Sk '. Sa and Sr shown. The signal SJt 'at the output of the delay circuit DL (FIG. 4) is shorter than the output signal Sk of the clock detector CD by a predetermined time at which the Vc ^{r' runner pulses are present.} The reset circuit V? S thus emits a reset pulse Sr as soon as the signal Sa arrives from the logic circuit AL a first time per data packet, but only after some of the preceding pulses have been suppressed.

The data signal pulses Sd are written into the data memory DS cyclically with the frequency f = fd and also read out cyclically but with the frequency f2 = fc / 2 from the data memory DS , the frequency difference Δί = / "2 - f \ relative is small.

With the reset pulse Sr (Fig. 1), the logic circuit EL is reset when writing into the memory cell SP1, so that the information that was written into the memory cell SP1 at this moment is read out four clock pulses later when <4A = 0.

If, for example, the frequency f \ is greater than the frequency / "2, the data signal pulses Sd are written in faster than they are read out and the interval between write and read pulses is smaller than when Af = Q.

If, however, the frequency / 1 is less than the frequency / 2, the data signal pulses Sd are written in more slowly than they are read out, and the interval between the write-in and read-out pulses increases.

Both are insignificant if the storage length is sufficiently large on both sides. A memory length of ± four memory cells can, for example, with a 1.024 MHz data frequency and a data packet length of 40 ms, ^{absorb a clock frequency difference of about 1 · 10 ~ 4} , because (40 ms) χ (ΙΟ- ⁴ ) = 4μ5. These 4μ5 correspond to four clock pulses at 1 MHz. In the case of data signals subject to jitter, more memory cells must be provided.

This method can be implemented at all because the data signals are interrupted by pauses while the duration of which the information overflow can be recorded.

The signal pulses Sg are written into the evaluation circuit AW (FIG. 3) with the frequency / 2 = / c / 2 and read out with the frequency Zc = 2 · / 2. The shift registers SPlV and PSlV of the evaluation switch

<5 device A IV each have eight memory cells for storing 8-bit words. The 8-bit words are transferred in parallel to the second shift register PSW (FIG. 3) by means of the selection clock signal Sc4 of the frequency fc / 16.

5 »At the output of the distribution circuit VS appear alternately, controlled by the selection clock signal Sc 4, an 8-bit word from the second memory PSlV and an 8-bit word from the Multipiex-Siguai Sp. The output signal Sds of the evaluation circuit AW a real synchronized PCM data signal provided that the multiplex signal Sp consists of conventional 8-bit PCM words

For applications in which an interleaving of the data signal Sd with another multi

If the plex signal Sp is not desired, the distribution circuit VS of the evaluation circuit AW (FIG. 3) can be omitted by connecting the clock input of the second shift register PSIV (FIG. 3) directly to the clock signal Seder clock frequency / c and the input for the transfer clock.

»5 signal Ut is applied directly to the subdivided clock signal Sc 4 of frequency fc / 16.

The synchronization device SE according to Fig. 1 can generally with a data memory DS with i,

Memory cells SPi, SP2 ... SPn be constructed. The counters AC and £ C (Fig. 1) must be designed as n-to-1 counters (mod. N) and the logic circuits AL and EL as cyclic 1-out-of-n decoders; there must also be η AND gates G 1, G 2 ... Cn and the OR gate GO must have η inputs; the feedback signal Sa must be the ((n: 2) + 1) -th output signal of the logic circuit AL . A preferred synchronization device could be implemented with λ = 24 memory cells, for example.

The synchronization device according to FIG. 6 has a main memory HS connected to a counter CT with eight memory cells, each of which is connected on the input side to an output of a first shift register SPR operating as a series / parallel converter and on the output side to an input of a second shift register PSR operating as a parallel / series converter are.

This synchronization device also has a further reset circuit RS according to FIG. 4 and a further distribution circuit VS according to FIG. 3 as well as a logic circuit AL and a binary counter ACT , which are connected to the corresponding circuits according to FIG. 1 can be identical. Here, the input side fc with the clock signal Sc 2, the frequency / 2 is acted upon binary counter ACT are three output signals r, s, t on, which are supplied to one input of the logic circuit AL so that the following for the feedback signal 5a (j) of said logic circuit AL Formula gives:

Sa (j) = \ füry = 4 / - + 2s + f + l with Sa (J) = O for j / a (r, s, t) = (000,001,010,011,100,101,110,111)

On the input side, the reset circuit RS has the output signal Sa = Sa (j) from the logic circuit AL applied to it and the clock signal St obtained from the data signal Sd . The output signal Sr of the reset circuit is fed to the reset input of the 8-to-1 (mod. 8 counting) counter CT , to which the clock signal 5 / is also applied on the input side.

The first shift register SPR (FIG. 6) has the data signal Sd applied to it on the input side and the clock signal St obtained from this data signal Sd on the other hand.

The distributor circuit VS (FIG. 6) emitting the synchronized PCM data signal Sds is input on the one hand with the output signal Se of the second shift register PSR, on the other hand with the PCM clock signal Sc and also with the subdivided PCM clock signal Sc 4 the frequency ft / 16 is applied. Another output of the distribution circuit VS which emits a signal Sb is connected to the clock input of the second shift register PSi? connected, the input of which is applied to the subdivided PCM clock signal Sc 4 for a transfer clock signal Ut

The synchronization device according to FIG. 6 now works as follows:

The data signal Sd and the clock signal St arrive at the same time or both are not present. The first pulses of the data signal Sd are in each case precursor pulses without information content, of which it is assumed that they can be too jittery.

In Figure 5 the signals Sd, St, Sk, Sk 'are, Sa, and Sr shown The signal Sk' at the output of the delay circuit DL (Figure 4) by a predetermined Zeil, wherein the precursor pulses are present, shorter than the Output signal Sk of the clock detector CD.

The reset circuit /? S (FIG. 6) thus emits a reset pulse Sr as soon as the signal Sa arrives from the logic circuit AL a first time per data packet, but only after some of the preceding pulses have been suppressed.

The data signal pulses Sd are written in the series / parallel converter SPR with the frequency f \ - fd and with a frequency f2 = f \: 8 or f2 = f \: n, if there are η memory cells, in the main memory WS transfer. The data signal pulses are then transmitted with the transfer clock signal Ut from the main memory HS to the parallel / series converter PSR , the relationship that the frequency ft / 16 of the transfer clock signal Ut is approximately equal to '/ β the frequency id of the clock signal St.

After the transfer, the signals are read out with the frequency Ic and, if necessary, interleaved with the multiplex signal Sp.

This synchronization device according to FIG. 6 is required for a relatively small number of Memory cells less expensive than the synchronization device according to FIG. 1.

For applications in which interleaving the data signal Sd with another multiplex signal Sp is not desired, the distribution circuit VS of the synchronization device SE (Fig. 6) can be omitted by connecting the clock input of the second shift register PSR directly to the clock signal Sc of the Clock frequency / bund the input for the transfer clock signal Ut is applied directly to the subdivided clock signal Sc 4 of frequency fc / 16.

The synchronization device SE according to FIG. 6 can generally be constructed with a main memory DS with η memory cells SP 1, SP2 ... SPn . The counters ACT and ECT (FIG. 6) can be designed as 24-to-1 counters (mod. 24) and the logic circuit AL as a cyclic 1-out-of-24 decoder; a signal ScJt of frequency fc / 48 must be selected as the transfer clock signal Ut; the feedback signal Sa must be the ((n + 2) + 1) -th output signal of the logic circuit AL . A preferred synchronization device could be implemented in this way with / i = 24 memory cells.

The examples given in the present description are not related to the specific realizations according to the F i g. 1 to 6 tied.

In particular, the F g in i. 1 shown data memory DS be identical to that in F i g. 6 main memory HS shown.

Furthermore, the monostable multivibrator MFQ in the reset circuit RS (FIG. 4) can be omitted if the binary counter EC shown in FIG. 1 operates with edge triggering

In addition, this monostable multivibrator can also AiFO be a pulse generator working as a differentiator.

In addition, the monostable flip-flops AiFl and MF2 shown in FIG. 4 can also be pulse counters.

Furthermore, the tapping of the signal Sa from the logic circuit AL (FIGS. 1 and 5) does not necessarily have to be symmetrical.

Next is the number π of those in FIG. 6 generally divisible by eight, so that the output pulse sequence Se consists of packets of eight pulses each. Finally, the following applies between the frequency of the selection signal Sc 4 and the frequency of the

Transfer clock signal t / f the relationship

((se 4) = k · f (Ut), where is not an integer.

For this purpose 4 sheets of drawings

Claims (6)

Patent claims: 1. Synchronization device for a PCM system with at least one channel in which no signals arrive at times, each data signal packet containing a number of precursor pulses in order to derive the clock frequency, characterized in that the data signals (Sd) with the PCM clock frequency (fc) of the clock signals (transmitter PCM system to synchronize, a main memory (DS) is available in which the data signals (Sd) are written cyclically with the data signal frequency ( fd) and cyclically with a first with the PCM clock frequency ( fc) phase-locked clock signal (Sc 2) are read out, furthermore that the cyclically read out data signals (Sg) are written into a first shift register (SPW) operating as a series / parallel converter and with the first with the PCM clock frequency (fc) phase-locked clock signal ( Sc 2) are read out and written into a second shift register (PSW) operating as a parallel / series converter, from which the information (Se) is transmitted with the PCM clock frequencies z itself (fc) is read out, and that a reset circuit (RS) is present, which emits a reset pulse (Sr) with which the first of the series of input pulses written cyclically into the data memory (DS) by a few clocks (n: 2) is phase-shifted by the initial pulse of the series of output pulses read out cyclically from the data memory (DS). 2. Synchronization device for a PCM system with at least one channel in which no signals arrive at times, each data signal packet containing a number of precursor pulses in order to derive the clock frequency, characterized in that the data signals (Sd) with the PCM clock frequency (fc) of said clock signals (Sc) to synchronize the PCM-conditioning, to the main memory (HS) is present, the data signals (SD) groups of the data signals (Sd) is divided into the a from the clock signal (St) Write clock signal (St : n,) are written in and transferred with a transfer clock signal (Ut ) that is phase- locked at the PCM clock frequency (fc) into a shift register (PSR) operating as a parallel / series converter, from which the information (Se) is transmitted to the PCM Clock frequency itself (fc) is read out, and that a reset circuit (RS) ™ is available which emits a reset pulse (Sr) with which the first write clock (St: n) is phase-shifted with respect to the transfer clock (Ut) by a fraction (1: 2) of the repetition period of this transfer clock signal (Ut). 3. Synchronization device according to claim 1 or 2, characterized in that a by a divided from the PCM clock signal in the frequency selection signal (Sc 4) controlled distribution ω circuit (VS) is present, with the help of which a bit word from the with the PCM clock frequency itself read out information signals (Se, / and a bit word from an external multiplex signal (Sp) are alternately interleaved. ⁶ ^ 4. Synchronization device according to one of claims 1 to 3, characterized in that in the reset circuit (RS) a clock detector (X a delay circuit (DL), a locking circuit (LSX an AND gate (G 40) and a pulse generator (MFQ ) are present, the clock detector (CD) emitting a continuous signal (Sk ) at its output as long as clock signals (St) obtained from the data signals (Sd ) arrive at its input, and also that the starting edge of the output signal (SJt ^ of the delay circuit (DL ) is delayed by a predetermined time compared to the starting edge of the output signal (Sk) of the clock detector (CD) , the delayed output signal (Sk ') and a feedback signal (Sa ^ derived from the PCM clock signal in a phase- locked manner via an AND gate (G 40)) are summarized, and that the locking circuit (LS) is connected via a first input to the output of the AND gate (G 40) and a second input to the output of the clock detector (CD) , u m to let the feedback designa] (Sa) take effect only once per data packet. 5. Synchronization device according to claim 4, characterized in that the reset signal (Sr) is fed from the output of the locking circuit (LS) via a pulse generator (MFO) . 6. Synchronization device according to claim 4 or 5, characterized in that the second input of the locking circuit (LS) exercises an interference suppression circuit (SU) is connected to the output of the clock detector (CD) , the interference suppression circuit (SU) by means of a delay stage ( MF2) and an AND gate (G 46) bridged short clock pulse dips.