DE2938713A1 - DATA PROCESSING CIRCUIT - Google Patents

Description

5938713

Dipl.-Phys. OE Weber / ft d-8 Munich 7i

Patent attorney Hofbrunnstrasse 47

Telephone: (089) 7915050

Telegram: monopoly weavers some

h 1213

IiÜ'lOHULA. IHC.
East Algonquin Hoad
ochaumburg, 111.60196

Ii .Jb.A.

Data processing circuit

The invention "relates generally to and relates to data processors refers in particular to data processors that can be produced on a single plate or chip of an integrated circuit and for processing signals in real time are suitable.

A problem arises with known iJcha It arrangements of this type when interruptions are not recognized immediately. This problem is essentially that the time at which the interruption has occurred can be critical with regard to the action to be taken by the processor. Since the Detection of the interruption is delayed or postponed and since the external event occurred in real time, the data processor has no record of the time, too which the interruption occurred.

The invention is based on the object of a data processor or to create a data processing arrangement which, with regard to applications in real-time operation, provides information can take into account the time at which an external event or several external events to later Consideration occurred.

The patent application in particular serves to solve this task laid down characteristics.

According to the invention, the essential advantage can be achieved that several external events are recognized for later consideration and can be stored without interrupting the execution of instructions within the data processing arrangement is to be feared.

According to a particularly preferred embodiment of the invention it is provided that a first register is provided, which is used to store the most significant half of a double word operand and half with the highest

0300U / 0880

AH

btellewert of a double value result from a multiply instruction record that there is still a second Hegister, which is used to half with the least Place of a double word overand and the part with record the least significant value of a memory address that a timing register is also provided, which is able to do so at a continuous rate by 1 to be incremented, the timing register serving to provide a timing reference signal that continues to be at least a catch register is available, which is able to be loaded directly from the timing register, when a signal transition in an input signal of the data processing circuit occurs that a comparison register is further provided to store a predetermined time and to be continuously compared for equality with the timing register to produce a signal, if there is an equality, there is still a control shift register for serial shifting of data at a corresponding control is available, whereby the control shift register, which is also referred to as an instruction shift register, is capable of shifting data when the timing register corresponds to a value stored in the compare register that is also an input / output control register is present, which is able to carry out control of predetermined interruptions, and Finally, there is an input / output status register to indicate the causes of interrupts.

Another preferred embodiment of the subject matter of the invention provides that a command decoding device is provided for decoding commands for the data processing arrangement is that there is also an instruction hegister with the instruction decoder is connected to receive instructions to be decoded by the instruction decoder, that further

0300U / 0880

A range of kegisters is provided to hold changeable data to save the range of .registers with the N-bit data rail is connected that further an arithmetic and logic unit with the N-bit data rail and with the instruction decoder is connected that the arithmetic and logic unit is able to perform operations in the range of Hegister stored data to carry out that further a program counter is provided to the sequence of instructions control that the program counter is connected to the address rail, further characterized in that a timing register which is able to be continuously incremented by 1 that the timing register is connected to the N-bit data rail that at least one capture register is available, which is able to to be loaded from the timing register that the at least one available capture register with the N-bit data rail is connected, connected to the timing register and connected to an input terminal of the data processor device is to enable at least the capture register to be loaded from the timing register as soon as a signal transition occurs occurs at the input terminal that a comparison register is still connected to the N-bit data rail, that the Compare register is able to continuously compare for equality with the timing register to provide a signal when there is an equality that the control shift register or command shift register is connected to the N-bit data rail and to an output terminal of the data processing arrangement and that the Control shift register or command shift register a temporary one Storage of data and a shift of data from the output terminal to a specified control signal or a given command possible.

The invention is explained below, for example, with reference to the drawing described; in this show:

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i'ig. 1 is a block diagram of a microprocessor, which according to a preferred embodiment of the invention is,

i'ig. 2 is a timing diagram showing the relationship between an external clock and various internal Clocks is illustrated,

if'ig. 3-M- t> is JU a logic diagram of a particularly preferred one üusführurigsform des in the i'ig. 1 shown! Microprocessor ,

i'ig. 4- a logic / circuit diagram showing a circuit is shown, which is used to detect the occurrence of a trigger signal and also contains an ocircuit, which serves to selectively interrupt the in response to the occurrence of the trigger signal ! Microprocessor, and

i'ig. 5 is a logic / bchaltungs diagram of part of the timing control means and a portion of the fcjpeichereinrichtung according to the preferred Ausführungsf ο Z ¹ Di of the invention.

In the i'ig. 1 are an eight bit digital data processor and its oteuerlogik, as well as an arithmetic logic unit, an input / output unit and memory are shown. Architecture and the instruction set of the digital data processor 10 are universally oriented, but for control and regulation purposes particularly suitable. The input / output functions of the digital dot processor 10 are controlled via a group of special registers which are addressed in the same way as other processor registers. Therefore it is possible to enter / Output logic for a specific control application or cone application or to program for more general applications.

Ö300 U / 0880

The processor 10 can address up to 81 ^ 2 ten-bit words of memory door commands and data. Normally, this memory is designed as a .b'est memory (ϊίϋίΊ), from which only data can be read, with changeable data being stored in the register area 48. The register area 48 contains a plurality of eight-bit data storage registers arranged in an area for handling changeable data. Four special registers 64, 1/1, 73 and 74 are arranged in the register area 48, together with seven input / output registers 53, 54, 55, 56, 58, 7 and 62. The remaining data storage registers are preferably in the i'orm of memories with static access (IiAiI). Additional data memories which are arranged externally to the microprocessor 10 are accessible via the memory rail l ^v iB. The bpeicherschiene rg has ten working in two .Richtungen lines which can used to v / ground, a part to transmit a! Memory address from the data processor 10 to an external öpeicher, as will be explained in more detail below. The memory rail 1ΊΒ can be used to transfer commands from an external memory to the data processor 10, and it can also be used to transfer data between the data processor 10 and the external memory. The storage rail ΓΊΒ can also be connected to a peripheral circuit to serve as a general input / output rail.

The command decoding and command control device 11 decodes Commands and controls the operation of the data processor 10 and is therefore with many circuit parts within the Data processor 10 connected. Addressed commands are first locked in the command register 24 after they have been removed from the memory have been fetched to be decoded by the decoding and control circuit 11. As shown, line 22 is from the command decoding and control block 11 to the command register and is operational during an interruption, like it

030014/0880

is explained in more detail below. The command decoding and The control block 11 is connected to the arithmetic and logic unit 13 via a plurality of lines 12. An exit line 14 of the command decoding and control block 11 is with a Selection circuit 16 connected. The line 14's action is to put an address on the output of the selection circuit 16 when an interrupt occurs. A multiplier / Divide counter 17 is connected to the command decoding and control block 11 via a line 18 and is used to Multiple passes through the arithmetic and logic unit 13 so that multiply and divide operations are performed can be. The line 19 connects the cycle counter 21 to the command decoding and control block 11. The cycle counter 21 is a lock which is used to separate a first cycle from a second cycle in the two cycle instruction to distinguish. Although in the i'ig. 1 generally only one line is shown between different ßlöcken, it should be noted that in a corresponding device-technical embodiment multiple lines may be present in such connections.

The command register 24 has an output line 23 which is connected to the command decoding and control block 11 with the selection circuit 16, with the temporary storage register 78 and with the program counter register 76 is connected. The bits stored in the command register 24 can be an operation code to be decoded in the instruction decoding and control block 11. In an alternative way, the bits, which are locked in the command register 24 represent the address of a data register in the register area 48, the selection circuit 16 controls this address in the register area 48. For certain two-cycle commands, one of the im Command register 24 latched bits must be combined with those ten bits which are used during the second cycle can be read to form an eleven-bit input signal, which

Ö300U / 08ÖO

Λ *

either the program counter register 76 or the temporary one Storage register 78 is supplied. A side lock or a flip-flop 28 is associated with the command decode and control block 11 connected via the line 26. A page stack 29 is connected to the side lock 28 so that when an interruption occurs, the page status in the page stack 29 can be stored, which was in the lock 28. The page flip-flop 28 is connected to a buffer 31, which has an output AD12 which carries the bit of the memory address with the highest priority. The output AÜ11 is over a buffer 32 and a line 27 with the instruction decoding and control block 11 connected. The output AD11 is controlled by an interrupt mask, which is transmitted via a line 41 and an interrupt latch / riaske 42 is supplied, and in connection with the output AD12 two widths of Foreground programs provided in memory to handle the interrupts. Furthermore, there are also two sides of Background programs contained in memory to perform those programmed operations that occur between the sub refractions occur. The page address bits AD11 and aD12 address one of four pages of 2048 words. AD11 and üD12 remain stable during an entire storage cycle.

An oscillator 37 has two external connections that are connected to are designated. These are connections for an oscillator crystal. A home resonance crystal that vibrates in the basic mode and cut in the shape AT can be between the two XTAL terminals be arranged to control the operation of the internal oscillator. If desired, an external oscillator to use, then a corresponding signal source can be used that delivers a square wave signal and that to a the XTAL connector is connected while the other connector remains open. The oscillator 37 is connected to a clock generator 36. The clock generator 36 supplies all internal clock signals for the data processor 10. The clock generator 36 also supplies a

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^0Ft 'GtNAL / mo.

Output signal, which is labeled CLK and which is buffered by a buffer 38. When the clock signal CLL output at a high level, it indicates that the bpeicherschiene mcs contains a "memory address. When the fact output signal CLK is at a low ± ^j egel, it indicates that the bpeicherschiene HSS contains data during a bpeicher-bchreibbef Ehls when the clock output CLK is deeply set, the processor can accommodate 10 data to the opeicherschiene IiB. During commands other than memory write commands, an external circuit can bring data to the memory rail Γιϋ when the 'fact output signal GLK is low. The clock generator 36 is connected to the Bei "ehls decoding and control block 11 via a line 33 in order to supply the generation of the various Bteuez output signals in a timely manner.

In the preferred embodiment of the counterpart of the invention, limitations with regard to the logic circuits of the circuit arrangement rule out the use of a read / write signal to indicate the data direction on the storage rail Iili during the second half of a hash cycle when CLK is low. Therefore, read / write buffers, which enable external storage of changeable data, and indeed as well as other peripheral units connected to the storage device Uli , may require the use of one of the address subits to indicate the data direction around the b to use memory write command.

The microprocessor or data processor 10 can have a plague memory 83, from which can only be read, as an internal memory on the plate, which is arranged within the dashed lines ·. ': . If the processor 10 has an internal storage memory 83, then an input signal is required at the terminal Eh, which is shown within the dashed line 3'- ", so that the processor 10 receives information as to whether a storage read command is on the internal iest-S'jeicher 83 or to an external storage device. A

0300 U / 0880 INSPECTED

2Λ

high rule at the entrance gill Eli during the data part of the clock cycle (i.e. the clock signal (JLJi is low) shows indicates that the address arrangement is external to the i-processor 10, and consequently the internal read-only memory 83 is ignored, so that data on the memory rail can be read without fail. When a low level at the input terminal Eh during the data part of the x'aiLtzyklub is available, the internal non-volatile memory 83 made to read regardless of the time at which a read store command is executed. The read memory command has a three-bit field which can be used to das li-iiegister 73 ^ u to increment or decrenient what is useful for an ochema when examining a table has proven. However, the logic is structured in such a way that if all three iiits are a logical one, the ii-register 73 is not incremented (or is incremented by HuIl) and that! weeds are read from the external storage rail ΓιΒ, instead of from the internal memory 83 · This results in a larger Flexibility in using the processor 10.

The storage rail Iiii is vex-buriden via a buffer 85 with the selection circuit 84. The selection circuit 84 selects either external data that arrive on the opeichez'schiene Γηί, or data from the read-only memory 83 that are to be brought to the line 86. The line 86 is connected to the flow register ^ 4, to the frogramia counter ^r / G and to the temporary register 78. The best memory 83 is typically a ten-bit memory with a storage capacity of 1K. in the present specification ¹ preferred embodiment of the subject invention is used to dex ßeschreibung often opeicherkapazität an abbreviation such as 1K, 2K, etc.. It should be apparent to those skilled in the art that 1K is an abbreviation for 1024 memory words, while 2K is an abbreviation for 2048 memory words, etc. It should be noted that if it is not desired , one ! '' est memory on the same plate of the integrated

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ORIGJNAL INSPECTED

Having circuit on which the processor 10 is formed, the components contained in the dashed lines 39 and 82 were omitted and the output of the buffer 85 directly would be connected to line 86. 'If the processor 10 has a i / estspoicher 83, the lasister area 48 may contain fifty-two have directly addressable eight-bit iiegisters. If the Processor 10 has no j'est memory * 83, then the kegister area 48 expanded to 127 directly addressable ACht bit hegisters while the same total area of the platelet wii'd retained.

An interruption / locking hash 42 is connected via line 41 to the command, decoding and control block 11 and to aD11 as output buffer $ cl . The interrupt / lock ilask 42 is a temporary buffer that is used exclusively for internal timing purposes and is set when an interrupt occurs. The interrupt / interlock hash 42 is reset when the reset interlock receives an input at the Kuckstellen terminal. Reset is an active, low signal, and this signal triggers a reset operation in processor 10 so that the signal must remain low for at least ten full clock cycles. The reset latch 43 provides an output on line 44 to reset the stack indicator 46 and cycle counter 21 and to clear the control register 47. The override bit in the interlocking 28 is also reset by the output signal from the back-up interlock 43, but this connection is in effect. 1 not shown in order to prevent the drawing from being overloaded. If the control register is cleared, all interruptions are switched off, and the output terminal ΗΪ3 is switched to an input mode, and the output signal labeled üüUT is still brought into a static flodus with an output signal zero. These functions are explained in more detail below. Another function that is carried out by the reset signal is to enter an operation code for a jump in

03001.W 0 8 8 0

ORIGINAL INSPECTED

put a subroutine (Jolt) in the command register 24, and to continue to put a zero vector address on address rail 79 so that the jump address is fetched can to execute the command Jüü. Then dex causes Command JiSH that the program counter 76 with the content of the “Location zero is loaded and an instruction to be executed is still fetched will.

The stack indicator 46 is connected to the selection circuit 16. The selection circuit 16 selects which of its four inputs is connected to the address input of the xiegister area 48. The selection circuit 16 receives three input signals from the citapelajizeige 46, seven input signals from the command register 24, seven input signals from the K-register 64 and a forced address, for interruption purposes, on the line 14 which corresponds to the command-iiekodier- and control block 11. The output from the selection circuit 16 is fed to the register area 48 and the register address decoder 4 ^. This register address decoder is used to set the addresses for the registers 4 /, 53-56, 58, 62, 64, 71 , '/ I and 74 v, \ x to decode. The register area 48 is connected to the data rails 51 and 52. The data rail 52 is an eight-bit rail. The data rail 5I is a three-bit rail and is used to expand the data rail 52 to form an eleven-bit data rail for part of the processor 10.

The registers in the area of the register 48 are logically divided into two Groups are subdivided by the addressing options of the instruction set, and certain registers have special ones functions. The first .register is designated as .register ± t1, and the other registers are numbered in ascending order. There is no register labeled WuIl. the .Registers in register area 48 are made directly via corresponding bits in the command word or indirectly via the k-iiegister 64

03001 A / 0880 ORIGINAL INSPECTED

addressed. A register address of zero determines indirect addressing because there is no Kegister WuIl and the contents of the K-register 64 are used to serve as a real register address. The registers 1 to 31 are designated as intermediate registers and are used for the intermediate storage of voxi intermediate results, while those registers that are identified with 32 and higher are to be regarded as auxiliary registers. In addition to the eight-bit registers, the register area 48 includes nine eleven-bit registers. Eight of the nine eleven-bit registers are used to serve as the program counter stack, and the ninth eleven-bit register acts as an M-register for a one-level stack for xtegisters 73 and 74. If an interrupt is triggered, the instruction decoding and control block 11 brings the register area address of the ninth eleven-bit register on the line 14, which is then selected by the selection circuit 16 to read the contents of the h register 73 and the i'iE register 74 - to be stored in the ninth eleven-bit register. The ir'rogrammzählerstapel serves to store the contents of the program counter 76, and zv / ar / 6 in such a manner that a bprungadresse is entered before the change of the program counter '. The b-stack indicator 46 is a urei-bit it register and is used to address the program counter stack so that the current program counter value can be safely stored in the addressed location if an interroutine or an interrupt occurs.

An instruction shift register ^ 3 is connected to the data rail 52 and to the output driver 59. The buffer output driver 59 supplies an output signal UUUT. The buffer output driver 59 can be programmed to operate as a clocked data output for serial bits or as a static output (DC) using the two control bits in the input / output control register 47 Data from the instruction shift register 53 This shift register 53 has a length of eight bits,

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2Γ

However, the transmitted data is always preceded by a ninth bit, which is to be referred to as the ocart bit and always has a logic level "1". The data which are entered into the command shift register 53 via the data rail 5 <^ are shifted and output after the start bit has been recognized, the bit with the least significant value being shifted first. As a result of the shift, the register 53 is deleted, so that logical output signals "0" are present, and the output signal oUlil ^{1 is} kept at a logic level of zero until the command shift register ¹ 53 is reloaded or its override mode is changed. The register 53 can operate in such a way that a shift occurs immediately and it can operate in such a way that a delayed shift is sensed. When the mode is selected in which a shift occurs immediately is carried out, the transmission of data begins on the output line oub'i ¹ , namely in the hashing cycle that follows the cycle in which a data byte is written into the shift register 53 or during the cycle that responds to a write command for the input / output control register 4 ^r / follows to select the modes with the immediate shift Thus, the time control mode or time delay mode enables a control byte or command byte to untex * P rogram control can be transferred to canoe. In each shift mode, the transmission begins with the start bit. All data transitions on the dex ¹ output line bOUT take place when the negative going Jj'laiike of the clock signal CLK. The shift speed 1 bit per machine cycle. In the static mode, no shift is carried out in register 53, and this register can then be used as a normal register. The instruction shift register 53 can be used in the manner

030 0 1 A / 0880

- ** - 2938715

that under program control via the data rail 52 in this Kegister is written in or read out. Writing in this register during the interval in which there is data transmits, Can lead to a disruption of this data. Since that Command shift register 53 is not activated by resetting or is triggered, a valid data byte should be stored in it before a particular shift mode is selected wii-d.

The input registers 5 and 55 are connected to the data rail 52 and to the clock generator 56. The input registers 5 ^ and 55 are loaded directly by the clock generator 56 when a signal transition (from low to high or from high to low) at the inputs It ¹ J? 1 or K'1'2 occurs. An input ΚΪ1 controls the loading of the Jj'ang register 54- »while an input üV'd controls the loading of the if'ang register 55. Each secondary register thus holds the time, which is indicated by the timer 56, at which the last transition occurred on the corresponding real-time input line ΚΪ1 or ii'1'2. The signal transitions at the inputs Hl ¹ I or UT2 also generate interruptions to inform the program that an input has been made. These interruptions can be masked individually by the program via the control register 4-7. The. Capture registers 5 ^ and 55 can be read out by the program via the data rail 52 or data can also be stored in this way by the program, and none of these operations leads to the if'angfunkt ion, while storage is the last captured value destroyed. A third real-time input KT3 can be programmed in such a way that it works as an input or as an output, with the help of the two control bits in the input / output register A-7. In the input mode, the interruption can be blocked or activated, while in the output mode the output signal can be raised or lowered. in the

0300U / 0880

2?

Bit 3 of the input / output otatus register becomes the input mode 62 is set when a signal transition occurs at the Hi'3 terminal. An interrupt is generated if the interrupt has not been locked. In the input mode, the output buffer 60 is on one high impedance (off) held. In output mode Hi'3 becomes the output raised or lowered, depending on from bit 3 in control register 4-7

The timing register 56 is an eight-bit hegister which is incremented by one at a continuous rate by an input from the clock generator 36. It is possible to use a metal mask so that the speed at which the timing register 56 is incremented can be selected such that it can be set to 1 per machine cycle or to 1 per two machine cycles or also to 1 per four machine cycles. These possibilities are provided by the manufacturer, and a corresponding operating mode can be selected during the manufacture of the integrated circuit, which then cannot be changed by the program. In this way, the time control register 56 has a continuous reference to real time. An interrupt is generated as soon as the timing register 56 overflows. The interrupt can be selectively masked by the program. The timing register 56 is connected to the data rail 52 to .besen and storing, with the tfangregistern 54 and 551 ^m it the equality detector 57 and connected to the status register 62 to determine an overflow. The time control register 56 is connected in such a way that it can be written in or read out by program via the data rail 52 as well as with any input / output register. Reading from the register 56 has no effect on its counting sequence or on the timing, while the storage in the timing register 57 enters a new eight-bit value in the register, whereby the incrementing of the timing is blocked, but only during the immediately following Cycle.

03001 A / 0880

2 *

The compare register 58 is connected to the data rail 52 and to the equality detector 57. The compare register 58 is an eight-bit hegister in which a preselected future time can be stored. This stored time is continuously linked to the content of the timing register 56, and if the content in the timing register 56 is equal to the number stored in the compare register 58, a signal is generated which can cause an interruption which can be masked by the program, It is also possible for a start output signal SOUi ^{1 to} emanate from the command shift register 53. These two functions can be carried out simultaneously or separately, specifically under the control of corresponding bits in the input / output control register 47. It can be read from the comparison register 58 or stored in the comparison register at any time by program. The predetermined time, which is stored in the comparison register 58, is continuously compared with the contents of the timing register 56 by the equality detector 57. The equality detector 57 provides an output signal to the status register 62. The input / output control register 47 is connected to the data rail 52 connected and supplies an output signal to a buffer driver 59 and to an output driver 60. The control register 47 supplies, under program control, control of the shift register 53 'and the output driver 59 supplies program control for the operating mode for the input / output KT3 and selectively masks the various interruptions. The control register 47 is an eight-bit register and it can be read from this register or written into this register under program control via the data rail 52. The bit 7, which represents the bit with the highest priority value of the control register 7, is the bit which masks the output which is determined by the equality detector 57. Bit 6 masks the overflow of the timer of time control register 56, bit 5 masks a fiTI transition interruption, bit 4

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2838713

masks an iCi ^ hiding interruption, bit 3 masks its iii'3 interruption and, in conjunction with bit O, determines whether iti'j? raised or lowered when the assembly is in the dispensing mode. Bit 2 and bit 1 of the control register ¹ V / v / earth are used to control the "ehls shift register" 53 and the output driver 59. The control register 47 also receives an input signal from the reset 43, which is used to clear the control register 47 and to fill it with a logic signal "ü", whereby all interrupts are switched off, and IU'3 is placed in the input mode and oUbi 'in the static mode, with an output 0. The control register 47 also provides an output signal to the interruption priority and control circuit 61.

The interrupt priority and control circuit 61 generates the priority of the interrupts under the control of the Control register 47 and provides an output on address rail 79 · The interrupt priority and control circuit 61 also provides an output to the interrupt lock / haske 42 and is still connected to the status register 62.

The input / output status register 62 is an eight-bit register, can be read from and written into, under. program control, and this register is linked to the Üatenschiene 52 connected. The status register 62 is with the inputs 1ίΐ1, iiT2 and iiT3 > with the equality detector 57 and with the timing register 56 and receives input signals from there. The status register 62 shows the causes of interruptions and enables the three real-time input lines to be read out directly Ki'1, HT2 and KTjJ. The level at which Input HT1 occurs is indicated by bit 2 of the status register reflected when bit 2 is at a logic level "0", it indicates that the input signal at input ΗίΊ is low and when bit 2 is at a high logic level, this indicates that the input signal at input ii'i'i is high

0300U / 0880

is. Correspondingly, bit 1 of status register 62 reflects the input signal which occurs at input K'i'2, and bit O indicates the input signal at input KT3. Bits 3 to 7 are set, and if the input / output ochaltung of Jrrozessors 10 an interruption is detected. bit 3 is set by a transition at the input Kl'3, bit 4 is set by a transition at the input KT2, bit 5 is set by a Jbergang at the input RI ¹ I , bit 6 is set when the timing register has an overflow and bit 7 is set when the time comparison is indicated by the equality detector 57. When one of these bits 3 to 7 is a logic "1" and the corresponding bit ii: i Control register 4-7 is a logic "1", an interrupt occurs. The input K'i'3 can only generate an interrupt if it is in the input mode. It should be noted that the bits in status register 62 point to a logic " 1 "set zt are, if the specified state is present or the specified condition occurs, regardless of the btatus of the interrupt activation bits in control register 47, but interrupts are only generated if the corresponding activation bit in register 47 is a logic "1". The bit in the status register, which causes the interruption, is cleared to a logical "0" by the technical device when the interruption is recognized. The btatusbit or ütatusbits are also deleted by the program.

The timer overflow interrupt occurs at the end of the cycle in which the timer value is brought from 255 to 0 . Me Timer Compare Interrupt occurs at the end of the cycle following that in which the value of the timer register 56 becomes equal to the value in the compare register. Any interrupt will be delayed when another interrupt routine is in progress or when a multi-cycle instruction is in progress. Each interrupt condition has an associated memory location from which the interrupt vector address is fetched when the interrupt

030014/0880

3 *

In the event that several interruptions occur, that interruption has the highest priority which is the one with the Bit with the highest ordinal number of the status register 62 is present, e.g. B. status bit 7 has priority over status bit 6, which in turn enjoys priority over status bit 5, etc. If an interruption has occurred, further interruption conditions can be used exist before the first interruption is deleted.

The last program instruction in any interrupt servicing routine, which is stored in the foreground program is a return from the interrupt command HTI. if no interrupts are active when an interrupt processing routine has completed the last interrupt execution of the return from the HTI interrupt command results in program control being transferred to the background storage program returns. However, if there is still one interrupt while HTI is running, another occurs Interrupt and it is executed immediately by evaluating the corresponding interrupt vector memory location becomes because the effect of HTI is the same as executing an instruction to jump to a subroutine (Jsk), and it will a new vector address is supplied to fetch the jump address to be executed by the JSH instruction. The bits 5 dxs 7 des Status registers 62 can be programmed to cause an interrupt if the Interruption by the associated bit in control register 4-7 is activated. The bits 0 to 2 of the status register 62 cannot be written by program. It will only be 10 bits fetched from memory when an interrupt vector is needed as soon as an interrupt occurs. The three bits with the highest order AD10 to AD12 are determined by the device-related Facility generated.

0300U / 0880

If an interrupt occurs during a first machine cycle, the data processor stops executing the instruction being executed. Instead of storing the instruction that was fetched from the memory during this first machine cycle, the instruction decoding and control block 11 brings an operation code for an instruction to jump into a subroutine on line 22, namely for storage by the instruction register 24. The program counter Increment operation is turned off during this first machine cycle. The address bar 79 is driven by the interrupt priority and control block 61 instead of the program counter 76 to provide the location of the jump address for the recognized interrupt, and the jump address is fetched in the second machine cycle. During this second machine cycle, instruction decode and control block 11 brings line 14 to the address of the ninth eleven bit stack register to store the contents of M register 73 and ME register 74. Also during this second machine cycle, the output signal of the program counter 76 is fed to the input of the incrementing stage 77, the incrementing operation is switched off and the output signal of the incrementing device is stored in the T register 78. At the same time, the jump address that was fetched during this second machine cycle is taken from the memory and that LSS l ^v on the memory track, and it is transmitted through the buffer 85 and the line 86 to the input of the program counter 76th Finally, during the third machine cycle, the instruction stored at the jump address is fetched from the memory, while the previous program counter value, which is now stored in the T-fiegister 78, is transferred to the program counter stack.

The K-register 64 is an eight-bit register which is linked to the Data rail 52 is connected and an output signal to the selection circuit 16 supplies. Register 64 is a directly addressable register and it is also used to store the effective Register address for the indirect register addressing mode

0300U / 0880

to record. The K negister 64 is connected to the Ks register 63. The register 63 is also an eight-bit register and serves as a one-level stack for the register 64. As soon as a program interruption occurs, the contents of the register 64 are stored in the stack register 63. When the return jump from the interrupt command H'fl is executed, the content that was stored in the stack register 63 is transferred back to the K register 64.

The register 67 is a. «. Clit bit register which is connected to the data rail ^ Z to receive data from the rail 5 ^. The A register 67 is also connected to the arithmetic and logic unit 13 and supplies real and complementary output signals for this purpose. The hegister 67 contains one of the operands for two-operand operations, while the other operand is read from the addressable register. For most instructions, the result of the operation is returned to the addressed register in register area 43. Register 67 manages a group of single operand instructions. Register 67 contains the most significant half of a sixteen bit operand for split and shift double instructions and it contains the most significant half of a sixteen bit result of a multiply operation. A hegister 67 is not one of the addressable registers and its use is implicit in various instructions. The register 67 is connected to a stack register 66 having a single level. When an interrupt occurs, the contents of register 67 are transferred to stack register 66, where they are securely stored. After the end of the return jump from the interruption or the interruption command Rl ¹ I, the content of the stack register 66 is transferred back to the register 67.

The arithmetic and logic unit 13 is connected to the data rail 5'Z and supplies output signals for the shifting network 69 and the marking register 71 ° The zero and overflow bits

0300U / 0880

3 «

are sent to the tag register by the arithmetic and logic unit 13 71 is supplied in order to determine whether the result of the operation carried out by the unit I3 was equal to zero or a discharge signal was generated. Data from the data rail 52 can be transferred directly to the arithmetic and logging unit 13 or its complement can be selected by the command word before the data is entered into the unit 13 will. The inverter 68 serves to form the complement of the data on the data rail 52. The arithmetic and logic unit 13 performs the operations of adding, subtracting, of incrementing, decrementing and also the operations for the logical function AND, the logical function ODEü and the logical if function of the exclusive ÜDEii for data that is in the itegister 67 are stored and it performs this operation also for data that is stored in one of the addressable registers. The eight-bit result of the operation can preferably or optionally shifted one place to the left or to the right by the shifting network 69. The operations of multiplying and dividing are carried out by the arithmetic and logic unit 13 through multiple steps. The moving network is connected to the data rail 52 and cooperates with arithmetic and logic unit 13 to perform the shifting functions.

The tag register 71 is an eight-bit register which is connected to the data rails 51 and 52. In addition to the eight bits from the register 71 »those of the data rail 52 are fed, two of the bits of the data rail 51 are also fed fed. These two bits are the zero bit and the carry bit. As has already been explained above, the zero bit and the carry bit are generated by the arithmetic and logic unit 13 the marking register 31 is supplied. The register 71 is switched in such a way that it is read out via the data rail 52 by a program or inscribed in this way in the register

0300U / 0880

ic

can be. The kegister 71 contains indicator marks which can be set or cleared depending on the results of most arithmetic and logical operations. There are also markings that can be controlled and checked by the program. The marker bits in register 71 can be checked as jump conditions by the conditional warping commands. The mark register 71 is with a Marking stamp register 72 associated with a single notch. The stack register 72 is also an eight-bit register, and if so an interrupt occurs, it stores the contents of the register 71. At the end of the interrupt, when the instruction KTI is executed is, the contents of the stack register 72 into the register 7I transferred back.

The H register 73 is an eight-bit register, and it is with the Data rail 52 and connected to the address rail 79. That Kegister 73 is switched in such a way that it can be read out by program and also stored in the kegister by program, and it is only doubled when multiplying, dividing, shifting to the right, shifting to the left doubles, Read the memory, write into the memory, jump through the M register and jump but subroutine through M register commands used. When multiplying, dividing and shifting twice, the register 73 forms one half of one Sixteen-bit operands or a result, the least significant half. With those commands with which a memory is read out or written into a memory, the register 73 contains the eight bits with the least significant value the memory address, while the three most significant bits in the M extension (ME) of the register contain 7 ^ are. When jumping through M and when jumping into the subroutine through M, register 73 contains the eight bits with the lowest number Significance of the jump address, while the three bits with the highest significance of the jump address in the ME register 74-contain are. The ME register 7 ^ is a three-bit register,

0300U / 0880

and it is with the data rails 51 and 52 as well as the address rail 79 connected. Las register 7 ^ contains bits 8, 9 and 10 the memory address for the read memory, the write memory, the entry through the M register and the jump into the subroutine by the M-Iiegister. As mentioned above, divide the il-iiegister 73 and the llE-kegister 7 ^ into an eleven-bit interrupt support and stack registers, which is part of register area 48. That eleven bit register is there located where the contents of registers 73 and 7 ^ during a Interrupt routine is stored. During the execution of the return from the interrupt command, the content which was safely stored in the stack register into the register 73 and 7 ^ brought back. The program counter register is an eleven-bit register associated with data rails 51 and 52 and is connected to the address rail 79. Read Register 76 is a program counter and contains the address which is currently being fetched and which is increased by one if the individual Command words are fetched so that the commands are fetched from the program memory and executed one after the other. The registry 76 can be loaded via the jump command and the branch command so that this sequence of operations is changed. The incrementer 77 is connected to the program counter register 76 and increments that register 76. Register 76 receives ten input signals which are supplied via line 86 from the buffer 85, plus one input signal which is from the Command register 24 comes.

Eight eleven-bit registers are provided in the register area 48, the contents of the program counter register 76 during the subroutines and to save and ensure the interruptions. The eight eleven-bit registers also form a reserve stack eight levels, and those eight eleven-bit stacking registers are not addressable directly by program. Is the three-bit stack indicator 46 indicates which of the eight eleven-bit stacking registers is currently is addressed. If a jump to a subroutine or

0300U / 0880

2338713

If a program interruption occurs, the otapel display 46 is in order 1 removed, and the content of the program counter register '/ ö is transferred to the otapeiregister, which is indicated by the otapel display 46 is displayed. Thus, the stack display shows 4b usually also the last address that was saved. The stored address is the address to which the program back as soon as the routine or the Interrupt routine are completed. The return of the overroutine and the return jump; from an interrupt command can cause the program counter register '/ 6 to be reloaded from the stack register, which is determined by the bstack indicator 46 is specified and it then becomes the stack indicator 46 increments by 1 unless while executing the command li'rl is pending another interruption. Then it will be the stack indicator 46 is not incremented by 1, and the register 76 is with dera content; of the vector address instead of with the contents of the b-stack register to be loaded. Increment that or dexrementing the stack indicator 46 causes a wrap to be performed after eight storage locations have been used so that the stack can be viewed as a circular stack and thus more than eight addresses are stored in this otapel The oldest address is destroyed and only the most recent eight addresses are retained. the otapel display 46 Cannot be controlled directly by the program for writing in or reading out. Of the eight available Levels can be an interrupt return address if interrupts are used while the remaining levels are available for storing subroutines.

The temporary register 70 is also an eleven-bit register, and it is only used for the temporary storage of information. Register 78 is clocked during each machine cycle and receives ten input bits from line 86 and one input bit from command register 24. The outputs of register 78 are connected to the data rails 51 and 52. The output signal

03001 4/0880

the increment guide device ']' / can also be loaded into the temporary register ^r / b. This feature allows the contents of the program counter register 76 to be incremented and stored in the! Cycle is loaded.

The address rail 79 is an eleven-bit rail and is selectively connected to the external memory rail IiB through the selection circuit 81 and the output buffer 87. One of the bits from the address rail 79 is fed to the buffer 88 which has an output signal for supplies the output AD10. This one bit is taken from the bit with the highest significance of the eleven-bit program counter 76 or from the bit with the highest value of the Mwister 74. The selection circuit 81 selects either the address rail 79 or the data ^{rails 51 and 52 for connection to the storage rail i v} u3. The three-bit data rail 51 cooperates with the eight-bit data rail 52 to form a data rail which is capable of handling eleven-bit data. The selection circuit 81 is connected to the buffer 87 and to the i'est memory 83 if the read-only memory 83 forms part of the data processor 10. The memory rail IiB contains the 10 low order bits of the memory address during the first half of the clock cycle and the data bits during the second half of the clock cycle. The ten storage busbars MB are lines that assume three different states and can work in two different directions.

In order to describe the page limits of the processor 10, it is convenient to define three terms. The first expression is "foreground program" and means that part of the program which in heaction on the various interruptions

030014/0880

is executed, for example all those commands that are executed after an interruption, up to and including to jump back from the interruption, from the command IiTl. The second term "background program", which is part of that program, which in the absence of Interrupts or intermediate interrupt routines is performed. The third term is "data tables," and this term means the data words that are accessible from the memory by the memory read command. This address space would also have a Include memory into which data can be written, or a peripheral device that attaches to the storage rail HB is connected and can be accessed through commands such as read memory or write to memory.

Two steps are available for the background program. One page is only accessible to the foreground program, and another page can be accessed by both the foreground program and can also be addressed by the data tables. The page bit is controlled by the program that issued the jump page instruction and used to expand the background or foreground program from 2048 words of memory to Allow 4096 words of memory. In systems with a Storage capacity of 4E. or 6K. it is required a page bit to use to put the entire program in an available space, although neither the foreground nor the the background program exceeds 2048 words. The page bit, which is stored in the page-elip-plop 28, is activated by the Reset to zero command triggered. The jump page instruction inverts the page bit so that the pages are changed. A page change within the foreground and the background program can only be triggered by the page jump command will.

When an interrupt occurs, the background page bit is stored by a single level page stack 29 and that

0300U / 0880

MO

Side i'lip-flop 28 is then brought to zero for the foreground, and it can be changed as required. The jump back from the interrupt command sets the background page restore which was safely stored by the page stack 29, namely it is in the page i'lip-i'lop 28 brought. The outputs AD11 and AD12 select the side and are controlled by the technical equipment as explained above, and AD12 is set by the page bit controlled by the side lock 28. During the data transfer cycle of the Read Memory command or the In den command Write memory causes the puncture of the technical equipment during the data transfer cycle to AD11 and AD12 are supplied with the signal of a logic "1" when the memory M and the ME registers 73 and 7 ^ · are addressed. Therefore, all data must be on page 3 and are accessible, regardless of which page of the program is currently is performed. Digital data processing systems, which require less than 8K storage capacity, can have pages fold together by partially encoding the page address bits used to form memory sizes of 2K, 4K or 6K.

It became the basic structure or architecture above for a digital data processor which can be used as a general data processor, but in particular is suitable for special tax and Hegel purposes. The data processor 10 described above can be used in conjunction with a matching circuit can be operated in a special application in such a way that, for example, in the engine of a motor vehicle control is taken over, with the following tasks being taken over, for example: measurements on the machine, to carry out on the vehicle and in the ambient conditions and to generate resolution signals for the ignition signal, a control the exhaust throttle position recirculation and a controller to carry out the fuel measurement. There are four input / output signals (SOUT, HT1, HT2 and RT3) and a timing signal CLtC for communication between the processor 10 and a

0300U / 0880

linear adapter circuit supplied. The processor 10 performs its tit euerfunkt ion in response to these signals, namely via seven special input / output registers (registers 47, 53-56, 58 and 62). The seven registers are addressed via an instruction set in the same way as the other registers, without to make use of certain input / output commands, liie The first 31 registers in register area 48 can be addressed directly and indirectly, up to and including all register manipulation commands, and they can be used for arithmetic and logical operations. The seven input / output registers are in contained in this group of 31 registers. The registers 32 and Above it in the register area 48 are directly addressable, namely by instructions Load A and Save A, and they are through all other register manipulation commands can be addressed indirectly. That way, these registers aren't as easily accessible as the first 31 registers and should be used where possible is to handle and process data that is needed less often. Furthermore, a stack with one level is provided, to change the contents of registers 64, 67, 71 »73 and 7 ^. to save. The content of these registers is stored directly, together with the storage of the content of the program counter register 76 during a program interruption. After returning from an interrupt command, the content of these registers is stored together with the storage of the content of the program counter register 76 in the remaining registers returned. This is an extraordinarily quick one Responding to interruptions is guaranteed and the overall time which is required for an interruption is reduced to work off. The stacking register, which is used for storage of the contents of these registers are not addressable by the program.

In the i'ig. FIG. 2 shows a timing diagram which includes the external clock signal CLK and a series of internal clock signals T ^ ₁ , T ₂ , T ₅ and T ^. The external clock signal CLK is generated by the clock generator 36 and is an output signal from the

0300U / 0880

Buffer 38 »as it is in the i'ig. 1 is shown. The internal clock signals T ^ "to 1 'are supplied by the clock generator 36 and are shown in FIG Also shown in Fig. 2 are waveforms indicating the status of storage rail HB and data ^{rails 51 and 52 during a machine cycle.Jj 1} The typical process of iloling an instruction is CLk high during the first half of a machine cycle, and the address of the The memory space to be addressed is brought into the memory rail ilB, namely by the buffer 87 · During the second half of the machine cycle, CLK is lowered and the external permanent memory, which can only be read from, brings the addressed command to the memory rail MB, which is sent to the input buffer 85 is connected.

During a first clock phase T ^ the internal data rail 51 or 52 is charged in advance in order to transmit data from the hegister area 48 to the arithmetic unit 13. The program counter 76 is also connected to the incrementing device 77 during the clock phase 'I ^. During the internal clock phase Tv, the data word stored in the register area 48, which corresponds to the memory location selected by the selection device 16, is placed on the data rail for a typical command in order to be processed by the arithmetic and logic unit 13. During the internal clock phase T, the data rail is charged again in advance in order to prepare it for a second data transmission. Also during the internal clock cycle T ^ the arithmetic and logic unit 13 executes the instruction which was decoded by the instruction decoding and control block 11. Finally, during the internal clock phase T ^, the result of the operation carried out by the arithmetic and logic block 13 is fed to the data rail 52, specifically by the shift logic 69, and it is transferred to the register area 48 to be stored in the memory location which was selected by the selection device 16. Likewise

030014/0880

the program counter is loaded 76 from the incrementer 77, ^{un <i} though, is to pick up in the next machine cycle with the address of the instruction during clock phase T ^.

As shown in the figure, the address rails are precharged during the clock phase T 1. The content of the program counter 76 is with the incremented value during the clock phase T ^. brought up to date. At the trailing edge of T. the output of the program counter is fed to the address rail 79 to provide the address of the next instruction. The output buffer 87 is activated during the clock phases T. and IU in order to connect the address rail 79 to the memory rail MB. While the address rail 79 is being charged in advance during the clock phase T 1, the data rails 51 and 52 are connected to the input buffer 87 by the selection device 81. For a memory write command, the output buffer 87 is activated during the clock phases T 1 and T 1, in order to supply the data on the data rail to the memory rail MB, so that the data can be written into the memory. During the execution of all commands except the memory write command, the data rails 51 and 52 are switched on during the clock phase T _x . and also during the clock phase T, charged in advance. During a memory write command, the data rail is ^{not charged in advance during the clock phase 1} S-, so that interference from the data transmission to the memory rail MB is avoided.

The instruction register 24-, the program counter 76 and the T-Hegister 78 are brought up to date during the clock phase T ^. The program counter is usually loaded with the output counter of the incrementing device 77. During the jump instructions, however, the program counter is loaded with the ten bits of the data received by the input buffer 85 from the memory rail MB plus an eleventh bit which is received from the command register 24-. Typically, the T-Hegisbar78 ^w ith

0300U / 0880

Updated ten bits of data received from the storage bus MB and an eleventh Bit that comes from command register 24. However, if a Subroutine or an interrupt occurs, the T register 78 with the output signal of the incrementing device 77 to the brought up to date to a storage of the return address on the program counter stack.

The data rail is connected to the input of the arithmetic and logic unit 13 during the clock phase T-. The output of the shifting network 69 is typically connected to the data rail from the trailing edge of the clock phase T ₇ . connected to the leading edge of the clock phase 'IL. It should be remembered, however, that for a memory write command, the data rail is not precharged during the clock phase T-. Therefore, during a memory write command, the output of the shifting network 69 is connected to the data rail 52 from the bare rear of the clock phase Tp to the leading edge of the clock phase T. During the execution of most of the instructions, the register area 48 is written during the clock phase T. in order to store the data present on the data rail. During the execution of a branch instruction in a subroutine, however, the register area is able to write data during the clock phase Tp so that the return address can be stored on the program counter stack.

Although the command register 24 is loaded during the clock phase T ^ with an instruction to be executed in the following clock cycle, locking the new instruction will interfere with execution of the command that is currently running. During the clock phase T ^. the output signals of the command register 24 are passed through a logic circuit switched off and the command decoding lines within the command decoding and control block 11 are preloaded. The control signals that are used for the command just executed are decoded during

0300U / 0880

HC

the clock phase T- or ¹ J ?, for use during the clock phase '' S ₁ , locked. The output signals of the suitable interlocks are then passed on in the clock phase ¹ S ₁ in such a way that these control signals are available at the appropriate time. Latching the corresponding decoded signals before the clock phase ¹ S ₁ enables the circuit to be prepared for the decoding of the next instruction without the execution of the current instruction being disturbed.

FIG. 3 shows in a block diagram, like FIGS. 3A "to 3U, like the Arrangement can be made to build a logic diagram of a preferred embodiment of the subject invention.

The i) 'ig. 3A shows the register area 48 and part of the hegist addressing selector 16 within the dashed lines. Terminal 300 receives a reset pulse which is fed to the input buffer 301 in order to reset the component 43, which is shown in FIG.

The Fig. 3 ^ shows; part of the register address selection device 16, the register address decoder 49 and the register address control device 302. The Pig. 3C to 3F show the instruction decoding and control block 11.

FIG. 3G shows the K. register 64, its stack register 63 and the control device 303 labeled oOUT. The i'ig. Figure 3H shows the stack indicator 46, the stack indicator controller 304 and the register area controller 305. Figure 31 shows the reset circuit 43, the page register 28, the page stack 29, the cycle counter 21, the interrupt lock mask 42 and the multiplier / Divide Counter 17 * Figures 3 <J, 3 & and JL show some of the control logic for the instruction decode and control block 11. Figures 3L and 3F also show the instruction register 24. Figures 3F, 3L and 3U show memory rail connections HBO to MB9.

0300U / 088O

Fig. 3M shows crystal entrances 307 and 308, which are connected to a Clock generator 306 are connected via an oscillator, the between inputs 307 and 308 is shown. The control shift register or the instruction shift register 53 also appears in Figure 3M. 3N shows the capture registers 54 and 54 55 »the timer 56 and the equality circuit 57 · the jig. 30 shows the comparison register 58, the control register 47, the Status register 62 and the fixed-time connections RT1, RT2 and ΠΤ3

FIG. F shows the interrupt priority and control device 61 and the stack register 66 labeled AS. FIG. 3Q shows the A register 67, the arithmetic and logic unit 13 and the connection AD11 together with the control circuit for AD11. The i'ig. 3 ± i shows the shifting device 69 and the F-fiegister 71 · FIG. 3 & shows the connection AD10, the F-register stack 72, the memory expansion ME register 74 and the M-position register 73 · FIG. Y2 shows the incrementing device 77 and the program counter 76. FIG. 3U shows the temporary T-register 78 and the storage rail NB selector 309.

4 shows a circuit which is used to determine the occurrence of a trigger signal is used. The sampling circuit contained in dashed lines 100 has an input terminal 101 and an output terminal 102. The input signal received by the input terminal 101 is received by a non-inverting buffer 102, the output of which is connected to a coupling MOSFET 103 is. The gate of the MOSFET IO3 is through the internal clock signal T, controlled so that the output of the buffer 102 with the Node 104 is connected when the signal T ^ is high. Node 104 is connected to the input of a first inverter circuit 105, and node 104 is also connected to the feedback MOSFET 106 connected. The output of inverter 105 is connected to the input of a second inverter 107, whose

0300U / 0880

Hf

Output is connected to the return MOSFET 106. The gate of the hOSFET 106 is controlled by the complement of the internal clock signal T ^, so that the output of the inverter 107 is connected to a node 104 when the signal T ₅ , is low, so that the inverters 105 and 107 as well as the feedback MOSEET 106 form a locking circuit which responds to the logic state of the input terminal 101 during the time in which T ^ is high and which locks the status at the input terminal 101 when the signal T i is low.

The output of the inverter 105 is also connected to a first input of the exclusive ÜDEK element 108. The output of the inverter 107 is connected to a coupling MOSFET 109, the gate of which is controlled by the internal clock signal T-. When the signal T- is high, the output of the inverter is connected to a second input of the exclusive ODEß element 108. During the time in which the signal T- is high, the inverter IO7 and the MOSFET 109 operate in such a way that the second input of the exclusive ODEH gate 108 is brought to a high or to a low level, according to the Output status of the inverter 107. When the signal T ₂ returns to a low level, the HOSFET 109 acts like a high impedance, and the charge stored at the second input of the exclusive OR gate 108 has the effect that a high or at that input a low level is maintained until the time the signal Tp is brought back to a high level.

The exclusive OR gate 108 is used to either a transition from a high to a low level or a transition from to determine a low to a high level at the input terminal 101. Assume that input 101 is during of a first machine cycle is high when T i is high. During this first cycle, the

030014/0880

The inserted input is connected to the node 104, inverted by the inverter 105 and again inverted by the inverter 107, so that the output of the inverter 107 is at a high level. When T i goes low, the high output of inverter 107 is connected to the input of inverter 105, thereby locking the output of the inverter high. It is now assumed that during a second machine cycle the input signal which was received by input 101 was switched to a low level. While IV is high during the second machine cycle, the state of a high level at the second input of the logic link 108 is stored. Since the first input of the logic link 108 receives a low level from the output of the inverter 105, the output of the logic link 108 is a logic "1" or a high level. The MOSi ¹ El ¹ 111, which is arranged between the output of the logic link 108 and the positive supply voltage and which is active when the signal ϊρ is high, supports the build-up of a high level at the output of the logic link 108 during that time in the T ^ is high. However, if the signal ü. ¹ , is high during the second machine cycle, the low level now present at input 101 causes a high level at the output of inverter 105. Since both inputs of logic gate 108 are now high, the output of logic gate 108 is low, which indicates that an input transition or trigger signal was detected. During a third machine cycle, a low level is stored at the second input of the logic combination element 108 when the signal T- is high, and the output of the logic combination element 108 returns to a high level. If the signal '1 ¹ ^ is low during this third machine cycle, a low input level is again applied to node 104, and the high level previously latched at the output of inverter 105

0300U / 0880

Level remains unchanged. Thus, the output of the logic link 108 remains high when the signal I ¹ -, is high and continues until the input 101 is switched to a high level again.

As soon as a transition occurs at input 101, thus causes the output of the logic link 108, that the node 110 is lowered from the time at which T- is raised until the time i'p at the the following machine cycle is raised. The node 110 has a first inverting input of a logical AND element 11J connected. A second inverting input of the AND gate II3 is with the complement of the internal clock signal 1 \ is applied ο The output of the AND element 11j> is connected to output 102. So that the. Output 102 on a is high, both node 110 and signal ϊΤ must be low. When the output signal, which is supplied at the output 102, is used to lock the time in a memory or input register, such as If it is currently supplied by the timer, then conditions arise as they are based on the Ji'ig. 5 will be explained.

In the i'ig. 5 shows the two bits with the lowest value of the timer together with the two bits with the lowest value of a catch register according to a preferred embodiment of the invention. In the bit with the least significant value of the timer, the inverter 120 supplies an output signal at the node 121. The MOSi ¹ ET 122 is arranged between the output node 121 and the bit with the least significant value of the data rail 12J and has its gate with the control line 124- tied together. Similarly, the output node 125 of the second-least significant bit of the timer is connected to the data rail line 126 with the second-least significant value through the MOSI ¹ ET 127, the gate of which is also connected to the control line 124. The logic status of the control line 124 is determined by the command decoding and

0300U / 0880

controls lock 11 (-b'ig. 1) so that the output of the Timer is connected to the data rail when the control line 124 is high.

The output node 121 is also connected to an input node 128 of the MOSi ¹ ET 129. The gate of the MOSEET 129 is controlled by a clock signal T- so that the output node 121 is connected to the input node 128 when the signal Tp goes high. The input node 128 is also connected to the second-least significant data rail line 123 through the MOSiTST 131. Similarly, for the second least significant bit of the timer, input node 132 is connected to data rail 126 with the second least significant value through MOSiET 133. The gate connections of the MOSi ¹ ET 131 and MOSiET 133 are connected to a control line 134. The logic state of the control line 134 is determined by the command decoding and control block 11 so that the digital information present on the data rail is entered into the timer when the control line 134 is high. The logical link in the command decoding and control block 11 ensures that the control line 134 can only go high when the internal clock signal IV is high. Although input nodes 128 and I32 are loaded to match the logic status of output nodes 121 and 125, respectively, when the internal clock signal T ^ is high, the level at nodes 128 and 132 is modified to match the logic status of the data rail when IV goes high as soon as the transfer of data from the rail to the timer is activated by control line 1J4.

The input node 128 is exclusive to a first input ODEü member 135 connected. The second input of the OR gate 135 is connected to line 136, from which initially it is assumed to be a logic "1" or a high

0300U / 0880

Level leads. In this case the output of the exclusive UDER gate 135 is of an opposite logic state like the node 128. The output of the logic gate 135 is connected to the input of the inverter 120 through the MOoFET 137, the gate of which is connected by the internal clock signal T. is controlled. When the signal T. is high, the Input of the inverter 120 brought to a logic level "1" or to a logic level "0", which is from the output signal of the logic gate 135 depends, so that the output of the inverter 120 on the same logic state lies, like the node 128. Thus, the logic linkage element 135, the MUSEET 137, the inverter 120 and the tfückführ-NObZET 129 a latch circuit for storing the least significant bit of the timer.

However, if it is now assumed that line 136 is open a low logic level or a "0", then the output of the logic linkage element 135 is in the same logic state like the input node 128. If now the internal clock signal T ^ goes high, like the input of the inverter 120 is charged at the same logic level as node 128, and output node 121 becomes equal to the logic's complement State of node 128. After T ^ to a low Level has returned and T- has gone high is, the logic status of the input node 128 is inverted. Hence when line 136 is held low is, the logic status of the least significant timer bit is set once every machine cycle switched.

The input node 128 is also connected to the gate of the MOSi ¹ ET 138. The MOSFET 138 is arranged between the line 136 and the line 139. The second least significant bit of the timer works in a similar manner by adding the

0300U / 0880

State of this bit is also switched, the line 139 being at a low logic level. However, in order to bring the line 139 to a low logic level, the line 136 must be at a low logic level, and the MOSi ¹ ET 138 must be switched through, that is, the node 128 must be high. Thus the KUiIFET 133 causes that The bit with the second least significant value is only toggled half as often as the bit with the least significant value of the timer. Similarly, HOSFET 141 connects a low logic level to line 142 only when the input node and input node 132 are both high. The line 136 is also connected to the gate connections of the MUSI ¹ ET 143 serving for pre-charging and the corresponding MUSFET 144. When the line 136 is at a high logic level, the MUSi ¹ ET 143 connects the positive supply voltage to the line 139 'and the MUtJI ¹ ET 144 connects the positive supply voltage to the line 142, so that this leads to a high level in advance to be charged. When line 136 returns low, the least significant bit of the timer is toggled when T. goes high. The remaining bits of the timer are only toggled when the low level on line 136 exceeds the remaining stages by the MUSiET

138 and the MUSiJ ¹ ET 141 etc. is fed.

The logical status of line 136 is determined by the command decoding and control block 11 controlled. The logic level on line 136 is brought high during every machine cycle to ensure that the lines

139 and 142 and the following lines in the increment chain are driven high during each machine cycle. As mentioned above, the Control logic in the preferred embodiment of the subject matter of the invention can be programmed by the manufacturer by a Metal mask is used so that the timer is set once every machine cycle, once every two machine cycles, or once every

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four machine cycles, is incremented. This is because of this achieves that the possibility is created that the logic state of the line 136 corresponds to a low level, namely during each occurrence of the internal clock signal T-, during every second occurrence of the internal clock signal T ,, or during every fourth occurrence of the internal clock signal T ..

In order to lock the state of the timer device when a trigger signal is determined, the output node 121 of the liits with the least significant value of the timer is connected to the input node 14-6 of the bit with the least significant value of an ij'ang register by the MuSi) ¹ ET 14- 7 connected. Similarly, output node 125 is connected to input node 14-8 through M (JUi) ¹ ET 14-9. The gate connections of the MOSi) ¹ ET 14-7 and the MOSi) ¹ ET 14-9 are connected to the control line 150, which in turn is connected to the terminal 102. It should be noted that the terminal 102 is the output terminal of the trigger signal sampling circuit 100 according to i) 'ig. 4- is. Thus, when a trigger signal is detected, control line 105 is brought high, thereby connecting output nodes 121 and 125 to input nodes 14-6 and 14-8, respectively. An essential feature of the preferred embodiment of the invention is that the transmission of the timer output signal on the catch register input does not depend on the data bus lines 123 and 126 being used. This enables the time at which the trigger signal is detected to be recorded or stored without interfering with other operations performed by the data processor which would normally require the use of the data rail. It should be noted, however, that the input node 146 is connected to the data rail line 123 of the MOSi) ¹ ET 152 and that the input node 148 is connected to the data rail line 126 through the IiOSi) ¹ ET 153. The gate connections of the MÜSSET 152 and the MOSi) ¹ ET 153 are connected to the control line 15 ^, so that the information available on the Üatenschiene dem

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Input node of the input register can be supplied, wherein the Beiehls decoding and control block 11 has a high level on the control line 15 ^ · brings. This feature enables that the first register from the Jatenschiene is under program control is loaded.

The input node 146 is connected to the input of the inverter 156 and the output of the inverter 156 is connected to the input of the inverter 157. The output of the inverter is connected to output node 158 so that the logic state of input node 146 is duplicated at output node 158. A feedback MOSi'ET 160 connects the output node 158 to the input node 146. The gate of the IiUUi ¹ ET 160 is supplied with the internal Trktsignal T, so that the input node 146 is charged to a logic level which is the logic level of the output node 158 corresponds to when the internal clock signal T ^ is set high. Thus, the inverter 156, the inverter 157 and the feedback MOSi'ET 160 form a backfill latch circuit for storing a data bit. The second least significant bit of the pang register has an output node 161 and operates in a similar manner.

The output nodes 158 and 161 of the capture register are connected to the data rail lines 123 and 126 through the MOSi ¹ ET 162 and through the MOSjj'ET 163, respectively. The gate connections of the HOSi ¹ ET 162 and the IiOSi ¹ ET 163 are connected to the control line 164 so that the output nodes of the input register are connected to the data rail when the command decoding and control block 11 connects the control line 164 to a brings high level. This feature enables the data rail to be operated from the input register output under program control. The MOSi'ET 147 and the MOSi ¹ ET 149 thus form a first input device which is connected to the timer output nodes 121 and 125 and is controlled by the output signal of the sampling circuit in order to store the time output signal from the timer in the input register when a trigger signal

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is determined. The HUiSi ¹ ET 162 and the MOSFET 163 are used to connect the output of the input register to the data rail. The MOSEET 152 and the MOSi ¹ ET 153 are a second input device which is connected to the data rail in order to cause the input register to store those data which are present on the data rail when the control line 154 is at a high level lies.

Fig. 4- further shows a device which is used to bring about an interruption in the data processor in response to the sampling of a trigger signal. A device which is used to display the status of the scanning circuit 100 is shown within the dashed block 166. The node 110 of the sampling circuit 100 is connected to a first inverting input of an ODEK element 167. The second inverting input of the ODEK element 167 is connected to a node 168. The output of the ODEH element 167 is connected to a node 169 of the MOSEET 170. The gate of the MOSi ¹ ET 170 is supplied with said internal clock signal T., so that the node is brought to a logic level 169 which corresponds to the output signal of the logic gate circuit 167, when the signal is set high T.. Node 169 is connected to the input of inverter 17I and the output of inverter 171 is connected to node 168. It is assumed for the present description that the node 110 is at a high logic level, and then the inverter 17 '· »form the logic link 167 and the MOSi ¹ ET 17O a feedback latch circuit for storing a digital status. If, however, the node 110 comes to a logic level "0", the output of the logic combination element 167 is brought to a high level, which is led to the node 169 the next time the internal clock signal T ^ occurs. As already explained above in the discussion of the sampling circuit 100, the node 110 only goes to a low logic level if a transition occurs at the input terminal 101

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is determined. Therefore, if the status circuit 166 is triggered so that the node 169 is initially low, then the node 169 remains low until the occurrence of a trigger signal is determined, after which the node 169 is locked in a high state. MOSi ¹ ET 172 connects node 129 to ground under the control of input terminal 173, thereby enabling node 169 to be triggered or activated to a high logic level when terminal 173 is high.

In the dashed block 17 ⁷ ^ there is a device which serves to control the generation of an interrupt in response to the logic status stored in the status circuit 166. The control circuit 174 has an input node 175 and an output node 176. The entry node

by
175 / the MOSi ¹ ET 177 can be brought to a low logic level, as a result of which the input node 175 is connected to ground when a reset signal which is fed to the gate 178 is at a high logic level. The input node 175 is also connected to the data rail line 179 through the MOSFET 180, so that the logic state of the input node 175 corresponds to the logic state of the data rail line 179 when the control terminal 181 by the command decoding and control block 11 to a high logic level is brought. This-

enables the control circuit from the data rail via Program is loaded.

The input node 175 is connected to the input of the inverter 183 tied together. The output of inverter 183 is connected to the node and to the input of inverter 185. The exit of inverter 185 is connected to output node 176. The output node 176 is connected to the input node 175 through the Coupling MOSFET 186 returned, its gate to the internal Clock signal T ^ is applied. When the clock signal T ^ is high, the input node 175 goes to a logical

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Brought to the state which corresponds to the logic state of the output of the inverter 185. Thus, the inverter 18j5, the inverter 185 and the return MUS.tt'ET 186 form an itfickführung interlock circuit for storing a logic state of the input node 175. The output node 176 is also connected to the data bus line 179 through the HOSi ¹ ET 187, the controlled by gate 188. When command decode and control block 11 drives terminal 188 high, output node 176 is connected to data rail 179, thereby allowing the status of the control circuitry to be driven onto the data rail under program control.

The logical state of the status register 166 is established by a corresponding logical connection with the logical state the control circuit 174- connected »namely to the purpose of bringing about a masking of an interruption which is triggered by the scanning of the occurrence of a trigger signal. The logical AND element 189 acts in the Way that this masking function is carried out. The node 168 of the status circuit 166 is inverted with a first Input of the logic link 189 connected. The node 184 of the control circuit 174 is connected to the second inverting input of the logic link 189 connected. The output of the logic link 189 is connected to interrupt terminal 190 which is brought to a high logic level when an interrupt occurs should occur. If it is desired to block an interrupt in response to the sampling of the trigger signal, Program control causes a logic "1" level at node 184 to be latched. This becomes the break terminal 190 brought to a low logic level, independently from the logical status of node 168. At a later time, when it is easier for the data processor, to a

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Responding interruption causes a program instruction that the node 184 locks a low logic level, which activates the logic combination element 189. If already a Trigger signal has been detected, then node 168 is already at a low logic level and it is immediately generates an interrupt. If a trigger signal fails has been determined, an interruption is generated immediately after the trigger signal has been sampled. The instruction decoding and control block 11 is designed so that a high logic level at the interrupt terminal 190 a high Level at the reset terminal 173 generated to control the status circuit 166 reset, which enables the status circuit 166 to store the next sample of a trigger signal by the sampling circuit 100.

The above based on the FIq. 4- described sampling and interruption circuit enables the catch register to store the time at which the trigger signal was detected and to postpone the interruption of the data processor until such a later time at which the interruption in response to the occurrence of the sampled trigger signal can be easily processed.

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, ^S9

Read 11 e

Claims (1)

Claims Integrated l) at processing circuit with a plurality of registers which are arranged in an area, which registers are directly addressable and capable of doing so are to store digital data with an arithmetic logic unit for performing predetermined operations the data, with an instruction decoder for decoding of commands for the integrated data processing circuit, with a command register, which with the Instruction decoder is connected to receive instructions, to be decoded by the instruction decoder, and with an irrogram counter which is a Can accommodate memory address and can be incremented, characterized in that a first register (67) is provided, which serves to half with the highest priority of a double word overperand and half with the highest significance of a double value result from a multiply instruction record that there is still a second register (73), which is used to half with the lowest Include the significance of a double-word operand and the part with the least significance of a memory address, that further a timing register (56) is provided, which is able to with a continuous Rate to be incremented by 1, the time control register serving to provide a time reference signal that at least one catch register (5 ^, 55) is still available, which is able to be loaded directly from the timing register when a signal transition on a Input signal (RT1, RT2) of the data processing circuit occurs that a comparison register (58) is further provided to store a predetermined time and to continuous with a view to equality with that Ö300U / 08Ö0 Timing registers to be compared to generate a signal if there is an equality that continues to be a Control shift register (53) for serial shifting of data in a corresponding control is present, wherein the control shift register, which can also be referred to as the command shift register, is able to Move data when the timing register matches a value stored in the compare register is that there is also an input / output control register (47) which is capable of controlling of predetermined interrupts and that finally an input / output status register (62) is present is to indicate the causes of interruptions. 2. A circuit according to claim 1, characterized in that an expansion register (74) is provided to the bits with the record the highest priority of a memory address. 5. A circuit according to claim 1, characterized in that a a third register (64) is provided, which is directly addressable and can accommodate a register address of a register can, which is to be addressed indirectly. 4. A circuit according to claim 1, characterized in that a circuit (81) is provided to one of a plurality select of rails that at least one data rail (51, 52) is connected to the selection circuit that further an address bar (79) connected to the selection circuit and that the selection circuit is able to select one of the rails to be an external rail (MB9-MBO). Ö300U / 0860 5 data processing arrangement with an N-bit data rail, with an M-bit data rail and with an M + N-bit address rail, characterized in that an instruction decoder for the decoding of commands for the data processing arrangement is provided that furthermore a command register (24) is connected to the instruction decoder for receiving instructions received from the instruction decoder are to be decoded that furthermore a range of registers (48) is provided in order to change data store, being the range of registers with the E-bit data rail is connected that further an arithmetic and logic unit (18) with the N-bit data rail and with the Instruction decoder is connected so that the arithmetic and logic unit is able to perform operations to execute the data stored in the area of hegisters that a program counter (76) is also provided to the Sequence of commands to control that the program counter is connected to the address rail, further characterized by that a timing register (56) is present which is able to continuously increment by 1 to become that the timing register with the N-Bitüatenschiene is connected that at least one capture register (54-1 55) is present, which is able to from to be loaded from the timing register, that at least an existing capture register is connected to the N-bit data rail, is connected to the timing register and with an input terminal (Rl "!, RT2) of the data processor device is connected to enable at least the capture register to be loaded from the timing register, as soon as a signal transition occurs at the input terminal, there continues to be a comparison register (58) with the N-bit data rail is connected that the comparison register is able to continuously with regard to a Equality to be compared to the timing register to provide a signal when an equality is present that the control shift register or command shift register (53) 0300U / OÖÖO -if - is connected to the N-bit data rail and to an output terminal (S ^ .n,) of the data processing arrangement and that the control shift register or command shift register a temporary storage of data and a shift of data from the output terminal to a predetermined one Control signal or a predetermined command possible. 6. Arrangement according to claim 5i, characterized in that a Control register (4-7) is connected to the N-bit data rail that the control register has program control of at least to the control shift register and that a status register (62) is connected to the N-bit data rail is to temporarily store data indicating the causes of interruptions. 7 · Arrangement according to claim 5> characterized in that the N-bit data rail is an eight-bit data rail that the M-bit data rail is a three-bit data rail and that the II + N-bit address rail is an eleven-bit data rail. 8. Arrangement according to claim 7> characterized in that one Adaptation rail (hB9-I'iBO) for adapting the data processing arrangement to an external circuit is available and that a circuit (81) is provided to selectively connect at least a portion of the address rail to the interface rail to connect or the N-bit rail and at least part of the Ιΐ-bit data rail to the adapter rail associate. 9. Small plate for an integrated circuit with a data processing circuit, an instruction decoder for decoding instructions and controlling the Has operation of the data processing circuit, which further comprises an instruction register which is associated with the Command decoder for receiving commands 0 3 0 0 1 W08ÖÖ which are to be decoded, which further comprises a data rail to carry data within the chip of the integrated circuit, which further comprises a range of registers connected to the data rail, the range of registers for storing changeable data which further has an arithmetic and logic unit to perform operations on the stored data in the area of registers, the arithmetic logic unit being connected to the data rail, which furthermore has a »shift circuit for shifting data from the arithmetic and logic unit disposed between the data rail and the arithmetic and logic unit, characterized in that a first register (67) is disposed between the data rail and the arithmetic and logic unit for use with predetermined instructions, further comprising a Input / output circuit is available, which a »control shift regulation ster (53) has that at least one input register (5 ^ i 55) »a time control register (56)» a comparison register (58), a »control register (4-7) and a status register (62) are provided all of which are connected to the data bus, wherein the iSteuerschieberegister thereto is able ^to move data to a corresponding controller through to an output terminal (QTj.n) that this is at least present a ii'angregister able from the timing register that the timing register is able to be incremented by 1 with a continuous rate, that the comparison register is able to store a predetermined amount and to be continuously compared for equality with the timing register to provide a »signal, if there is an equality, that the» control register is able to provide program control of the preselected registers of the input / output circuit, and that the status register is able to temporarily store data indicating causes of interruptions. 0300U / 0880 10. The arrangement according to claim 9> characterized in that a Part of the data rail is expanded in such a way that it can process a larger number of data bits. 11. Arrangement according to claim 9 _5, characterized in that an address rail (79) is present to carry an address. 12. Arrangement according to claim 9 _5, characterized in that a clock generator is provided to generate clock signals for the wafer, that further an interrupt and Iiaskierungs circuit (42) is connected to the command decoder to lock existing interrupts and to future Mask interruptions. 13. Microprocessor with a digital rail, for execution a first set of instructions and, for responding to interrupts, for executing a second set of Commands, characterized in that a first circuit (56) is provided to generate a first digital signal, that the first circuit brings about an incrementation of the first digital signal with a periodic sequence, so that the first digital signal is representative of the time that a second circuit (58) for storing a second digital signal is present that furthermore an equality detector (57) with the first circuit and is connected to the second circuit that the equality detector supplies a equality signal, which indicates when the first digital signal is equal to the second digital signal, and that a third circuit (4-7, 53 »62) is connected to the equality detector and is responsive to the equality signal for an operation by the microprocessor, the third circuit operating in such a way that the operation occurs during the Is to be executed during the time in which the microprocessor executes the first set of instructions, or during the time in which the microprocessor executes the second set of instructions. 0300U / 0880 14-, microprocessor according to claim 131, characterized in that that the first digital signal generated by the first device is a real time reference signal. 15 · Microprocessor according to claim 14, characterized in that that the third circuit performs the serial data shift operation; that the third circuit performs the operation the serial data shift triggers when the equality signal indicates that the first digital signal is equal to the second digital signal is. 16. Microprocessor according to claim 15 »characterized in that that the second circuit has input terminals which are arranged such that a connection with the digital Rail (52) can be produced, and that the input terminals are used to receive a digital signal which is to be stored by the second circuit. 17. Microprocessor according to claim 16, characterized in that that the third circuit has the following parts: input terminals, which for connection to the digital rail are suitable, the input terminals being used to receive a third digital signal, a shift register (53)> which is connected to the input terminals to carry out the storage of the third digital signal and to produce a serial shift of the stored third signal when the equality signal indicates that the first digital signal is equal to the second digital signal, and an output terminal (& qtjj-i) for transmission of data output from the shift register in a serial manner. Ö300U / O8Ö0 18. Microprocessor after. Claim 17, characterized in that that a circuit (61) is provided which is connected to the equality detector to selectively enable or disable the generation of an interrupt when the equality signal indicates that the first digital signal is equal to the second digital signal. 19. microprocessor for processing digital information, characterized in that a timing control circuit (56) is provided which is responsive to a clock signal that the timing control circuit is designed such that it provides a first digital output signal which is representative of the time that continues a circuit (100), (Js'ig. 4-), is provided to determine the occurrence of a 'trigger signal (KI ¹ I, K'T2) that at least one storage circuit (54-, 55) is present which is able to store digital information, and which has a first input (14-7 »14-9) ^u * id an output (162, 163) that the first input is connected to the timing circuit and to the Sampling circuit responsive to store the first digital output signal in the at least present one memory circuit upon occurrence of the trigger signal that the output signal is used to provide a second digital output signal, which is representative of the digital information stored in the at least one available memory, and that a digital data rail (52) is connected to the output for the transmission of digital information. 20. Microprocessor according to claim 191, characterized in that that the output is responsive to a first control signal (164) to convert the second digital output signal to the digital to bring üatenschiene. Ü3001A / 0880 21. Microprocessor according to claim 20, characterized in that that the timing control circuit has a first »circuit (122, 127) which is connected to the digital rail, that the first »circuit is responsive to a second control signal (124) responds to bring the first digital output signal onto the digital rail. 22. Microprocessor according to claim 21, characterized in that the time control circuit has a second circuit (131> 133), which is connected to the digital rail, that the second circuit to a third control signal (13 ^) responds to set the timing circuit in advance to a time determined by the digital information on the digital rail is shown. 23. Microprocessor according to claim 22, characterized in that that the at least one memory circuit present has a second input circuit (152, 153) which is connected to the digital rail is connected, and that the second input circuit is responsive to a fourth control signal (15 ^), to get the digital information on the digital track in the least 4. microprocessor according to claim 20, characterized in that that the microprocessor is suitable for executing a plurality of instructions stored in a memory, and in that the microprocessor has an instruction decoder (11) which is responsive to a plurality of instructions, to provide the first control signal. 5. Microprocessor according to claim 20, characterized in that that the microprocessor is designed in such a way that it has a plurality of instructions stored in a memory can execute that the microprocessor continues to have a 030014/0880 Interrupt circuit (166, 17 ^), which with the Sampling circuit is connected, and that the interruption circuit is designed such that it is an interruption in the execution of the plurality of commands in response to the detection of the occurrence of the trigger signal brings about. 26. Microprocessor according to claim 20, characterized in that the interruption circuit has the following parts: a status circuit (166) responsive to the sampling circuit, the tit at us circuit having a first and a has second logical status and is in the first logical status before the trigger signal is detected and im The second logic status continues to be a control circuit after the occurrence of the trigger signal has been determined (174-) »which is connected to the digital rail to store digital information, and finally one Masking circuit (189) 1 which with the status circuit is connected and responsive to the control circuitry to selectively eliminate the interruption in the execution of the Activate multiple commands. 27 · Microprocessor according to claim 19 »characterized in that that the sampling circuit is based on a binary input signal (HT1, HT2) responds, which has a first and a second status, and that the occurrence of a trigger signal is determined when the binary signal changes from a first status to a second status. 28. Microprocessor according to claim 27, characterized in that an occurrence of a trigger signal also in the event of a transition of the binary input signal is determined from the second status to the first status. Ö300U / 0880 29 · Microprocessor according to claim 19, characterized in that that the timer circuit comprises a counter which is responsive to the clock signal and that the counter with a continuous eat is incremented. 30. Microprocessor according to claim 29, characterized in that the counter has a timer register and one Has incrementing device and that the incrementing device is responsive to the clock signal to increment the timing register by 1 with a continuous hatch. 31. Microprocessor according to claim 30, characterized in that the time control register and the incrementing device each have a MOSi ¹ ET. 03001 4/0880