DE2933883A1 - CHARGED COUPLING ARRANGEMENT - Google Patents

Description

N. V. Philips' ßloGÜampsnfabriokcn, Eindhoven ~ ">" *

26-4-1979 j ** 'PHN 9210

"Charge coupled arrangement"

The invention relates to a charge coupled device Arrangement with a semiconductor body, which carries an insulating layer on one surface, on which electrode regions are attached, with the help of which a potential pattern is created in the underlying part of the semiconductor body for storing and transporting cargo packages can be generated, wherein means are present, with the help of which in the semiconductor body under the electrode areas Drift fields are generated.

Charge coupled arrangements are based on various Areas, e.g. as a delay line and in transversal filters, used in signal processing arrangements. You will also find, among other things, in the field of image reproduction and digital technology (memory, logic circuits) Use.

One advantage of using drift fields in charge-coupled arrangements is that the charge packets can be transported much faster than in the absence of these drift fields. In the absence of drift fields the charge is transported through a diffusion process at which the diffusion current is exponent! ell decreases.

Such drift fields can occur in so-called "bulk" charge-coupled arrangements as a result of the large

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Distance between the charge packets and the electrode areas can be obtained. These arrangements are in general, however, with the usual integrated MOST circuits not compatible; this is in contrast to so-called "surface" charge coupled devices in which the Storage and transport of the charge packets at least substantially at the interface between the insulating layer and the semiconductor material. A "surface" charge-coupled arrangement with drift fields is therefore often used preferred.

Such a charge coupled device is known from US Pat. No. 3,796,932. In the described therein Arrangement, the drift fields are generated in that the semiconductor body is non-uniform under the electrode areas is doped, so that asymmetrical potential wells are formed under the electrode areas during operation will.

In other embodiments of that shown therein The drift fields are arranged by a non-uniform distribution of immobile charge in the insulating layer or by a discontinuous thickness of the insulating layer under the electrode areas or by a Combination of these two conditions is obtained.

The application of immobile charge in the insulating layer is difficult to carry out in practice and requires additional processing steps. Something like that applies to the application of non-uniform doping under the electrodes or to the discontinuous application the insulating layer. In addition, it is particularly difficult in practice to achieve a continuous, non-uniform To apply doping, so that you are, as is also described in the patent mentioned, usually with a step-like approximation of the desired doping profile contented. As a result, the potential generating the drift field is also step-shaped.

One of the objects of the invention is to provide a charge coupled device To create an arrangement in which no additional doping steps are required and also none

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step-shaped insulating layer needs to be applied, and, moreover, a very precisely linear change in potential is obtained under the electrode area in the operating state. It is based on the knowledge that this task can be achieved in that over the electrode area in the operating state a voltage drop is generated, which is a practical in the underlying material uniform linear potential change, brings about that the desired drift field is generated.

A charge-coupled arrangement according to the invention is characterized in that the electrode regions an uninterrupted strip-like resistance form, which is provided at regular intervals with connections for offering clock voltages, the electrode areas by parts of the strip-shaped resistor between two consecutive terminals are defined, thereby adding different voltages to these terminals are applied, the said drift fields are generated in the semiconductor body.

If voltages are now offered at two adjacent connections, there will be a voltage drop over the part of the strip located between these connections Shaped resistance generated. This creates a continuously changing potential in the underlying Semiconductor body hand in hand. With a suitable choice of the offered voltages, drift fields are generated, which cause the intended transport to take place at an increased speed.

An advantage of the arrangement according to the invention is that they are compared in a particularly simple manner to the known methods described for the production of charge-coupled arrangements with drift fields can be produced because no additional process steps are required for attaching a doping profile and the strip-shaped resistor in a particularly simple way can be attached.

In a particularly simple embodiment, the strip-shaped resistor can be practically homogeneous.

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A preferred embodiment of an arrangement according to the invention is characterized in that each Pair of successive electrode areas have a common Includes connector. Although, unlike conventional charge coupled devices, each electrode region has two Contains connections, the total number remains due to this measure the connections are practically the same.

Preferably contains the strip-shaped

Resistance polycrystalline silicon, making the arrangement with the aid of process steps generally known in semiconductor technology can be produced.

An important preferred embodiment, the among other things has the advantage that a charge-coupled arrangement for high-frequency applications together with for these uses common MOS transistors in a common Semiconductor body can be attached, is characterized in that the arrangement is a "surface" charge-coupled device Arrangement is in which the storage and transport of the charge packages at least essentially take place at the interface between the insulating layer and the semiconductor material.

Some embodiments of the invention are shown in the drawing and are described in more detail below. Show it:

Fig. 1 schematically in section a known charge-coupled arrangement,

Fig. 2 is a plan view of a charge-coupled device according to the invention, Fig. 3 shows a cross section through the charge coupled device taken along the line III-XII in Fig. 2,

FIG. K shows the electrical equivalent circuit diagram of the electrode structure of the charge-coupled arrangement according to FIG. 2,

5 shows the potential profile and the charge transport brought about by it during operation of the arrangement according to Fig. 2,

6 shows the potential profile and the charge transport in another application according to the arrangement

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Fig. 2,

7 is a plan view of the electrode structure of another charge coupled device according to FIG of the invention, and

8 shows the potential profile and the charge transport brought about by it during operation of the arrangement according to FIG. 7.

The figures are schematic and not to scale drawn, for the sake of clarity in the cross section in particular the dimensions in the thickness direction are greatly exaggerated. Semiconductor regions of the same conductivity type are generally in the same direction hatched; In the figures, corresponding parts are generally denoted by the same reference numerals.

Fig. 1 shows schematically in section part of a known charge coupled device of of the type to which the present invention relates and which is described in U.S. Patent 3,796,932. The order is for example of the n-channel type and contains a p-conductive silicon body 2, the surface 3 with a Insulating layer 4 is provided. On this insulating layer there are electrode regions 5 in the form of a series of metal electrodes attached, which are connected to clock lines 12 for offering clock voltages, creating electron bunches from below one electrode 5 to a following electrode be transported. Means are available for quick transport, with the help of which drift fields under the Electrodes are generated and, in this example, from a zone 14 attached below the surface 3 with a consist according to the sawtooth profile I5 changing η-doping. The doping concentration is drawn increasing downwards, which is indicated by the arrow 16. The effect of this doping is that when a suitable voltage is applied to the electrodes, a surface potential is created occurs, which changes with this doping and an almost identical sawtooth-shaped curve of the electron potential brings about, as described in the aforementioned patent. This causes the electrons

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in an electrical generated by this potential curve Field also accelerated.

Sawtooth-shaped profiles can be used in the Practice, however, difficult with the help of doping the semiconductor body obtain. As a rule, one is therefore content with a rough, step-like approximation.

Other means for generating drift fields, such as doping the insulating layer according to a Sawtooth profile or the application of an insulating layer changing thickness cannot be easily realized in practice.

Figures 2 and 3 show a plan view

or a cross section through a charge-coupled arrangement according to the invention, in which drift fields can be generated with an electrode structure that is easy to manufacture. It is a charge-coupled arrangement of the type in which charge transport takes place in the form of electron transport along the surface. The arrangement contains a conventional p-conducting silicon substrate with a doping concentration between 10 and 10 atoms / cm. The body 2 is provided on its surface 3 with a thin insulating layer h , which as a rule consists of silicon oxide, but can also consist of other materials or a combination thereof. On this insulating layer there are the electrode regions 5 ', which are designed as an uninterrupted strip-shaped resistor, which is provided at regular intervals with connections 6 for supplying clock voltages. The charge transport takes place under this strip-shaped resistance in the longitudinal direction.

The electrode areas 5 are through the parts of the strip-shaped resistance between two consecutive Connections formed. With the aid of these electrode regions, potential patterns can be created in the underlying semiconductor body for storing and transporting cargo packages.

The potential patterns are obtained by applying clock voltages with a

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such size and polarity are offered that im Semiconductor body at the interface with the insulating layer, an exhaustion zone is formed, as is generally known is. Because in the arrangement according to the invention, the clock voltages that are offered at these connections, cause a potential drop across the intermediate electrode area, in the area below this electrode area lying part of the semiconductor body generates drift fields that accelerate the charge transport, whereby the Transmission effect is improved.

The arrangement is further provided with a source region 7 and a drain region 8 for supplying or removing movable charge carriers (electrons in the present example). In Fig. 2, the circumference of the areas 7 and 8 is indicated schematically by a dashed line. The source and drain regions are each formed by an η zone with an impurity concentration of, for example, 10 atoms / cm ^J. In addition, in order to avoid charge loss and charge transport in the transverse direction, the arrangement contains a channel interrupter 9 of the ρ type, the limits of which are likewise indicated in FIG. 2 by a dashed line.

The arrangement according to FIGS. 2 and 3 can easily be produced by generally customary MOST processes without the need to perform critical alignment steps and without overlapping gates available. In that the arrangement can be manufactured by such processes, it can be easily integrated into one single semiconductor body combined with other elements, such as MOS transistors and resistors, and in a simple manner Way to be incorporated into more complex integrated circuits.

In order to generate a potential difference across an electrode area, per electrode area two connectors are attached; this is in contrast to the usual arrangements in which one is with a single Connection can get by. In the arrangement according to FIG. 2, two consecutive electrode regions always have

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a common connection 6, so that the ^ eesämtänzahl the connections is practically the same as that of the conventional charge-coupled arrangements with separate electrode areas.

In the operating state, the substrate is grounded or connected to a reference voltage. The input signal is fed to the input diode formed by the substrate 1 and the η region 7 via a contact track 10 made of, for example, aluminum or another suitable material. At the exit, the electrons are collected in an η region 8 which forms the cathode of an output diode which is connected to a positive voltage V _{via a resistor R 1, shown schematically.} Changes in the accumulated charge are detected as changes in current through resistor R ₁ , which cause voltage changes at the gate of a MOS transistor T ₁ , whereby the changes in current and therefore that supplied by the charge coupled device. Signal to be amplified. The n ^{+ region} 8 is provided with a contact 11 for this purpose. The transistor T ₁ is an n-channel transistor, the source and drain zones of which are formed at the same time as the source and drain zones of the charge-coupled arrangement, while the gate electrode is attached at the same time as the terminals 6A.

The resistance strip 5 As * over low resistance Connections 6 (6A, OB, 6C, 6d) with the clock lines 12 (12A, 12B, 12C, 12D) connected. In the present example, the resistance strip 5 consists of low-doped polycrystalline! Silicon with a sheet resistance of 10 to 100 kOhm per square, while the connections 6 made of highly doped polycrystalline silicon with a sheet resistance of consist of about 20 ohms per square.

The connections 6 are at practically equal mutual distances transversely to the strip-shaped Resistor 5 », which is practically homogeneous, is connected (Fig. 2). The part of the strip-shaped resistor between two consecutive connections (6A and 6B, 6b and 6C, 6C and 6D or 6D and 6a) satisfy the same Functions like an electrode for supplying clock voltages

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in a charge coupled device of the usual type. The strip-shaped resistor with its connections can be represented by the electrical equivalent circuit diagram according to FIG. K. Between successive connections on the clock lines 12 (A, B, C, D) there is always a resistor R which has practically the same value everywhere. If suitable voltages are now offered at these connections, potential differences occur across the resistor R. As a result, a potential profile is obtained in the body under the electrode areas represented by the resistor R, with which the generation of drift fields is paired, which accelerate the charge transport.

The mode of operation of the charge-coupled arrangement according to FIG. 2 is explained in more detail with reference to FIG. 5, the arrangement being used as a four-phase charge-coupled arrangement. Figure 5-A- shows a pattern of clock voltages as presented on clock lines 12A, 12B, 12C, 12D. The clock voltages have the same pattern for all connections, which is shifted from the pattern for the other connections and moves between a maximum voltage V ₁₁ and a minimum voltage V.

Fig. 5B shows the associated potential profile with respect to the mobile charge carriers (in the present example the electrons) at times t .. to t_. The potential profile is drawn in a generally customary manner in such a way that potential _{wells correspond to energy minima, for the electrons thus a voltage V TT} on the electrode part located above the semiconductor part where the potential well is located.

At time t .. the connections 6a,

6C and ÖD a voltage V ", while the connection 6b has a voltage V. This means that for the electrons there are potential wells under the strip-shaped Resistance between the connections 6C and 6A arise at those points at which the connections 6D are also located. On the other hand, there will be a potential barrier at the points of the connections 6b, whereby the electrons will move

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will concentrate in the aforementioned potential troughs. This is shown in FIG. 5B, where at time t. two Potential wells filled with movable charge 13a »13t» are, while the wells are separated from each other by a potential barrier at the points B.

At the time t, the voltage at the connections 6C has decreased to a value 1/2 (V "+ Y.). This means that in the semiconductor body the potential under the strip-shaped resistor between the connections 6D and 6d (with 6C as a common point) is increased. The increase in potential has the consequence that a current of charge carriers occurs to the right to the part under the resistor between the connections 6D and 6A, whereby the "level" of the movable charge carriers in the potential wells can rise.

During the transport of load carriers in

Conventional arrangements essentially takes place by diffusion, this transport will be accelerated in the arrangement of Fig. 2 to the potential wells under the portions between the on-circuiting 6d and 6A in that voltage differences occur over the strip-shaped resistance between ^the% terminals 6C and 6D that generate drift fields in the semiconductor body that accelerate the transport to the potential wells.

At the instant t "the voltage at the terminals 6C has become equal to V _T , while the voltages are on."

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the other connections have remained unchanged. The bottom of the potential wells is located _{between the connections 6D and 6A, just as at t? F} , but the "wall" between 6C and 6D has become steeper, as a result of which the "level" of the movable charge carriers may have risen even further.

At time tr is the voltage at the connections 6b has become equal to V ", while the connections ÖA

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and 6D still have this voltage V ". Only the connections 6C have a voltage V, so that the same potential profile as at time t .. in the semiconductor body occurs, but then over a distance equal to that between

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two consecutive connections moved, are also the charge packets 13a and 13 ^ over this distance postponed. It should be noted that although at time t. there are no drift fields that would affect the transport of charge - accelerate the parts DA to AB, but that this is only an instantaneous situation and that immediately after tj that The voltage at the points 6D decreases, as a result of which drift fields are generated again, so that the operating speed is not affected. The charge packets shift in the same way at times t_ bis t ~ again over the same distance even further to the right.

The charge-coupled arrangement according to FIG. 2

in the example above using a four-phase clock system can also be controlled using a two-phase or an apparent two-phase clock system will. An example of such a system is shown in FIG. Connections 6A and 6B are now practically identical voltage patterns offered with the Provided that there is no phase difference between the patterns, but only a fixed voltage difference. The same applies to connections 6C and 6d.

Fig. 6a shows this voltage curve, while x ¹ -

end Fig. 6B again shows the potential profile under the strip-shaped resistor as a function of the position at the various times t ₁ to t-.

At time t .. the connections 6D

a higher voltage than any other connection; in other words: the minima of the potential wells are located at the points of these connections. The cargo packages 13a, 13t * are in the areas between the ports 6C and 6a, which are around 6D.

At time t_ the voltage difference between terminals 6C and 6D has remained the same (i.e. a constant difference) while the voltage difference between terminals 6a and 6d has decreased (see Fig. 6a). This means that the inclination of the potential wells on the left side (CD) has remained the same

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and on the right-hand side (DA) it has become less steep J ('uo ( _f, whereby the potential wells have become, as it were, "wider". As a result, the "level" of the mobile charge carriers in the potential wells decreases. At time t " this decrease has continued.

In the time course between the times t ~ and t. becomes the voltage difference between the terminals 6D and 6a become smaller and smaller until this voltage difference is zero at time tr, which means that under the areas a flat potential profile is obtained between the terminals 6D and 6A. Due to the fixed potential between the connections 6A and 6B there are potential minima under the connections OB at tr.

Between the times t 1 and tr, the potential under the connections 6A decreases and at a certain point in time it reaches the "level" of the movable charge. carrier. From this point on, charge transport occurs to the right. In the area between the connections 6A and SB , this transport is accelerated as a result of the drift field generated by the constant voltage difference between the connections 6a and 6B.

Immediately after time tr, there is also such a voltage difference between the connections 6D and 6a that drift fields are generated under the intermediate parts of the strip-shaped resistor, which accelerate the transport to the potential minima under the connections 6B, up to the time t_ the same potential curve as at the time t _{1 is} obtained, but then shifted to the right over a distance equal to twice the distance between two successive terminals 6. The charge packets 13a, 1 3 ^ are thus also transported to the right over this distance.

7 shows a plan view of another embodiment of a charge coupled device which is operated with a three-phase clock system. Transversely to the strip-shaped resistor 5 are again in almost equal intervals terminals 6 (6A, OB, 6C) for offering mode voltages on the T _a ktleitungen 12 attached. the

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clock voltages required to operate this arrangement are shown in Fig. 8A, while the potential pattern paired with these voltages in the semiconductor body to the Times t .. to t_ is shown in Fig. 8B.

At time t ₁ , terminals 6B have a voltage V, while terminals 6A and 6C have a voltage V (FIG. 8A). This means that under the areas delimited by the connections 6A and 6C there are potential minima which are delimited on both sides by potential barriers at the locations of the connections 6B. As a result, potential wells are formed which are filled with charge packets 13a, 13b.

At time t ~ the voltage across the Connections 6C i / 2 (V "+ V). Thereby the potential minima concentrated under the terminals 6A. Between the terminals 6B and 6A are under the strip-shaped resistor As a result of the voltage difference between these connections, drift fields are present that affect the charge transport accelerate to the right. The charge packets in the period between the points in time are due to these drift fields tp and t "shifted to the right so that the charge that still · under the part between the connections 6B and 6C is located at time t "to the potential wells under the connection points 6A, which are from potential barriers under the Connection points 6C (which points then have a voltage V.) andÖB are limited, is transported.

At time tj, the potential profile in the semiconductor body under the strip-shaped resistor is equal to the potential profile at time t .., but shifted to the right over a distance equal to that between two connections. The charge of the charge packets 13a and 13b is again distributed in the same way, so that these charge packets are also shifted to the right over the same distance. In the same way, the charge packets 13a, IJh shift to the right again over such a distance at the times t "to t".

It goes without saying that the invention is not limited to the above examples, but that in

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Many modifications are possible within the scope of the invention for the person skilled in the art.

So can in the embodiments of

Conductivity type of all semiconductor areas and zones (to at the same time) can be replaced by the opposite type.

The connections 6, which in the examples are made of doped polycrystalline silicon, can be any other suitable for wiring purposes Material such as aluminum.

The invention can also be used for charge-coupled arrangements of the so-called "with shallower buried" type Layer "are used, in which under the insulating layer the actual transport channel in the form of a very thin layer (about 0.5 / µm) of semiconductor material from opposite line type is attached.

The strip-shaped resistor can also be used

be covered with an oxide layer in which there are small windows for connections 6.

Instead of the channel breaker 9 can Channel also delimited by thick oxide, possibly in combination with a channel interrupter attached underneath will.

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Claims (1)

26-k-1979 y * ■ PHN 9210 PATENT CLAIMS: 1. J Charge-coupled arrangement with a semiconductor body which has an insulating layer on one surface, on which electrode regions are applied, with the aid of which a potentialnster for storing and transporting of in the underlying part of the semiconductor body
Charge packets can be generated, with means being present by means of which drift fields are generated in the semiconductor body under the electrode areas, characterized in that the electrode areas form an uninterrupted strip-shaped resistance, which in regular
Distances is provided with connections for offering clock voltages, the electrode regions being defined by parts of the strip-shaped resistor between two successive connections, whereby said drift fields are generated in the semiconductor body by applying different voltages to these connections. 2. Charge-coupled arrangement according to claim 1, characterized in that the strip-shaped resistor is practically homogeneous. 3. Charge-coupled device according to claim 1 or 2, characterized in that each pair is consecutive Electrode regions contains a common connection. 030011/0701 26-4-1979 2 'PHN 9210 k. Charge-coupled arrangement according to one of the preceding claims, characterized in that the stx ^ egg-shaped resistor contains polycrystalline silicon. 5. Charge coupled arrangement according to one of the preceding claims, characterized in that the connections for the clock voltages transversely to the strip-shaped Contain resistance running tracks. 6. Charge coupled arrangement according to one of the preceding claims, characterized in that the Array a "surface" charge coupled device is, in which the storage and transport of the charge packets at least substantially at the interface between the insulating layer and the semiconductor material. 030011/0701