DE2923380A1 - ERROR DETECTION CIRCUIT - Google Patents

Description

- 5 patent attorney 2 9 2 O 3 O U

Dipl.-Ing. Dlpl.-Chem. Dipl.-Ing.

E. Prince - Dr. G. Hauser - G. Leiser

Ernsbergerstrasse 19

8 Munich 60

Our sign; D 722

5. Wed J973

DATA GENERAL CORPORATION

Route 9

Westboro, Massachusetts 01581, V.St.A.

Fault detection circuit

The invention relates generally to a data processing arrangement and in particular to a fault detection circuit suitable for use in such an arrangement, in which error detection code generators are used, to determine if there is an error in data words read from a data storage element is.

When reading data words from a data storage device It is desirable for a data processing arrangement to determine whether the data words read are the same data words previously written to the storage device. I.e. it is desirable to have the presence of a or to recognize several incorrect data bits in the data words. Such a data storage device can, for example be a device with a magnetic storage disk on which a serial data bit sequence has been written, which forms a block of data words; these data words

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will then be read from the plate at a later point in time «

In conventional error detection circuits, the data words written on the disk are used for error detection accompanied by an additional error word during the write operation corresponding to a selected Polynomial has been generated from the stored data words. A read error word is generated during read operation corresponding to a polynomial equivalent to the write polynomial from the data words read from the storage device generated. The writing error word, which is then read from the disk, is then compared with the during the Read process generated read error word compared, and if there are no errors in the read data words are, the remainder formed from an error correction code register used for this purpose has the value O. If on the other hand, if an error is present, there is one other than zero in the error correction code register Remainder. Such a remainder that is different from zero can then be detected and supplied to the data processing arrangement to indicate that there are one or more errors. The rest can then be used accordingly interpreted so that the error location is determined according to known methods and error corrections be made.

Usually, such a fault detection circuit requires relatively complicated multiplexing circuits and also complicated polynomial selection and generation circuits using a relatively large number of digital circuit elements require. This complexity not only increases costs the error detection circuit but also degrades its reliability. It is therefore desirable to build the error detection circuit as easy as possible

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design, so (grasp the complexity of the hardware and the cost can be reduced considerably.

According to the invention, an error detection circuit for detecting errors in serial data from a data storage device is greatly simplified by the complicated multiplexing and polynomial generation operations be greatly simplified by using a programmable logic field (PLA), wherein the input variables of this programmable logic field are selected so that desired selected output variables can be generated in a manner that greatly simplifies the hardware of the error detection circuit and the Overall cost of the error detection system can be reduced. By using a programmable logic field not only do the multiplexing and polynomial generation circuits normally required, but also appropriate control options for the read and write operations are created.

The invention will now be explained by way of example with reference to the drawing. Show it:

Fig. 1 is a block diagram of a conventional error detection circuit According to the state of the art,

Fig. 2 and 3 circuit details of the known circuit for generating polynomials as used in the error detection circuit of Fig. 1,

4 shows a block diagram of a preferred embodiment the error detection circuit according to the invention and

5 shows a more detailed block diagram of the inventive Circuit of Fig.4.

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As can be seen from Fig.1, contains a conventional Error detection circuit a shift register 10, an error correction code register 11, multiplexers 12 and 13 and a relatively complicated polynomial selection and polynomial generation unit 14. For example, the circuit of Figure 1 is in the technical manual for the DG / DISC storage subsystem (Series 6O6O, 100 megabytes) by the company Data General Corporation, Southboro, Massachusetts as "Manual No. 015-000061-00 for the Data General Series 6060 products "was released.

When operating such a known error detection circuit, the transmission takes place in a data processing arrangement data to be used usually to this arrangement or from this arrangement in parallel form. The shift register 10 sets the data received from the data processing arrangement for storage in a storage device, for example a magnetic disk storage unit, of a parallel shape in a serial form, or it receives serial data from the storage device and delivers the data in parallel Form to the data processing arrangement. During the write operation, a block of parallel data words, for example from data words with 16 bits, into the shift register 10 is input and the data words are stored in serial form of the storage disk and an error correction code register 11 about the polynomial selection and polynomial diffraction unit 14 supplied. This unit is designed in such a way that the error correction code register 11 is then transferred from the into the Register 11 entered data words that are written to the memory disk, corresponding to a selected one Polynomial delivers an error word, for example a word of 32 bits. Such a polynomial is a preselected polynomial, which is selected on the basis of mathematical methods known for this purpose.

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The error correction code register 11 performs several operations during the write and / or read modes by. During the writing operation explained above, it first generates based on the selected polynomial a write error word written on the disk; this error word is corresponding to a desired interconnection of digital circuit elements using non-equivalence elements generated in are suitably connected with feedback, as will be explained. The error correction code register also operates 11 during the write operation as a shift register, so that the write error word after the data words have been written is written to the disk. The error correction code register generates during the read operation 11 also a read error word from the data words read from the storage disk according to a read polynomial, using a different interconnection of non-equivalence elements in a different feedback circuit will; Finally, the error correction code register 11 functions as a shift register for comparing the writing error word with the read error word to generate a remainder with the value O or a value other than O as Comparison result. The rest then becomes the data processing arrangement supplied together with the data words; if the remainder has a non-zero value this indicates that there is an error.

To enable and disable the non-equivalence elements according to the desired feedback circuit, those for the various modes of operation of the error correction code register extensive logic is used. This combination logic is the cause of increasing delay times between the operating stages of the error correction code register, so that at very high data transmission speeds, which are currently in some cases, for example

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can reach 10 MHz, very fast, energy-consuming circuits are required. aside from that must contain both the original data words and the error word content when writing data to the storage disk of the error correction code register. This process requires a multiplexing process for multiplexing the contents of the shift register 10 and the error correction code register 11. In addition, must when reading data from the storage disk, the contents of the data words and the write error word from the storage disk be read, and a read error word and the rest of a comparison of the error words in the Error correction code registers are generated. This process also requires the use of multiplexing operations under appropriate control.

In Figures 2 and 3 examples of known coupling circuits are shown with non-equivalence elements, which for use with the error correction code register 11 to generate the desired write and read error words appropriately selected polynomials are suitable. A well-known polynomial that occurs in the A specific example of an error correction code register with a capacity of 32 bits can be used the polynomial:

32 23 21 11 2 x ^D * + χ ° + x ^ '+ χ "+ x ^ + 1.

A selected reading polynomial equivalent to the writing polynomial is in the form of two factors; it is the polynomial:

(x ¹¹ + x ² + 1) (x ²¹ +1).

For the conventional fault detection circuit of Fig.1 is the feedback circuit built up with non-equivalence elements

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circuit for each of the polynomials shown in Figures 2 and 3. As can be seen, the structure of the polynomial generation circuit is used for both the write operation as well as a relatively complicated circuit containing exclusive equivalents is required for the read operation. aside from that also becomes a relatively complicated multiplexing circuit needed. The total number of logic elements is therefore relatively high, so that the total energy consumption is correspondingly large. Because of the delay times that occur, it will operate at higher speeds difficult if not using high-speed and energy-consuming circuit elements will. In addition, the construction of the error detection circuit on a program control card for use in a data processing arrangement is complicated, and the total area required on such a card can be larger as desired. A reliability problem arises because of the large number of digital circuit elements required because there are so many circuit elements that can fail.

To overcome these disadvantages, according to the invention the polynomial selection and polynomial generation unit 14 as well as those for the multiplexing processes explained above required logic circuits by a single programmable logic field (PLA) replaced, as in Fig.4 is shown. As can be seen in this figure, there is a transmission of parallel data in both Directions between a data processing arrangement and the series / parallel shift register 10, which is in the essentially corresponds to the type of register shown in FIG. An error correction code register 11, the

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also corresponds to the type of register shown in Fig. 1, is also used. The control of the read and write modes, the generation of the necessary polynomials and the multiplexing of the various processes required for this are accommodated in the programmable logic field 15.

The programmable logic field, which will be explained in more detail below, is designed so that it not only enables the desired multiplexing operations during the various modes of operation, but also generates the desired error words corresponding to the polynomials during the read and write modes of operation. The time control
overall operation is achieved by means of a suitable conventional timing circuit 16.

The structure and operation of the circuit shown in FIG. 1 can be better understood with reference to FIG. As can be seen in this figure, the shift register 10 has corresponding connections for outputting parallel data words of 16 bits to the data processing arrangement or for receiving parallel data words
16 bit data words from the data processing arrangement as indicated by the bits designated as BUS AO through BUS A15. These data bits are transmitted using conventional methods on a corresponding data bus (not shown) in parallel form to or from the data processing arrangement. Serial data is also handled by
this shift register 10 delivered or to this
Shift register supplied, the input terminal SRO at one end of the register being available when

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Data is fed to the shift register input while the output terminal SR15 at the other end for the output of serial Data is available at the register output.

The error correction code register 11 consists of four registers 11A to 11D each having a capacity of eight bits for the output of an error word consisting of 32 bits with the bits ECCO to ECC31; the bits ECCO to ECC7 are included assigned to the register 11A, bits ECC8 to ECC15 assigned to the register 11B, bits ECC15 to ECC23 assigned to register 11C and bits ECC24 through ECC31 are assigned to register 11D. Special .data bits of the Error correction code register needed in the programmable logic array to generate the desired polynomials are in Fig.? with ECC BIT 0, ECC BIT 9, ECC BIT 10, ECC BIT 20, ECC BIT 21, ECC BIT 29, ECC BIT 30 and ECC BIT designated.

The programmable logic array 15 can receive up to 16 input signals on 16 input ports; it can be up to Deliver eight output signals to eight output terminals. Several of the logic fields are also explained below Control signals supplied; a timing circuit 16 is also shown. When using the programmable Logic field 15 according to the invention, the output functions to be generated are selected in a suitable manner; the input signals required to generate these output functions are also processed in a corresponding manner selected along with the required functional relationships desired. These selected functional relationships are programmed in the programmable logic field in a suitable manner.

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Programmable logic fields required for the here Purpose are currently available to the expert. Typical logic fields, as they can be used here, are for example from the company Signetics Corporation of Sunnyvale, California under the designation 82S100 or 82S101. One a general description of such programmable logic fields is, for example, in one from Signatics Corporation in February 1976 published brochure entitled "Signetics Field Programmable Logic Arrays" contain.

In the circuit to be described here, such a programmable logic field can be used to generate the desired Write and read error words according to the selected polynomials and for performing the desired multiplexing operations can be used by delivering the following selected outputs:

1. Entry in ECC BIT 31

2. Entry in ECC BIT 29

3. Entry in ECC BIT 20

4. Entry in ECC BIT 10

5. Entry in ECC BIT 8

6. Serial data to disk

7. Serial data from disk

The first five output signals given above will be on lines 17 to 21 to the corresponding bit storage locations of the error correction code register 11, to the feedback signals corresponding to the polynomials described above in connection with FIGS. 2 and 3 must be created. In everyone else

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Bit storage locations of the error correction code register 11 is simply the content of the next higher Storage space delayed by one clock period.

The sixth output signal given above, which is applied to the Line 22 is supplied, is the serial .Datensignal, to be written to the disk; it is therefore the multiplexed output signal from the serial data words sent by the data processing arrangement for writing to the disk, as well as the error word from the Error correction code register generated during the write operation. These data are used for this purpose synchronized accordingly by the flip-flop circuit 25, the operation of a write clock signal WRCLOCK and from Control signal WRITE GATE is controlled so that it is synchronized Data from WRDATA.

The seventh output on line 23 noted above is the serial data signal received from the disk is received during a reading operation; it is also a matter of the multiplexed combination of the data words from the storage disk and the remainder word obtained after a comparison is made between the write error word and the read error word remains in the error correction code register. This output signal is used by the data processing arrangement fed through the shift register 10, which converts the data from the serial form to the parallel Implements form.

To generate the output signals specified above,

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uses the following inputs according to the invention:

1st edition of ECC BIT 0

2nd edition of ECC BIT 9

3rd edition of ECC BIT 11

4th edition of ECC BIT 21

5th edition of ECC BIT 30

6. SR15 serial output of shift register 10

7. SRO - serial input of shift register 10

8. DATA IN - serial data from the storage disk

9. EN ECC CLK

10. RD ECC

11. SHIFT ECC

The first five input signals given above are ECC bits from the error correction code register 11 which are used to generate the desired write or read error words according to the selected polynomial related to the above with Figures 2 and 3 was explained, are combined.

The sixth and seventh input signals noted above are data input signals to the shift register 10 and out, respectively the shift register 10 for use in performing logic equations in read and write operations, as will be explained in more detail below. The data to be written or read is multiplexed in Form of the logic field as input signals to the error correction code register for generating the error words supplied, supplied as input data to the disk in the case of a write operation, and supplied in the case of a read operation is supplied to the shift register as output data from the storage disk. The output data from the storage disk in the latter case the logic field on line 26 as the signal DATA IN and

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then fed to the shift register 10 from the logic field.

The input signal EN ECC CLK is a control signal that enables the operation of the error correction code register.

The input signals ElEAD ECC and SHIFT ECC are coded control signals for controlling four operating modes, namely a first operating mode in which these input signals the Have values 0.0 to generate the error word during the Write mode, a second mode in which the input signals have the values 1.0, for writing the error word to the magnetic disk during the write operation, a third operating mode, in which the input signals have the values 0.1, for generating the error word during the Read mode and a fourth mode, in which the input signals have the values 1.1, for checking the error correction code register for generating the remainder during reading operation. The control signals can come from a central unit of the data processing system so that they can be used during the read and write modes in one of the Be applied in a manner known to those skilled in the art.

To achieve the desired mode of operation of the programmable logic field for the purpose according to the invention, the the following selected logic equations for the construction of the programmable logic field for generating the desired error words and to achieve the desired multiplexing processes during the write and read modes has been derived. These logical equations are given below as equations (1) through (7); how to can be seen, the seven selected output functions are in a suitable manner with the eleven input variables

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in accordance with the relationships set out here. A a typical programmable logic field of the type indicated above has 16 inputs and 8 outputs, but the application described here only uses 11 inputs and 7 outputs.

Selected logical equations

Input bit 31

Enter bit 29

Input bit 20

= SHIFT ECC -RD ECC -EN ECC · [SR15 Φ ECC θ] + SHlJi ¹ T ilüC-RD ECC-EN ECC '[SRO Θ ECC 21]

= SHlFIP! UCC-RD ECC-EN ECC- [SR15®ECC0 Φ ECC30] + SHIFT ECC-RD ECC-EN ECC- [SRO © ECC30 © ECC2i] + SHIFT ECC-EN ECC-ECC30

= SHIFT KCC 4U) WCC-EN ECC- [SR15 © ECC21®ECC0] + SHIFT ECCΈΝ ECC-ECC21 + SHIFT ECU-RD ECC ΈΝ ECC- [SR 0 9 ECCO]

Input bit 10

Enter bit 8

FTTÜÜ-RTTTüÜU · EN ECC [SRI 5 9 ECC11 Φ ECCO] + SHIFT ECC-EN ECC'ECCH +

SHIFT ECC-RD ECC-EN ECC'ECCH

5ΤΠΡΤ ~ Εϋϋ'ΐΠΓΈΌΤΤ ΈΝ ECC * [SR15 $ ECC9 © ECCO] + SHIFT ECC -EN ECC'ECC9 +

SHIFT ECC'RD ECC-EN ECC-ECC9

Serial data output = SHIFT ECC »RD ECC -EN ECC-ECCO +

EN ECC ^ SRI 5 +

SHIFT ECC-RD ECCEN ECC-SR15

Serial data entry = SHIFT ECC-RD ECCEN ECC-ECCO +

ENECC- DATA IN +

3HIFT ECC -RD ECC -EN ECC -DATA IN

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The above logical equations are derived from the specially selected polynomials taken as an example, which have been explained above. As an example of such derivations, consider the logical equation (1), which reads as follows:

Input bit 31 = t> iili? "T JiCU« tüJ JiUU-EN ECC- [SR15 © ECC O] +

SHIFT ECC-RD ECC-EN ECC- [SRO © ECC 2iJ

During the generation of the error word according to the

32 23 21 11 2 write polynomial χ + χ + χ + χ + χ +1 »is the input signal at bit 31, as can be seen from a reference to the feedback circuit of FIG Data input from register 10 to the storage disk (SR15) and the O bit from the error correction code register (ECCO). During this write operation, the error correction code register must be enabled (EN ECC), and the coded control signals discussed above (at inputs 10 and 11) must be in such a coded form that an error word can be generated during the write operation (SHIFT ECC 'RD ECC ) , which means that the code group (0,0) must be present.

During the generation of the error word in read mode

11 P ? 1 corresponding to the reading polynomial (x + x + 1) (x +1) results in the input signal at bit 31 ♦ as can be seen with reference to the feedback circuit of FIG the serial data (SRO) entered into register 10 from the memory disk, the data being fed from the DATA IN input to the logic field and then to line 23, as well as from bit 21

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the error correction code register (ECC21). Also must during the read operation the error correction code register must be enabled as before, (EN ECC), and the encoded Control signals must be in such a coded form that the generation of an error word during the Read operation is enabled (SHIFT ECC · RD ECC), which means that the code group (0, 1) must be present. the other logical equations are derived in a similar manner.

These logic equations (1) to (7) can be derived from the programmable logic field according to known methods can be realized, for example in the brochure from Signatics Corporation given above is carried out when the logical equations with the selected input and output quantities and the selected Relationships between these quantities have been established.

Further control signals for the shift register (SR) and the error correction code register (ECC) are given in FIG. these control signals SR MODE SEL 1, SR EN OUT, DIORESET, SR CLOCK and CLEAR ECC can be used in a known manner in the Central unit of the data processing arrangement can be generated, as can be recognized by a person skilled in the art.

During the write operation, parallel data \ - / words fed to the shift register 10, whereupon they are in serial Form from serial output SR15 to programmable logic field to get redirected. The data words then appear on output line 22 to the synchronization device (i.e. to achieve synchronization with the clock signal V / R CLOCK generated by the timing control unit 16)

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transmitted as data signal WR DATA for feeding to the disk. The data words are also fed to the input of bit 31 of the error correction code register 11 on line 17, so that they are used to generate the desired write error word in accordance with the selected polynomial. The write error word is then transmitted from the terminal of the bit O of Fehlerkorrekturcodereg i sters 11 on the line to the logic array 15 so that it .If (also with appropriate synchronization) transmitted as part of the data WR -DATA on the line to the magnetic plate ₄ on the disk that is, the data words coming from the data processing arrangement and the writing error word generated by the error detection circuit are written.

During the read operation, the data words and the write error word are transferred from the storage disk to the connector DATA IN of the programmable logic field 15 is applied, whereupon the data words in serial form on the line 23 the connection for the bit 0 of the shift register 10 are supplied. -These data words are then used by the data processing arrangement supplied in parallel form. The data words are also on line 17 to the error correction code register 11 so that they can be used to generate a read error word. The typographical word is then applied to the error correction code register in which the read error word is generated has been; if the write error word and the read error word match, i.e. if those from the storage disk read data words are the same as were written, i.e. there is no error, is in the error correction code register a remainder word with the value 0 is present. On the other hand, if there is an error in the read

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If data is available, there is a residual word in the error correction code register with a word other than 0 Value which is then transferred on line 27 to the logic field and then on line 23 to the shift register so that it is delivered to the data processing arrangement and indicates that one or more errors available; the remainder of the word is interpreted accordingly so that the errors that have occurred are identified and corrected.

Performing the above-mentioned logical equations with the selected input variables to generate of the desired selected output variable in the programmable logic field according to the invention compared to known systems to a strong reduction in the total number of digital circuit elements, which are required for error detection; this results compared to the prior art the desired advantages in terms of increased operating speed, lower energy consumption, improved reliability and reduced cost.

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Claims (8)

Patent attorneys D 722 Dipl.-Ing.
G. Quieter 2923380 Dipl.-Ing.
E. Prince Dipl.-Chem.
Dr. G. Hauser Ernsbergetstrasse 19 8 Munich 60 Sign: June 5, 1979 DATA GENERAL CORPORATION Route 9 Westboro, Massachusetts 01581 V.St.A. Claims / 1J Error detection circuit for a data processing arrangement with a data storage device characterized by a first register device which is adapted to store the data words can receive and output in parallel form as well as data words in serial form can receive and output in parallel form, an error register device which is adapted to Receives data words in serial form and generates an error word as a function thereof, and a programmable one Logic field programmed to perform the following operations: (1) During a write operation, it controls the supply of the serial data words from the first register device to the data storage device and to the error register device, the error register device thereby generating a writing error word; (2) during the write operation, it controls the supply of the write error word from the error register device the data storage device in which the data words are stored; (3) during a reading operation it controls the supply of Da ^ · - words from the data storage device into the first Schw / Ba 909882/0688 Register device and into the error register device, the error register device thereby a read error word generated; (4) during the read operation it controls the feeding of the write error word from the data storage device to the Error register device, if in this the read error word has been generated, wherein the error register device thereby generates a remainder word; (5) during the reading operation it controls the supply of the. Remainder word to the first register device. 2. Fault detection circuit according to claim 1, characterized in that that the data storage device is a magnetic disk storage unit. 3. Fault detection circuit according to claim 2, characterized in that that the programmable logic field has a first selected number of input variables, the following Input variables contain: multiple bits from the error register device, serial data words from the first register device for supply to the magnetic disk storage unit, serial data words from the magnetic disk storage unit for supply to the first register device, a control signal for controlling the enabling of the error register device and Coded control signals for controlling the generation of the write and read words during the write and read operation, for Control of the supply of the write error word to the magnetic disk storage unit and for the control of the supply 909882/0688 of the remainder of the word to the first register device. 4. Fault detection circuit according to claim 3, characterized in that that the programmable logic field is programmed so that it the write error word corresponding to a first outputs selected polynomial determined by a first selected number of bits from the error register device and that it is the read error word corresponding to a second selected polynomial generated by a second selected number of bits from the error register device is determined, the second polynomial being equivalent to the first polynomial. 5. Fault detection circuit according to claim 4, characterized in that that the first selected polynomial is the polynomial 32 23 21 11 2
χ + x ^ + χ + x + χ + 1 and that the second selected polynomial is the polynomial (x + x + i) (x +1). 6. Fault detection circuit according to claim 5, characterized in that that the error register device is a 32-bit register, and that the first selected number of several bits from the error register device are bits 0, 9, 11, 21 and 30 and that the second selected number of the bits from the error register device are bits 8, 10, 20, 29 and 31. 7. Error detection circuit for use in a data processing arrangement, characterized by a Apparatus for generating write and read error words in response to data words during the write operation or the reading mode and for comparing the write and read error words to generate residual words and a programmable logic field that is used to generate the read and write error words and for Control of the generation of residual words according to that 9 09882/0688 Comparison is programmed. 8. Fault detection circuit according to claim 7, characterized in that that the programmable logic field to control the generation of the write and read error words accordingly selected polynomials is programmed. 9 · Error detection circuit according to claim 7 or 8, characterized in that the programmable logic field for
Control of the generation of the write and read error words and the generation of the residual words is programmed in a multiplexed manner. 909882/0688