DE2909822C2 - Data encoder with write precompensation and MFM algorithm - Google Patents

Description

The invention relates to an arrangement for converting an incoming sequence of serial data into an output-side sequence of serial data with coding in modified phase modulation and write precompensation.

When recorded on a high density magnetic recording medium such as tape, disk, Floppy disk or the like, recorded in a digital format it must be encoded in such a way that it can be reliably read out again. to Numerous well-known coding methods have been developed for this purpose. One of the most effective Use method! the modified phase modulation, also known by the abbreviation MFM. This process is referred to below as MFM coding. The MFM coding is usually performed using various logical random number generators.

When digital information is recorded on a magnetic disk, a bit shift can also occur occur when the recorded reversals of the magnetic flux direction from denser to move less dense areas of the track. This movement is apparent, not real. In reality it is a time lag caused by the properties of the magnetic recording medium will.

A process has been developed which is known as Schrelb precompensation. This The process acts to shift the data bits in time during the reading process by means of an identical but opposite method directional shift of the data bits during the write process. This write pre-compensation is usually done using analog or digital delay lines.

In contrast, the object of the present invention is, in an arrangement of the initially mentioned type a simultaneous implementation of the MFM coding and the write precompensation Significantly reduced expenditure on electronic components while dispensing with analog or digital delay lines to enable.

The object is achieved according to the invention by the characterizing features of the claim.

Advantageous developments of the arrangement according to the invention according to claim 1 emerge from the Claims 2 to 6.

In the arrangement according to the invention are the coded data information according to the algorithms for MFM coding and write precompensation stored in a read-only pocket (ROM). To determine the respective output data of the coding circuit the bit to be coded, the two previously coded bits and the next bit to be coded are checked. This is done with the help of a series-parallel shift register. The four output lines of the shift register are used to address the respective memory locations in the ROM in which the appropriately coded Data information is stored. The coded data can also be transmitted via the fifth address line additional Schrelb precompensation if a write precompensation is required.

The data bits stored in the ROM are set each made up of eight identical tent sections. Four of these sections stand for a logical one and four for a logical zero. Which of the four sections

4 "> carries the relevant data bit in each case, is replaced by the Algorithm for write precompensation determined. The eight time periods are saved from memory in read out in parallel form and converted back into a serial bit sequence.

The main advantage of the present invention is therefore in a simple and new circuit for Conversion of a serial bit sequence into a serial bit sequence with MFM coding and write precompensation.

The invention is explained in more detail with reference to the drawings; show it:

1 shows a block diagram of a preferred embodiment of the arrangement according to the invention
Fig. 2 shows the different time segments of an encoded data bit and

Fig. 3 timing diagrams for the signal curve at various Places within the block diagram according to I-ig. 1 to understand how it works do.

In Fig. 1, a preferred embodiment is the present invention illustrated. A 4-blt-Serlen-Parailel-Schlebereregister 2, a 256-bit-Read-only-Schercher are shown (ROM) 4, an 8-blt-Paraliel-Serlen-

Shift register 6 and two D flip-flops 8 and 10. The circuit receives the input to be coded at input 12 serial bit sequence is supplied and emits the coded bit sequence at output 22.

The present invention converts each bit of the input digital information into an MFM coding. The MFM coding is carried out in the following generally known manner:
An output pulse is generated for each input-side bit that represents a logical one; on the other hand, an output pulse is only generated for an input bit that represents a logic zero if the previous input bit was also zero.

Each time segment 50 for a coded output-side bit is, as shown in FIG. 2, in two half-bit intervals 52 and 54 split. A pulse in the half-bit interval 52 represents an output-side bit with a logical One and a pulse in the half-bit interval 54 on the output side Bit with a logical zero.

The present invention also divides each half-bit interval into four equal time slots 56 of each 250 nanosecond duration divided. In this way, there is the entire time range for a coded Bit on the output side from eight time segments of 250 nanoseconds each. These eight periods will be assigned according to the coding for the write precompensation. If the bit pulse for a logical one or a logic zero is placed in the period designated NORMAL, is for the coded bit no write precompensation before. Becomes the impulse on the other hand, if it is placed in the time segment marked -250, the precompensation for the coded bit is -250 nanoseconds. That is, this bit occurs 250 nanoseconds earlier than a normally encoded bit, that represents the same information. If the pulse is placed in the section of the tent marked + 250, the coded bit is precompensated by +250 nanoseconds or delayed by 250 nanoseconds.

To determine whether write precompensation is required on the inner tracks of a magnetic disk, <»o it is necessary to select the bit to be coded, the two previous coded bits and the next to be coded Bit to check. This is necessary because, as is well known, only certain bit combinations are one Require precompensation if they are recorded on the inner tracks. Below are the bit patterns which require pre-compensation, each with the amount required for pre-compensation listed.

Bit pattern
DCBA

Amount for compensation

0 0 0 1 - 250 nanoseconds 0 J 1 0 -250 nanoseconds 1 1 1 0 -250 nanoseconds 0 0 1 1 + 250 nanoseconds 1 0 1 1 + 250 nanoseconds 1 0 0 0 + 250 nanoseconds

50

55

60

where: Bit A is the next bit to be coded:
Bit B the bit to be coded; and
Bits C and D are the two previous encoded bits.

The mode of operation of the present invention can best be illustrated with the aid of the block diagram of FIG and the associated timing diagram of FIG. 3.

The 4-bit series parallel shift register 2 receives a serial bit sequence, shown as signal A in the timing diagram, supplied via the input terminal 12 and converts this in 4-bit parallel words.

The input terminal 12 is connected to the serial data input of the shift register 2 for this purpose. The shift register 2 can suitably consist of the commercially available shift register 74 LS 164. The serially applied bits are shifted through the shift register 2 by means of the clock signal, which is shown as signal B in the timing diagram and is fed to the clock input via the input terminal 14. A common frequency for this clock signal is 500 kHz. The clock signal B is also connected to the clock input of the flip-flop 8. Each zero / one transition of the clock signal shifts the input bits one place to the right. The outputs of the individual stages of the shift register 2 are all available. Output Q _B , signal F in the timing diagram, represents the bits to be coded. Output Q _A , signal t in the timing diagram, represents the next bit to be encoded and the outputs Q _c and Q _D , signals G and H in the timing diagram, represent the two previous coded bits.

The outputs Q _A , Q ₈ , Or and Q _{D of} the shift register 2 are connected to the ROM 4 _{via the address lines A 0} , A ₁ , A ₂ and A _3. In this way, the outputs of the shift register 2 address the content of the ROM 4. An external control signal for switching the write precompensation algorithm on and off is fed via the input terminal 16 and is connected to the fifth address input A _{4 of} the ROM 4.

ROM 4 is a 256-bit read-only memory that is organized in 32 words of 8 bits each. ROM 4 can suitably consist of a commercially available ROM 74 S 288. The bit patterns which correspond to the MFM-coded and write-precompensated equivalents of the input-side serial data bits are stored in the ROM 4. ROM 4 is used to generate a corresponding data word on the output side for each data word on the input side. The data word on the input side, generated as an address by the shift register 2, is decoded by the internal circuit of the ROM 4; the corresponding output data word is available on the output lines B ₀ to B ₇ , signal I in the timing diagram. The input data words and the corresponding output data words for the thirty-two memory locations of the ROM 4 are listed in the following table:

address catchy .A; , A ₂ .A ₁ A ₀ output side B ₆ B ₅ B ₄ B ₃ B 0 5, B ₀ • 0 Data word 0 0 0 0 Data word 0 1 0 0 0 0 0 A, 0 0 0 1 B ₇ 1 0 0 0 0 0 0 O 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 3 0 0 1 0 1 0 0 0 0 0 1 0 0 4th 0 0 1 1 0 0 0 0 0 0 0 0 0 5 0 0 1 1 1 0 0 0 0 0 0 1 0 ti 0 1 0 0 0 0 0 0 1 0 0 0 0 7th 0 1 0 0 1 0 0 1 0 0 0 8th 0 0 9 0 0

continuation

address

entry point
Data word

A ₄ A ₃ A ₂ A, A ₀

output
Data word
B7 B ₆ B ₅ B ₄ B3 B ₂ Β;

10 ( ) ( 0 1 0 0 0 0 0 0 0 1 0 11 ( ) ( 0 1 1 0 0 0 0 0 0 0 1 12 ( ) ( 1 0 0 0 0 0 0 0 0 0 0 13 ( ) ( 1 0 1 0 0 0 0 0 0 0 0 14 ( ) ( 1 1 0 0 0 0 0 0 1 0 0 15 ( ) { 1 1 1 0 0 0 0 0 0 1 0 16 ( ) 0 0 0 0 0 1 0 0 0 0 0 17th ( ) 0 0 1 0 0 1 0 0 0 0 0 18th ) 0 1 0 0 0 0 0 0 0 1 0 19th ) 0 1 1 0 0 0 0 0 0 1 0 20th ) 1 0 0 0 0 0 0 0 0 0 0 21 ) 1 0 1 0 0 0 0 0 0 0 0 22nd ) 1 1 0 0 0 0 0 0 0 1 0 23 ) 1 1 1 0 0 0 0 0 0 1 0 24 0 0 0 0 0 1 0 0 0 0 0 25th 0 0 1 0 0 1 0 0 0 0 0 26th 0 1 0 0 0 0 0 0 0 1 0 27 0 1 1 0 0 0 0 0 0 1 0 28 1 0 0 0 0 0 0 0 0 0 0 29 1 0 1 0 0 0 0 0 0 0 0 30th 1 1 0 0 0 0 0 0 0 1 0 31 1 1 1 0 0 0 0 0 0 1 0

For addresses 0 to 15, the bit combinations for the output data word correspond to the algorithms for MFM coding with write precompensation, while the bit combinations for addresses 16 to 31 only contain the algorithm for M FM coding. As can be seen from the table above, the additional write precompensation can be achieved by applying a logic zero signal to the address line A ₄ .

The parallel-series shift register 6 receives the coded 8-bit words on the output side from the outputs B ₀ to B _{7 of} the ROM 4 in parallel form to its inputs A to H. The shift register 6, for which a commercially available shift register 74 LS166 can be used, converts the parallel data into a serial data sequence. The shift register 6 is clocked by the shift / load signal, shown as signal C in the timing diagram, which is fed to the clock input via the input line 18. The frequency of the clock signal corresponds to eight times the data clock. The shift / load signal is fed to the clock input of the flip-flop 10 at the same time. The D-FlIp-Flops 8 and 10 control the transfer of the data to the shift register 6.

As already mentioned, the flip-flop 10 is activated by the signal Shift / load clocked, while flip-flop 8 is clocked by the data clock. Logical one level at the D input of the flip-flop 8 is in each case for a zero / one transition transmitted to its Q output. The Q output of the flip-flop 8 is with the D input of the FlIp-Fiüps 10 connected. The respective complement of the logic level at the D input of the Fllp-Flop 10 is for a zero / one transition of the shift / load signal

jo transferred to its Q output. This Q output is connected to the “delete” input of the fllp-flop 8 and the “shift / load” input of the shift register 6. The shift / load control signal resulting at output 20 is shown as signal D in the diagram. This control signal consists of negative-going impulses with the duration of the impulses for pushing / loading and the repetition rate of the data clock.

The shift / load control signal is fed to the shift / load input of the shift register 6. If this signal has the level for logic zero, the _{8-blt word appearing at the outputs B 0} to B _{7 is} transferred to the shift register 6 at the next zero / one transition in the shift / load signal. If this control signal for pushing / loading on the other hand the

α corresponds to level for logic one, the parallel inputs A to H are blocked and the content of the shift register 6 is shifted one place to the right with each zero / one transition of the shift / load signal. The result is the serial data sequence with the desired coding at output 22. This encoded serial data sequence is shown as signals J and K in the timing diagram. This results in signal K for the same serial input bits as signal J, but signal K also has write precompensation.

Of course, only one preferred embodiment of the invention has been described above and shown.

For this purpose 2 sheets of drawings

Claims (6)

Patent claims: 1. Arrangement for converting an input Sequence of serial data in a starting position Sequence of serial data with coding in modified phase modulation and write precompensation. characterized in that serial input data bits in a serial-parallel converter (2) in parallel addresses for addressing one according to the modified phase modulation and the write precompensation coding programmed addressable memory (4) containing at least 8-bit data words can be converted from the memory read out, parallel write precompensated at least 8-bit data words in the modified phase modulation code in a parallel-series converter (6) in a series output signal with modified Phase modulation code and write precompensation can be implemented and that a sequence control connected to the output of the parallel-serial converter (6) connected, the transfer of the addresses of the addressable bit words from the memory circuit (4) to the serial-parallel converter (6) controls. 2. Arrangement according to claim 1, characterized in that that the memory circuit has a read-only memory. 3. Anoidnung according to claim 1, characterized in that that the input-side conversion of serial signals into parallel signals in a serial input and parallel output slider (2) takes place. 4. Arrangement according to claim 1, characterized in that the output side conversion of Parallel to serial signals in a parallel input and serial output drag controller (6). 5. Arrangement according to claim 1, characterized in that the transmission control by D-Fllp-Flops (8, 10) takes place. 6. Arrangement according to claim 1, characterized in that further a device for supplying and disabling of the write precompensation coding is provided.