DE2855730A1 - DATA PROCESSING SYSTEM - Google Patents

Description

DIPL-INCHEINZBARDEHLE Munich. 22. EET. 1978

DIPL. CHEM. DR.PETER FÜRNISE 2 8 B 5 7 3

PATENT LAWYERS

File reference: Our reference: P 2808

Applicant: Honeywell Information Systems Inc. 200 Smith Street
Waltham, Mass., USA

Data processing system

909828/0726

Office: Herrnstrasse 15, Munich

DIPL. ING. HEINZ BARDEHLE Münohen,

DIPL. CHEM. DR.PETER FORNISS 28 5 5730 PATENT LAWYERS

/ fO

File reference: Our reference: P 2808

Applicant:

-ys-

description

The invention relates generally to minicomputer systems and more particularly to testing and checking storage hierarchies using a high speed, low capacity Storage device, the low-speed, high-capacity storage device connected is.

Data processing systems variously have a high speed buffer memory or a so-called one Cache memory between a central processing unit (CPU) and a main memory. The central unit requests displays information from the cache memory during normal operation. If the information is not in the cache is stored, it is requested from the main memory. The system task is to create a high proportion of the information requested by the central processing unit in the high-speed cache to find memory instead of the main memory operating at a lower speed. this leads to an overall increased system performance.

Since the cache is usually for the software becomes invisible during normal operation, many glitches in the cache memory will not show up as System errors show because the information is being obtained from main memory when the cache is not responds to the central unit request. The system is therefore not working with its throughput.

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Office: Hermstrasse 15, Munich 22

In the previously known systems, software diagnostics are used to check the cache memory. These diagnoses write known data to the cache memory under the control of the central processing unit on, and then the cache memory is read out while checking the data with the aid of the central unit. Unfortunately, however, cache memory glitches lead to information is read from the main memory. To overcome this difficulty, careful considerations are required Diagnoses are written to transfer information from main memory to cache memory to the cache memory to switch off and to put different information in the corresponding section of the main memory rewrite, after which the cache is read and the read content is then matched with the original Information from the main memory is compared. The disadvantages of well thought-out software diagnostic procedures are overcome by the arrangement according to the invention.

US Pat. No. 3,840,862 discloses a status display arrangement known for label directories in associative memories. U.S. Patent 3,845,474 discloses a cache flush operation known for multiprocessor operation. In both cases, full / empty or valid bits are used to distinguish valid information from invalid information in the cache memory.

In addition to eliminating the requirement for full / empty or Validity bits and the associated circuit arrangement are described in more detail below by means of the Invention improves the test and diagnostic properties of the cache memory system.

The invention is accordingly based on the object of providing an improved test and verification operation of the cache memory

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systems.

In addition, an improved cache memory system is to be implemented in which the cache memory and the main memory have the same information in the same address storage locations that are specified by the same address bis configurations.

In addition, the cache system is intended to be initiated without the use of full / empty bits or valid bits can be.

The object indicated above is achieved by the invention specified in the patent claims.

According to the present invention, there is provided a data processing system that includes a system bus line contains, to which an addressable main memory is connected, the a plurality of sets of word storage locations each of which is determined by an address, with a number of the word storage locations stores a variety of test and verification commands. This data processing system is characterized in that a central unit is connected to the system bus line is the requirements for the main memory with regard to reading out test and verification commands and data for the delivery to the system bus line that with the system bus line and the central unit a cache memory is connected, which has a data buffer with a plurality of sets of word storage locations which are in a plurality of sets of word storage locations determined by the address for storing the data and contains a directory with a plurality of word storage locations, the number of which are the number of the records in the data buffer, each word storage location of the relevant directory being one

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Address of a corresponding word of the sentence stored in the data buffer that the cache memory further includes means that is responsive to the occurrence of the test and verification commands and one of the operating mode control devices connected to the system bus line and an error device which emits a report signal if there is no match which is connected to the system bus line and the operating mode control device, and that the central unit upon the occurrence of a first command of the test and test commands a plurality of generated by signals for transmission to the system bus line, wherein the operating mode control device is based on the Occurrence of one of the signals concerned comes into operation in such a way that one is used for a test and verification operation characterizing certain state is switched on, with a signal if there is no match emitting error device by the relevant signals is controlled such that it generates an output signal which provides an indication of whether the Data as a result of a .Cache memory request from the Central unit are stored in the relevant data buffer.

The invention also provides a data processing system with a system bus line on which an addressable main memory is connected which has a multiplicity of sets of word memory locations, each record of which is defined by an address. This data processing system is characterized by this from the fact that a central unit is connected to the system bus line, that to the system bus line a cache memory is also connected, which has a data buffer with a large number of word storage locations, those in a variety of by the address in question

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designated sets of word storage locations are arranged, and a directory with a plurality of word storage locations the number of which corresponds to the number of sets of word storage locations in the data buffer, where each word storage location of the relevant directory an address of a corresponding word of the words of the sentence stored in the data buffer that the cache memory further stores a mode control means that is connected to the system bus line and that of this system bus line forth receives an initiation signal by which an initialization operation is determined that with the operating mode control device is connected to a memory request device, which in the case a Sequence of main memory requests generated that they are generated accordingly by the operating mode control device causes an address generating device to be provided which is contained in the requests Main memory addresses generated and those with the system bus line and the main memory request device is connected that the address generating device is controlled by the relevant requesting device a specific sequence of addresses contained within corresponding sequences of requests, to the system bus line, and that from the main memory to the delivery of the relevant requests information is read out to the system bus line from those word memory locations that have the relevant sequences of addresses correspond, with the relevant information in the data buffer and written in said directory with the cache memory being brought into a known state will.

According to the invention is also a method for initializing a data processing system

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created, which contains a system bus line to which a main memory is connected, the specific Number of introductory values is stored in successive memory locations, with the relevant System bus line connected to a cache memory which is a mode control means, the memory requesting means, and the address generating means the operating mode controller being connected to the system bus line wherein the main memory request means is connected to the mode control means and wherein the address generation device is coupled to the system bus line and the memory request device is. According to the invention, this method is characterized in that

a) that an initialization signal is generated on the system bus line,

b) that the address generating device responds to the occurrence of the relevant initialization signal is set to a specific memory request address,

c) that the operating mode control means for the occurrence of the initialization signal is set or switched on in a certain state will,

d) that on the setting of the main memory requirement device by the relevant operating mode control device in the specific state towards a first Main memory request is generated,

e) that the particular memory request address in question is transmitted as part of the main memory request via the system bus line to said main memory,

f) that a sequence of main memory addresses and requests generated by the address generation device or main memory request device

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g) that the addresses as part of the main memory requirements on appropriate control are transmitted by the main memory request device,

h) that depending on each of the relevant requirements and addresses to the system bus line one of the introductory values is issued, which is derived from one of the by a corresponding address The memory location of the main memory designated for the relevant addresses is read out,

i) and that each introductory value is converted into a corresponding one Storage space of the cache memory with transfer of the relevant cache memory into one known state is enrolled.

In the preferred embodiment, the test and verify (T and V) operations are two types of Central processor instructions used. These commands are stored in the main memory to the desired Cache memory test and cache memory test follow to execute.

The first type of instruction, the so-called Copy A for the Register (CAR) instruction, results in the creation of five types of instructions defining the hardware properties of the invention. The second type of instruction, the copy register for the A (CRA) instruction, results in the creation of two types of instructions that use the cache hardware properties the invention can be exploited.

The CAR instruction produces the following five Types of test and verification commands:

The Jmaylong cache instruction causes the cache to to indicate to the central unit that its

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Read requests directly to main memory are directed. The cache memory facility also does not update the cache memory, i.e., a cache directory and a cache data buffer.

The cache device is in the test and Test operation brought into a by-pass or detour state, when the central unit commands are transferred from the main memory to the central unit. the The cache memory device is also brought into the bypass state when the central processing unit is out of the Cache receives an error indication that a match has not been found. This is ensures that the cache memory device retains its information while the central processing unit keeps one carries out further diagnostic measures.

The reset bypass cache instruction will causes the cache memory device to indicate to the central processing unit that it has read requests for Accepts data from the central processing unit and that it will update the directory and the data buffer. The cache device goes into the reset bypass cache mode brought to accept data from main memory.

The initial cache instruction renders the cache full of data from consecutive Word memory locations loaded into the word memory, starting with a certain word memory location of the main memory. This command differs from the quality link test that is still being written (QLT) operation in that the cache memory device is in a bypass or detour

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is in state when the initialization cache instruction completes. This enables the requirement further instructions from the central processing unit, directly from the main memory, without going into the cache memory is enrolled. The central unit uses the initialization or initiation command in the no match indicating error operation to the directory and its associated circuitry to test.

Defining or setting the error command indicating no match or no hit causes the Cache memory device to send a signal to the central unit when the central unit requires them Data of the cache memory device are not stored in the relevant cache memory device. This signal causes the central processing unit to carry out the diagnostic measure as mentioned above. The cache memory immediately sets or transfers itself to bypass mode.

The resetting of the error command which does not indicate a match is processed by the central processing unit ^ when the unmatched error operation has ended. Also be Signals sent from the central processing unit to the cache memory to indicate the disagreement Reset faulty operation.

As part of the initiation or initialization procedure, the cache device is put into the quality link test (QLT) operation brought. In this operating mode, the cache memory is made up of 4096 address memory locations low priority of the main memory loaded via the system bus line. This is achieved by that the initialization signal CLEAR from the cache memory

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is recorded. The CLEAR signal then causes if it goes low, setting the logic device of the cache memory system in an initialization state. When the CLEAR signal rises, a QLT flip-flop is set. That Setting the QLT flip-flop results in the cache system for issuing a request from the main memory for the data word in the address memory location 0000. The cache memory then makes another request for the main memory, namely after the data word under the address memory location 0001.

The cache facility handles the request for the Main memory by the first request of a system bus line cycle. If the system bus line for the cache memory is available, it sends a memory request over the bus line. Of the Main memory receives the request and sends an acknowledgment signal over the system bus line, if the memory request is in the correct format.

After the second main memory request by the cache memory, the main memory sends over the system bus line the requested two data words back over two bus cycles. The cache then takes action two further requests for the data words in the address storage locations 0002 and 0003 of the main memory. The main memory sends the two requested words back to the memory. This process is repeated until 4096 words from the cache are included, after which the QLT operation is terminated by resetting the QLT flip-flop.

Also to ensure that the cache the same data as the main memory will contain

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the QLT function also in the test and diagnostic mode used. In this test and diagnostic mode, the cache memory is taken from the main memory in QLT mode loaded. The central processing unit then requests successive data word storage locations in the cache memory that should be stored in the cache. If any of these address storage locations is not present in the cache memory, a signal is sent back to the central processing unit.

The invention is explained in more detail below with reference to drawings, for example.

1 shows the overall system in a block diagram. Fig. 2 shows in block diagram a cache memory system.

Fig. 3 'shows a logic circuit diagram a clock control and a FIFO read / write control. Fig. 4 shows in a logic diagram an AOR and RAF control and an RAF write address counter and an RAF read address multiplexer. 5 shows a logic circuit diagram of a cycle control and a system bus power controller. Fig. 6 illustrates in a link diagram a circulation operation.

7 is a timing diagram illustrating a quality link test operation. Fig. 8 shows system bus line formats. Figure 9 is a flow diagram illustrating the quality link test operation. Fig. 10 shows in a circuit diagram a test and test logic.

Fig. 11 is a flow chart illustrating the test and verification operation.

Fig. 12 illustrates in a timing diagram the test and verification operation.

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Fig. 1 shows in a block diagram a mini-computer system, which a central unit CGPU) 2, a Main memory 3, an input / output multiplexer (IOM) 7, a system bus line 5, a cache directory and a data buffer (cache memory) 1 and a system support channel 8 on v / eist. the normal execution of the standard peripheral devices connected to the system via system support channel 8 are not shown. Except for system support channel 8, every unit is connected to the system bus line 5 via an interface signal bus line 4. The system support channel 8 is connected to the input / output multiplexer 7 via an input / output bus line 9. About that In addition, the central processing unit 2 and the cache memory are connected via a private bit position signal bus line 6. The input / output multiplexer 7, the input / output bus line 9 and the system support channel 8 do not belong to the actual invention, which is why they are not described in more detail.

The central unit 2 is for use as a communications network processor designed; it is a firmware-controlled binary system with 20 bits per word. Of the Main memory 3 can be used by the system in modules of 32,768 words up to a maximum of eight modules or 262,144 words to be added. The main memory 3 consists of MOS memory chips with random access, wherein 4096 bits are stored in each chip. The main memory in question has a read / write cycle time from 550 ns. The cache memory 1 is a high-speed cache memory with a maximum read / write cycle duration of 240 ns. The central unit 2 requests a data word from the cache

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memory 1 via the private interface 6 and receives the data word, if it is contained in the cache memory 1, in 110 ns via the private interface bus line 6. If the requested data are not contained in the cache memory 1, the central unit 2 receives the data via the main memory 3, the bus line 51, the cache memory 1 and the bus line 6 in 960 ns. If cache memory 1 were not present in the system, then the read access time from central processing unit 2 to main memory 3 would be 830 nanoseconds. By using the prefetching method according to the invention it is ensured that in most cases over 9096 of the requested data words are stored in the cache memory 1, whereby the throughput of the system using the cache memory 1 is considerably increased compared to a system without a cache memory 1. The system bus line 5 enables two units on the bus line to exchange data with one another. In order to carry out a corresponding message transmission, a unit must request a bus line 5 cycle. If the bus line 5 cycle is granted, then that unit can address any other unit connected to the bus line 5. The input / output bus line 9 agrees with the system bus line 5 in terms of performance and in terms of signal design. The input / output multiplexer 7 controls the flow of data between the bus line 5 and the various "data transmissions and peripheral control devices of the system via the input / output bus line 9. The system support channel 8 represents a micro-programmed peripheral control unit which controls various devices ( not shown) performs. Other control units (can not) also represented at the input / output bus line 9 reasonable \ joined his.

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The central unit 2 updates the data in the main memory 3 by including the data word its memory address relating to the main memory 3 and the control output signals in question sends out via bus line 5. The cache memory 1 is in view of the fact that it has the entire over the Bus line 5 reads incoming information into a register, updates if the data word is in a corresponding one Memory space of cache memory 1 is saved. This ensures that the Information stored in the relevant address memory location of cache memory 1 is the same information, as it is stored in the corresponding address memory location of the main memory 3.

The central processing unit 2 requests data from the cache memory by supplying the required address (PRA) the private interface 6 sends out to the cache memory 1. When the data is stored in the cache memory 1 are then the requested data from the cache memory 1 via the private interface-6 to the central unit 2 returned. On the other hand, if the requested data is not contained in the cache memory 1 the cache memory 1 requests the data of the main memory 3 via the bus line 5, and the cache memory 1 also requests three additional data words from the address storage locations PRA + 1, PRA + 2 and PRA + 3 for the interleaving memory or an additional ■ data word from the address memory location PRA + 1 for the Bank memory on. When the data words from the main memory 3 via the bus line 5 from the cache memory are received, then they are written into the cache and the requested data word goes out the cache memory 1 is sent out to the central unit 2 via the private interface 6.

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Cache system

In Fig. 2, the cache memory system 1 is shown, which a bus line interface unit 10, a Exchange and update unit 11, a cache directory and a data buffer unit 12 and an address control unit 13 and a private one Cache memory central processing unit interface unit 6 includes. Fig. 2 consists of four sheets of drawings. The flow of information is best seen when Sheet 2 on the left, sheet 1 on the right, sheet 3 below sheet 1 and sheet 4 is below sheet 3.

Bus line interface unit 10 - FIG. 2, sheet 1

The bus line interface unit 10 shown in FIG. 2 comprises drivers 212, 214 and 218, receivers 213, 215 and 217 and a system bus line control logic unit 219.

The bus line interface unit 10 is connected to the bus line 5 via the interface signal bus line 4. The bus line 5, the interface signal bus line 4 and the system bus line control device are explained in more detail elsewhere (see US Pat . No. 3,993,981 and US Pat. No. 4,030,075). The facilities in question will only be explained here to the extent that this becomes necessary in the course of continuing the description.

Between the bus line 5 and the connection point of the driver 212 and the receiver 213 of the bus line interface unit 10 18 address lines BSAD05-22 are connected. With the output side the receivers are 213 » 215 and 217 connected to a buffer 203, which works on the FIFO principle, according to which the first entered

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2A

Information is also the first information output. At the connection point of the driver 214 and the Receiver 215 are 20-bit data word lines BSDT A, B, 00-15, BSDP 00, 08 connected. At the junction of driver 218 and receiver 217 is a Number of control signal lines connected. This control logic signals a bus line request BSREQT, a now running data cycle BSDCNN, a bus line acknowledgment BSACKR, a bus line wait state BSWAIT, BSAD23, the second half of a bus cycle BSHBC and a bus line double entrainment signal BSDBPL for the input side of the system bus line controller 219 via the receiver 217. The relevant Link signals are sent to the rest Link control units, which have been described above, are distributed, and also those concerned Signals transmitted to bus line 5 via driver 218.

The existing link signal MYDCNN- relating to its own data cycle is used between the system bus line controller 219 and drivers 212, 214 and 218.

In connection with the signal bus line BSAD08-17 it should be noted that the output side of the receiver 213 is connected to the cycle control 232 of the exchange and update unit 11. The output signal of an address register 207, namely a 18-bit address BA0R5-22, effected in the address controller 13 connects to the input side of the driver 212. The cache memory identification code 0002q and the function code 00 _Q or 01g are at the input side of the driver 214 coded, the output side of which is connected to the data lines BSDT A, B, 00-15 of the data bus line 5. The logic circuit signals described above are routed between the remaining units of the cache memory 1 and the system bus controller 219.

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The control signals Bus, Master Clear, BSMCLR and the signal BSSHBC indicating the second half of the bus cycle are fed to the test and verification logic 240. The data bus signal BSDT 08, 09, 10, 12, 14, and 15 occurs between receiver 215 and T&V logic 240. The link signals CACHRQ, CNOMEM and CACHON occur between the interface unit 6 and the T&V logic 240. The logic signals MEMREQ and MYACKR are provided to T&V logic 240.

The receiver-driver pairs 212 and 213, 214 and 215 or 217 and 218 are 26S10 circuits, as described on page 4-28 of the catalog "Schottky & Low Power Schottky Bipolar Memory, Logic & Interface published by Advanced Micro Devices, 901 Thompson Place, Sunnyvale, California, 94086 are.

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Address control unit 13 - FIG. 2, sheet 2 The address control unit 13 contains the address register AOR 207, the exchange address file RAF 206, an adder 211

AND gate 236, ^a

EXCLUSIVE-OR gate 237, a 2: 1 multiplexer 209, the read address multiplexer 233, a write address counter 234, and an AOR and RAF control unit 235. The address signal lines BAOR 05-22 + of the central unit 2 connect the interface 6 to one input side of a 2: 1 multiplexer 209. The the line carrying the logic signal MEMREQ connects the cycle controller 232 to the selection connection of the 2: 1 multiplexer 209. The line carrying the interlinking signals MEMREQ and CYQLTO connects the cycle controller 232 and the inputs of one NAND gate 241, the output of which is connected to the selection input of the 2: 1 multiplexer 209. The the output signal of the adder 211 leading signal lines AOR 05-22 + are on connected to the other input of the 2: 1 multiplexer 209, whose output signal lines BAOR 05-22 are connected to the inputs of the Address register 207 and the exchange address file 206 are connected. The signal bus line 05-22 + 10 is between the Output of address register 207 and the inputs of adder 211 and driver 212 connected. The address register is organized as an 18-bit register, which is made up of conventional Flip-flops. The exchange address data2O6 is made up of 4 18-bit registers and using the previously mentioned memory chips 75 LS 670 implemented with random access. Those carrying the link signals ADDRRO and ADDRR1 Lines connect the write address counter 234 and the exchange address file 206, the AOR and RAF controllers 235, the AND gate 236 and the EXCLUSIVE-OR gate 237. The das Link signal CYQLTO-leading line connects the cycle control 232 and an input of the AND gate 236 * The output of the AND gate 236 is at the connection +2 of the adder connected. The output of the EXCLUSIVE-OR gate 237 is connected to the input of the AND gate 240, the output of which is connected to terminal +1 of adder 211. The * and a NAND element 241 »

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Link signal CYQLTO + leading line connects the cycle control 232 and the other input of the AND element 240. The link signals ADDRWD + OB and ADDRWD + OA Leading lines connect the read address multiplexer 233 and the exchange address file 206. A lead carrying the link signal AORCNT connects the AOR and RAF controls 235 and the write address counter 234. The lines carrying the logic signals BAWRIT and BAORCK connect the AOR and RAF controls 235 to the exchange address file 206 or the address register 207.

To perform the interleaved store operation, the address control unit 13 loads the address register 207 with PRA and the CPU memory request address is sent to the main memory 3 through the bus line 5 in one off Format shown in FIG. 8b is sent out during a first memory request cycle. The address register 207 becomes then loaded with PRA + 1, i.e. with the memory request address that is sent to main memory 3 via bus line 5 is sent out in the format shown in FIG. 8b during the 2nd memory request cycle. The exchange address file 206 is loaded into successive memory locations with PRA, PRA + 1, PRA + 2 and PRA + 3 under the Control by write address counter 234, adder 211, and AOR and RAF controllers 235. These addresses become delivered to the address field of the local register 204 if the information is in the format shown in FIG. 8c is sent out from the main memory 3 via the bus line 5 to the cache memory 1. For the bank memory operation of the address control unit 13, the logic circuit loads the PRA, the memory request address, into the address register 207 the central unit 2, which via the bus line 5 to the main memory 3 in the format shown in Figure 8b sent out during the memory request cycle. The exchange address file 206 is in consecutive memory locations loaded with PRA and PRA + 1, under the control

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by the write address counter 23 4. These addresses are then transferred to the address field of the local register 204, if the information is in the format shown in FIG. 8c from the main memory 3 via the bus line 5 to the cache memory 1 is sent out. The read address multiplexer 233 selects the address storage location of exchange address file 206 * for reading from register 204 for each Response from the main memory 3 via the bus line 5 for the read request of the cache memory 1. The adder 211 gives over the output signal lines AORO 05-22 + from the address stored in the address register 207, which is under the control is increased by the AND gate 236 and 237 by +1 or +2. When the write address counter 234 is set in the memory location 03 is, the logic signals ADDRRO + and ADDRR + occur with a high level, whereby the AND gate 236 the input +2 of the Adder 211 releases. If the write address counter is set in memory locations 01 or 02, the output signal is given of the EXCLUSIVE-OR gate 237 the input +1 of the adder 211 free. The adder 211 is a logic circuit with the designation 74 283, as described on page 7-415 of the aforementioned TTL data book.

During the QLT operation, the logic signal CYQLTO- occurring at the input of the AND element 236 is low occur and hold the +2 input of adder 211 low. The logic signal CYQLTO +, i.e. the input signal for the AND gate 240, enables the input +1 of the adder 211.

The central unit 2 contains a Α register 2a, an index register 1 2b, an index register 2 2c and an index register 2d. These registers are in terms of their structure and their use here is of a conventional type. They are only used here to describe the method of operation to be able to continue.

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Exchange and update unit 11-2 Sheet 3

The exchange and update unit 11 shown in FIG. 2 contains the FIFO buffer 203, a local one Register (LR) 204, buffer bypass driver 205, a FIFO read / write controller 230, a clock controller 220 and a cycle controller 232.

The exchange and update unit 11 takes the 18-bit update address from the bus interface unit 10 BSAD 05-22, the 20-bit data word BSDT A, B, 00-15, BSDP 00, 08 and control signals. All signals or data are via the FIFO buffer 203 and their respective receivers 213, 215 and 217.

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The input of the register 204 and the output of an exchange address file (RAF) 206 in the address control unit 13 are an 18-line exchange address signal bus line AOR 05-22 connected. The signal bus lines FIFO 00-17, FIFO 19-38 and FIFO 18, 39- ^ 3 connect the output side of the FIFO buffer 203 with the input side of the register 204. In addition, between the exchange and update unit 11 and the other units of the cache memory 1 will be described in more detail below Transfer control signals.

A data word signal bus line DATA 00-19 + carrying 20 bits connects the output side of the buffer bypass driver 215 with a connection point 216 in the cache directory and the data buffer unit 12. The 18 line update or exchange address signal bus line FIFO 00-17 + connects the output side of the register 204 with the input side of a 2: 1 multiplexer 208. The data output signal lines carrying 20 bits DATA 00-19- connect the output side of register 204 to a cache data buffer 201. The read address counter output link signals FRADDR and FRBDDR are between the FIFO read / write control 230 and the FIFO buffer 203 are transmitted to the output signals FViADDR and FWBDDR of the address counter and the write clock signal FWRITE. The link signal CYFIFO is between the FIFO read / write controller 230, the cycle controller 232 and the register 204 transferred. The link signal FIFO 41+ is between the FIFO bit position 41 of the output side of the FIFO buffer 203 and the FIFO read enable ports for FIFO 00-17 transferred. The linking signals FIFO 41- are between the output side the FIFO bit position 41 of the FIFO buffer. and the exchange address file 206.

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via the lines designated FIFO 18, 42, 43 a read address multiplexer 233 with the appropriate Bit position outputs of the FIFO buffer 203 connected. The line carrying the link signal MAMREQ connects the Cycle controller 232, system bus line controller 219 and a 2: 1 multiplex switch 209. The line labeled CLOCKO + connects the clock control 220, the cycle control 232 and other link units, which are described below. The one labeled with logic signal NO HIT + Line connects the FIFO read / write controller 230, the cycle controller 232 and a NAND gate 231 of the cache memory. Directory and the data buffer unit 12. The with The line labeled REPLACE connects the output side of the register 204, the 2: 1 multiplex switch 223 and a circulation linking unit 224. The line labeled with linking signal FEMPTY- connects the FIFO read / write controller 230 and the clock control 220. The line labeled CACHRQ connects the interface and the clock control 220, and the line labeled with the logic signal CYCADN is at the interface 6 from the cycle control 232 connected.

The FIFO buffer 203 is made up of 4 44-bit registers or organized, which consist of random access memory chips and which consist of chips with the designation 74LS 670, as described on page 7-526 of the TTL data book for development engineers, 2nd edition, 1976, from Texas Instruments, Dallas, Texas. Register 204 is a 44-bit register obtained from conventional flip-flops using conventional Construction techniques consists. The address, data and control information are transmitted via the linking signal bus lines FIFO 00-17, FIFO 19-38 or FIFO 18, 39-43. The data signal bus line FIFO 19-38 outputs its data via the buffer secondary route driver 205 when the link signal INTEPvG + goes high. The buffer bypass drivers 205 consist of 74 circuits labeled 367 as shown on Page 5-69 of the aforementioned TTL data book. The FIFO read / write controller 230 outputs the read address counter signals FRADDR and FRBDDR, the write address counter signals FWADDR

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and FWBDDR and a write clock signal FWRITE to the FIFO register 203 for reading and writing. If a FEMPTY signal assumes a high signal level, this indicates that that the FIFO buffer is not empty. This is with the cyclical Control by means of the signal CLOCK!) + Started in the clock control 220. The occurrence of a signal FIFO 41+ with low signal level indicates that the 18-bit address field LR 0-17 of the register 204 from the exchange address file 206 via the 18-line signal bus line AOR 05-22 is filled.

The exchange cycle is based on the delivery of a memory request link signal CACHRQ from the central unit 2. If the information you need is not in the cache 1 is contained, a request for the relevant information is sent from the cache memory 1 via the bus line 5 the main memory 3 is sent out. The required information, which arrives from the main memory 3 via the bus line 5, is activated the central unit 2 is sent out and written into the data buffer 201. This operation is called an exchange operation .

The cache memory 1 reads all occurring on the bus line 5 Information into the FIFO buffer 203. If the information in question had to update main memory 3, then the cache memory 1 carries out a test to determine whether the relevant memory location of the main memory is stored in the data buffer 201. When the information address space is stored in the relevant data memory 201 is, then the data word in the relevant memory location is updated by means of the new information data word. These Operation is called update.

Cache memory and data buffer 12 - Fig. 2, sheet 4 The cache memory directory and the data buffer 12 comprise the data buffer 201, the directory 202, 4 comparators 221 ad, the 2: 1 multiplex switch 208, the circulating logic unit 224,

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a 2: 1 multiplex switch 223, 18 inverters 225, twenty NAND gates 251a-t, 252a-t, 253a-t and 254a-t, an AND gate 231 and a connection 216.

The signal bus lines are coded in the description and the figures as follows. For example, for the Line address ADDR 00-07-10 the designation ADDR represents the signal name. The designation ADDR 00-07 refers to 8 Signal lines labeled ADDR 00, ADDR 01 .... ADDR 07 are. With ADDR 00-07- it is indicated that the signals occur with a low level when they are characteristic of a "1", and with a high level if they are indicative of a "0". With ADDR 00-07-10 it is indicated that it is a signal bus line 10 with an 8-bit line address ADDR 00-07- acts.

The address signal lines BAOR 05-22 + of the main memory 3 connect the bus line 6 and an input of the 2: 1 multiplex switch 208 of the cache directory and data buffer 12. Connect the address signal lines FIFO 00-18 + the output side of the register 204 with the other input side of the 2: 1 multiplexer 208. The 2: 1 multiplexer 208 is with its output signal bus line ADDR 00-17 + connected to 18 inverters 225, whose output signals ADDR 00-17-10 in a row address ADDR 00-07-10 and are divided into a column address ADDR 08-17-10. The line address ADDR 00-07-10 leading Line is connected to the directory 202 and one input of each of the 4 comparators 221 a-d. The the column address The line carrying ADDR 08-17-10 is connected to the data buffer 201, the directory 202. The column address ADDR 08-17 + is fed to the circulation device 224. The line addresses .ADDR 00-07-20, -21, -22 and -23 occur on lines that are connected to the respective second input of the four comparators 221a-d are connected. The four output signals the comparator 221a-d, namely the logic signals ΗΪΤ0-3 +, join the input side of the '2: 1 multiplexer

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and also an input of 20 NAND gates at each 251a-t, of 20 NAND gates 252a-1, of 20 NAND gates 253a-t and of 20 NAND elements 254a-t. The circulating device 224 emits the signal on the output side LEVEL 0-3 +, which is the second input of the 2: 1 Multiplex_ers 223 is fed. The four output link signals WRITE 0-3 of the 2: 1 multiplexer 223 are each fed to a data buffer 201 associated with the respective levels 0-3. The output signals of the data buffer 201, the 20-bit signals CADP 00-19, -10, -11, -12 and -13 are fed to the second input, and the logic signal INTERG- is the third input of the NAND gates 251a-t, 252a-t, 253a-t and 254a-t, whose output signals CADP .00-19 + are fed to the connection point 216. The data word signals CADP 00-19 + occur between connection point 216 and interface 6. The output signals HIT 0-3 + are fed to the input of the NAND gate 231, the output signal of which is used by the cycle control 232 and the FIFO read / write controller. The 2: 1 multiplexers 208 and 223 become switched by the link signals ADDRSO + or REPLACE. The link signal REPLACE is the Circulating device 224 supplied.

The data buffer 201 is organized in four levels, each of which has 1024 data words in 1024 word storage locations stores which by the 10-bit column .address ADDR 08-17-10 can be addressed. Four words, one word per level, CADP 00-19-10, -11, -12 and -13, are read from the data buffer 201 when this data buffer is addressed. The directory 202 is also organized in four levels with 1024 storage locations per level. Any storage space stores an 8-bit line address. If the 10-bit column addresses ADDR08-17-10 to the input

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page of the directory 202 is delivered, four 8-bit line addresses ADDR 00-07-20, -21, -22 and -23 from the four levels of devS directory 202 read out for the four comparators 221a-d. These four addresses are combined with the input line address ADDR 00-07-10 and if a match is found, uias "hit" line signal occurs HIT 0+, HIT 1+, HIT 2+ or HIT 3+ with a high level, whereby the 20-bit output signal of the data buffer 201 via the 20 NAND elements 251a-t, 252a-t, 253a-t or 254a-t in question to the connection point 216 and the central unit 2 is delivered.

When a data word in data buffer 201 is to be exchanged, circulator 224 selects the LEVEL of the directory 202 and the data buffer 201 for the corresponding exchange by setting one of the LEVEL signals LEVEL 0-3 + to is brought to a high level. The 2:! Multiplexer chooses

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this signal is off because the logic signal REPLACE occurs at a high level and since the logic signal WRTPLS-den 2: 1 multiplexer 223 enables.

In an update mode, the selected hit line signal HIT 0-3 + switched through by the 2: 1 multiplexer 223 and output inverted by means of the inverter 255 to enable the selected level of the data buffer 201. As a result, the data word DATA 00-19- is written to the selected column address ADDR 08-17-10. The 2: 1 multiplexer 223 is enabled by the WRTPLS- link signal.

The circulator 224 has 2 1-bit memories with random Access to which are addressable by 1024 addresses. For each address location, in each RAM memory 2 bits are stored which, when decoded, select the next level of the column address to be replaced.

The directory or table of contents 202 and the data buffer 201 are designed to be memory chips 93 use random access, which are labeled LS 425. The circulator 224 is designed to use memory chips 93 with random access, which are labeled 415. These memory chips are on pages 7-119 resp. 7-70 of Bipolar Memory Data Book, 1977, from Fairchild Camera and Instrument Co., Mountain View, California, described. The logic circuits of the comparator. 221 a-d are through working at high speed 6-bit identity comparator circuits as formed by manufactured by Fairchild under the name TTL / MSI 93S47 will. The 2: 1 multiplexers 208 and 223 are logic circuits with the designation 75S157, as shown on page 7-181 of the aforementioned TTL data book.

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28b5730

Cache memory central processing unit interface unit 6

The interface unit 6 between the cache memory and the central unit has an 18-line address signal bus BAOR 05-22, a 20-line one having data signal bus line CADP 00-19 and a control signal bus line having a number of signal lines includes. Four of the control signal lines CACHON, which are responsible for the computer-dependent operation of the cache memory relevant link signal CNOMAEM-, which is no Correspondence indicating error link signal CACHRQ, the cache memory request link signal and CYCADN, the cache memory completion link signal, are described here. The central unit 2 has a Α register and three index registers used by the central processing unit instructions and a copy register for A and for recording of copy A, these registers being described above. These commands with the Α register and the three index registers do not form part of the invention and will not be further described.

System bus line 5 - control signals

The signals listed below are the signals appearing on bus line 5 that are required for the Explanation of the invention are required. In the US patents mentioned above, all are with the bus line 5 associated control signals fully described.

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-X-

28b5730

Memory refresh signal (BSMREF)

When the level is high, the BSMREF signal indicates that the address lines BSAD 05-22 contain a memory 3 word address.

The BSMREF signal, when low, indicates that the address lines BSADO8-23 contain a channel address and a function code.

Bus write signal (BSWIDE)

The BSWRIT signal, when high, indicates that a master is requesting a slave to perform a write cycle.

Signal relating to the second half of the bus cycle (BSSHBC) The signal BSSHBC indicates when the level is high that the main memory 3 is sending to the cache memory 1 information previously requested by the cache memory. The low level signal BSSHBC indicates that it is a test and check cycle.

Double removal signal (BSDBPL )

The BSDBPL signal occurs with a high level when it is sent out from the cache memory 1 to the main memory 3, to signal the main memory 3 that data is to be read in a double-take away operation

The signal BSDBPL occurs with a high level when it is sent out ^from the main memory 3 to the cache memory 1 with the first word of a two-word response to a memory request. The BSDBPL signal, on the other hand, occurs at a low level,

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2865730 - ■

if it is from main memory 3 to cache memory 1 with the second word of a two-word response to the memory request is sent out.

This allows the main memory 3 to be one word or two words to be sent to the cache memory. For example, if the PRA signal is the high order address of a memory bank then the BSDBPL signal will appear low, indicating that there is only one word on the memory request is transferred out.

MV Qulttungssicfnal (MYACKR)

The signal MYACKR goes high from the cache memory 1 is sent out to the system bus line 5 to indicate that the cache memory 1 is a data word transfer from the main memory 3 via the system bus line 5.

My bus request signal (MYREQT)

The signal MYREQT is sent with a high level from the cache memory 1 to the system bus line 5 to indicate that the cache memory 1 enclosing the system bus line 5 Cycle requests.

Present My data cycle (MYDCNN )

The signal MYDCNN, when it occurs at a high level, indicates that the cache memory 1 has received information via the system bus line 5 to the main memory 3 transfers.

Present data cycle (BSDCNN)

The signal BSDCNN indicates when it occurs at a high level that the main memory 3 is sending information to the bus line 5 for has given up the use by the cache memory 1.

Acknowledgment signal (BSACKR)

The signal BSACKR, when the level is high, indicates to the cache memory that the main memory 3 is the one from the cache memory 1 sent out memory request has received.

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28B5730

Waiting signal (BSWAIT)

When the signal BSWAIT occurs at a high level, it indicates to the cache memory 1 that the main memory 3 is occupied and cannot accept the memory request at this point.

Bus line request signal (BSREQT)

When the signal BSREQT occurs at a high level, it indicates to the cache memory 1 that a system is connected to the system bus line 5 System has requested a bus cycle.

Byte operation signal (BSBYTE)

The BSBYTE signal, when high, indicates a byte transfer rather than a word transfer.

Main clear signal BSMCLR

The BSMCLR signal, when high, prepares the cache and begins the QLT operation.

Clock control 220 - FIG. 3, sheet 2

The cache memory request link signal CACHRQ is shown in FIG. 3 of the test and checking logic 240, a reset terminal of a flip-flop 301 and

fed to an input terminal of a NAND gate 302. A Clock signal CLOCKO + is fed to the CLK terminal of the flip-flop. The output signal at output Q of the flip-flop is fed to the second input of the NAND gate 302. Das Output signal CPUREQ + OA of a NAND gate 306 is fed to the third input of the NAND gate 302, the output of which is included one input of a 30 ns delay line 303 and one input of a NAND gate 304 is connected. The outcome of the Delay line 303 is connected to the other input of a NAND gate 364. The Q output of flip-flop 301, the

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HS

the logic signal BLKREQ + is connected to a D input and the reset input of the flip-flop 305. That Logic signal "1" is fed to the set input of the flip-flop. A link signal MYACKR is the input CLK of flip-flop 305 is supplied. The INTERG + signal appearing at the Q output is fed to the buffer secondary path drivers 205, and that the output signal INTERG- occurring at the Q becomes the input side of the (HITO-3 +) - NAND gates 251 a-t, 252 a-t, 253 a-t and 254 a-t in the cache memory directory and the data buffer unit 12. The link signal FEMPTY-20 is fed to one input of AND gate 324 and one input of inverter 307. A logic signal MEMREQ becomes one input of the NAND element 306 fed. A link signal ADDRSO-, which occurs at the Q output of the flip-flop 309, is the other input of the AND gate 306 supplied. The link signal CYQLTO + is between the cycle controller 232 and the third input of the NAND gate 306 transmitted. The link signal ADDRSO +, the signal appearing at the output of the Q of the flip-flop 309 is applied to the selection input of the 2: 1 multiplexer 208 in the cache memory directory and supplied to the data buffer unit 12. The output of NAND gate 308 is fed to the SET terminal; the signal CLOCKO + is fed to the CLK connection, and a general clear signal CLEAR is applied to the reset terminal of the flip-flop 309. The link signals CYFIFO + OA and CYwRIT + OA become the corresponding inputs of the NAND gate 308 supplied. A link signal CPUREQ is from the output of the NAND gate 304 to a set terminal of the Flip-flops 313 supplied. A logic signal FEMPTY-is the reset terminal of the flip-flop 313 from the output of a Inverter 319 supplied. The logic signal FEMTPY + 20 occurring at the output Q of the flip-flop 313 and that at the output Q of the relevant flip-flop occurring logic signal FEMPTY-20 are fed to the input side of a NOR element 310

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leads. A link signal CYREAD is received from output Q a flip-flop 330 is supplied to the third input of the NOR gate 310, and the signal CLOCKO + is the fourth input of the NOR gate 310 supplied. The output signal of the NOR gate 310 is fed to an input of the NOR gate 311. The CLOCKO + signal is applied to the input of an inverter 312. An input signal CLOCKO- from inverter 312 becomes fed to an input of a NAND gate 315.

The clock control 220 outputs a timing control signal CLOCKO + for timing the logic circuits of the cache memory 1 from. The CLOCKO + signal begins a cyclical operation either on a storage conveyor from the central unit 2 or with the loading of the FIFO buffer 203 with the information from the bus line 5. In the case of this a memory request from the central unit 2 is the link signal CACHRQ, the input signal of the NAND element 302, occur with a high level, whereby the output signal of the relevant NAND gate assumes a low level. The other two input signals of the NAND gate 302, namely the signals BLKREQ- and CPUREQ + OA, come to this High level point in time. The flip-flop 301 is not set, so that the output Q has a high level. Both Inputs of the NAND gate 306 have a low signal level, so that the output signal of the relevant NAND gate leads to a high level. When the output of the NAND gate 302 goes low, it becomes an input of NAND gate 304 go low and 30 nanoseconds later the other input signal goes low Take level due to the delay in delay line 303. The low level occurring The delayed signal causes the logic signal CPUREQ to appear at a high level. The link signal CPUREQ, the Set input signal r of flip-flop 313 causes upon occurrence with a high level that the Q output signal FEMPTY-20 appears with a low level. The flip-flop 313 is a linkage

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circuit with the designation 74S74; this flip-flop gives output signals with a high level at the two outputs Q and Q if there are input signals with a low level at the inputs SET and PRESET. The 74S74 flip-flop is open Page 5-22 of the above mentioned TTL data book.

The logic signal FEMPTY-20 causes the output signal of the NOR gate 310 occurs at a high level, thereby causing the output timing control signal CLOCKO + of the NOR gate 311 with occurs at a low level. Fifty nanoseconds later, the output of delay line 314 causes the input at the other input of NOR gate 311 to low The level drops, causing the timing signal CLOCKO + to be brought to a high level. The time control signal CLOCKO + causes with transition to the high signal level the setting of the flip-flop 301, whereby the occurring at the output Q of this flip-flop Logic signal BLKREQ- occurs with a low level. As a result, the output signal of the NAND gate 302 becomes corresponding set and thus the output logic signal CPUREQ of the NAND gate 304. Furthermore, the input signal is on SET input of flip-flop 313 brought to a low level, whereby the logic signal FEMPTY-20 is set to a high level. This leaves the timing signal CLOCKO + at the output of NOR gate 311 at a high level. The timing signal CLOCKO + remains high as long as how the link signal CACHRQ remains at a high level. The link signal CACHRQ remains high for this time Level until the central unit 2 receives the requested data word and until the cache memory completion link signal CYCADN has been sent to the central unit 2.

The flip-flop 313, which controls the start of the cycle of the CLOCKO + signal, is also loaded by loading the FIFO buffer 205.

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controls. The write address counters flip-flops 316 and 317 in the FIFO read / write controller -230 switch to the next memory location after they have received the acknowledgment information from the bus line 5 (the BSACKR signal appears high). As a result, the output signal of the comparator 318, the logic signal FEMPTY +, is brought to a low level, as a result of which the output link signal FEMPTY- of the inverter 319 is brought to a high level. At high level Occurring logic input signal FEMPTY at the input RESET of the flip-flop 313 is the output logic signal FEMPTY + 2O occur at the output Q of this low-level flip-flop, which causes the cyclic occurrence of the timing signal CLOCKO + begins as before. In this case, the timing signal CLOCKÖ + occurs cyclically as long as there is information is contained in the FIFO buffer 203. The logic signal FEMPTY still occurs at a low level and the logic signal CYPJEAD occurs at the input of the NOR gate 310 with a low level. The output link signal CPÜREQ + OA from the NAND gate 306 remains low as long as the input signals MEMREQ or ADDRSO- of the NAND gate 306 occur with a high level. As a result, the occurrence of a memory request cycle is from the Central unit 2 avoided in the event that the link signal CACHRQ occurs again at a high level, namely as follows long until the aforementioned responses to the main memory requests as a result of a previous memory request are sent out by the central unit 2 to the cache memory 1. The link signal MYACKR also occurs high at the beginning of the main memory response to the memory request on the part of the central unit 2, whereby the flip-flop 305 is set. This brings the interconnection signal INTERG + to a high level, which causes the buffer secondary route driver 205 can be controlled in such a way that the data requested by the central unit 2 (PRA) are sent directly to the interface 6 are sent out. The INTERG- signal causes at

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Such activation of the NAND glifider occurs with a high level 251a-t, 252a4; ^ 53a-t254a-t in the cache directory and in the data buffer 12 that the selected word is sent out from the data buffer 201 to the central processing unit 2 can, provided the data word was stored in the data buffer 201 when the logic signal CACHRQ occurred with a high level. The input link signal FEMPTY + 30 for the connection SET of the flip-flop 301 ensures that the flip-flop 301 is then not set if the link signal CACHRQ during a cycle of the FIFO buffer 203 with high Level occurs. The flip-flops 301, 305 and 313 are logic circuits with the designation 74S74, as shown on Page 5-22 of the above mentioned TTL data book. The flip-flop 309 is a logic circuit with the designation 74SL75, as described on page 5-46 of the relevant TTL data book.

Detailed description of the FIFO read / write control 230 - Fig. 3, sheets 1 and 2

According to FIG. 3, the output of a NAND gate 324 is connected to the input SET of a flip-flop 323. A general one The clear signal CLEAR is fed to the input RESET of the relevant flip-flop, and a timing signal CLOCKO + is fed to the input CLK of the relevant flip-flop. The logic signal occurring at the output Q of the relevant flip-flop CYFIFO is fed to an input of a NAND gate 315. The timing signal CLOCKO- occurs between • the output of the inverter 312 and the other input of the NAND gate 315. The Q output signal, the logic signal CYFIFO, is also fed to the cycle controller 232. The Q output signal is fed to the input of AND gate 324. The link signal FEMPTY-20 is the other Input of AND gate 324 supplied. An output combination signal BUMPUP of the NAND gate 315 is the inputs CLK of the Elip-Flops 316 and 317 supplied, their RESET inputs

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285573Q

the signal CLEAR is supplied. The logic signals "1" are the inputs J, K and PRESET of the flip-flop

316 and the input PRESET of the flip-flop 217. The Q output signal of the flip-flop 316 is the inputs J and K of the flip-flop 317 and the input side of a comparator 318 are supplied. The Q output signal of the flip-flop

317 is also fed to the comparator 318. The Q output signals the flip-flops 316 and 317 are supplied to the read address selection terminals of the FIFO buffer 203.

The link signals BSACKR and BSWRIT occur between the receiver 217 and the input side of a NAND gate 337, the output of which is connected to the other input of the NOR gate 336. The link signal CACHON + occurs between the test and test logic and an input of a NOR gate 342. The link signal BSMREF occurs between the receiver 217 and the other input of the NOR gate 342, the output of which is connected to the third input of the NAND gate 337 is. A logic signal MYACKR + and a logic signal BSSHBC are fed to the NAND element 322, the output of which is connected to an input of a NOR gate 336, which is the output logic signal F +1 supplies the CLK inputs of flip-flops 320 and 321. The logic signals "1" are fed to the inputs J, K and PRESET of flip-flop 320 and the input PRESET of flip-flop 321. That The Q output of flip-flop 220 is fed to comparator 318 and to inputs J and K of flip-flop 321. The Q output of flip-flop 321 is fed to comparator 318. The Q outputs of flip-flops 320 and 321 are supplied to the write address selection terminals of the FIFO buffer 203. The link signal FIF041 + becomes the read enable pins of the address field FIFO bit positions 00-17 of the FIFO buffer 203 is supplied. A ground signal is applied to the read enable terminals of the data and control field FIFO bit positions 18-43 of the FIFO buffer 203 is supplied. The FIFO 41+ signal becomes the SET input of the local register 204 for replacing or updating the flip-flop bit position 41 submitted. The logic signals CYFIFO and REPLACE

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st

are fed to the input connections of the NOR element 325, the output signal of which is fed to a NOR element 327. The output signal of this NOR element, the logic signal CYWRIT + DA, is fed to the SET input of flip-flop 330 and an input of NAND element 308. The timing signal CLOCKO + is fed to the CLK connection, and the CLEAR signal is fed to the RESET connection of the flip-flop 330, whose Q output signal, that is the logic signal CYWRIT, is fed to the 2: 1 multiplexer 223. The Q output link signal of the relevant flip-flop, that is the signal CYREAD ₁ , is fed to the circulating circuit 224 and to an input of the NOR gate 310. The logic signal BSDCNN + is fed to the input of an inverter 326, the output signal of which is fed to the inputs of the delay lines 328 and 329. The output of the delay line 328 is connected to the input of an inverter 331, the output of which is connected to an input of the NAND gate 332. The output of the delay line 329 is connected to the other input of the NAND element 332, which outputs the logic signal FWRITE to the write enable input of the FIFO buffer 203. The logic signal NOHIT + is fed to an input of the inverter 334, whose output logic signal NOHIT- is fed to one input of a NOR element 340 and to one input of a NOR element 333, the output of which is connected to the other input of the NOR element 327. The logic signals CYFIFO and UPDATE are fed to the other inputs of the NOR element 333. The link signal CYQLTo occurs between the cycle controller 232 and the input of the NOR element 340, the output of which is connected to an input of the NOR element 325.

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28b5730

The link signal BSDCNN + occurs at the beginning of each data transmission cycle with a high level on / according to which a data transfer from main memory 3 to cache memory 1 he follows. The relevant logic signal is inverted with the aid of the inverter 326 and through the delay line 328 delayed by 10 ns, then again by means of an inverter

331 inverted and delivered as a delayed positive logic signal to the first input of the NAND gate 332. The output of the delay line 329 carries a negative logic signal that is applied to the second input of the NAND element

332 occurs with a 40 nanosecond delay. The two input signals for the NAND gate 332 occur for a duration of 30 nanoseconds with a positive level, whereby the write enable input signal FWRITE becomes a negative pulse / which has a width of 30 nanoseconds and which starts from the rise of the signal BSDCNN + by 10 Is delayed by nanoseconds. As a result, the information located on the output side of the receivers 213, 215 and 217 is keyed from the bus line 5 into a memory location of the FIFO buffer 203 which is determined by the Q output signals of the write address flip-flops 320 and 321, ie by the Link signals FWADDR- and FWBDDR-. The signal MYACKR occurs high when a cache identification output of an AND gate 546 (see FIG. 5) occurs high, indicating that the cache signal ID 0002 _{o is} over

the receiver 213 has been received by the bus line 5 and that this is not a main memory 3 relating to it Write operation. When the 60 nanosecond delayed signal BSDCNN + occurs high, then the flip-flop 516 is set, and the logic signal MYACKR, the input signal of the NAND gate 322, occurs at a high level

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on. Since this is a response to a memory request, the BSSHBC signal appears high, causing the output signal of the NAND gate 322 with a high level and the output signal of the NOR gate 336, the logic signal F + 1 with a low level. By the fact that the CLK input signals of the flip-flops 320 and 321 are transferred to the low level, the write address counter flip-flops 32O and 321 are incremented. Since the output link signals FWADDR + and FWBDDR + of the write address count flip-flops 320 and 321 as well as the logic signals FRADDR + and FRBDDR +, the output signals the read address counter flip-flops 316 and 317 are no longer the same, the logic signal FEMPTY + occurs, the output of comparator 318, low on. As a result, the cycle signals CLOCKO + begin, as was previously described with regard to the clock controller 220 is.

The write address counter flip-flops 320 and 321 and the read address counter flip-flops 316 and 317 are conventional JK flip-flops, labeled 74S112, as shown on page 5-24 of the TTL data book mentioned above. These Flip-flops operate in the following way. Assume that the two flip-flops 320 and 321 are reset are, the Q output signals FWADDR- and FWBDDR- appear high. When the FPLUS1 signal is low passes, the flip-flop 320 is set when the trailing edge of the logic signal F + 1 occurs. The Q output of the Flip-flops 320 remains low and comes to terminals J and K of the flip-flop 321, which is reset remain. If the flip-flop 320 is set and it emits its Q output signal with a high level, the next Signal falling edge of the logic signal F + 1, the flip-flop 320 'is reset and the flip-flop 321 is set.' With occurrence

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£ 7

... ' 28b5730

the next falling edge of the logic signal F + 1, both flip-flops 320 and 321 are set, and with When the fourth falling edge of the logic signal F + 1 occurs, both flip-flops are reset. While the three input signals of the NAND gate 337, namely the logic signals BSACKR and BSWRIT and the output signal of the NOR gate 342 high, causing the NOR gate 326 has a low level output signal F + 1, which causes the write address counter flip-flops 320 and 321 can be advanced. However, during the test and verification operation, if the Cache memory is brought into a bypass cache memory mode, the link signal CACHON + with low Level, whereby the output signal of the NOR gate 342 occurs at a low level. As a result, the NAND gate 337 outputs a high level signal, thereby the output link signal F + 1 of NOR gate 336 occurs high. This prevents information is written on the bus line 5 in the directory 202 and in the data buffer 201 by switching the write address counter flip-flops 320 and 321 are prevented. The cache memory 1 remains in this By-pass operation as long as the link signal CACHON + remains at a low level. Of the The rise of the CLOCKO + signal causes the flip-flop 323 ρ to set its Q output signal, which is the logic signal CYFIFO, rises to a high level. When the CLOCKO + signal then goes low, take the two logic signals CYFIFO and CLOCKO-, which are fed to the inputs of the NAND gate 315, one high level. As a result, the output link signal BUMPUP assumes a low level, with the result that the read address counter flip-flops 316 and 317 advance. The input signals FWADDR + applied to the comparator 318 and FWBDDR + equal to FWADDR + and FWBDDR + lead to the setting of the signal FEMPTY + with a high level, which means that the output of the

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S *

Timing signal CLOCKN + is held if there is no bus line 5 cycle control signal BSDCNN. The logic signal FEMPTY + is inverted by means of the inverter 319, and the logic output signal FEMPTY-, which occurs at a low level, sets the flip-flop 313 so that its output signal FEMPTY + 2O occurs at a high level. As a result, the output signal of the NOR gate 31Ο is brought to a low level, with the result that the output signal CLOCKO + of the NOR gate 311 occurs with a high level. The logic signal CYFIFO according to FIG. 2 causes the output signal of that memory location of the FIFO buffer 203 which is designated by the read address counter flip-flops 316 and (FRADDR- and FRBDDR-) to be introduced into the local register 2o4 . If the information in the FIFO buffer 203 is a response signal to a memory request, then the signal FIFO 41+ occurs with a high level. This sets the local register 204, which causes the signal F / F41 according to FIG of the QLT-Betriefos with a high level to " because the logic signal CYQLTO- occurs with a low level. As a result, the output signal of the NOR gate 325 will appear at a low level, while the output signal of the NOR gate 327 occurs at a high level, so that the next time the signal CLOCKO + rises, the flip-flop 330 will be set. Output logic signal CYWRIT with a high level at nnd continues its cyclical occurrence under the control of the input logic signal CYFIFO fed to the NOR element 325 for the remainder of the QLT operation.

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During normal operation, this occurs at the input of the · NOR gate 340 logic signal CYQLTO- with high level. Therefore, in exchange operation with a high Level occurring link signals REPLACE and CYFIFO in the event that the search process in the directory 202 to does not result in a hit, the three inputs of the NOR element are each fed a signal with a high level. aside from that the logic signal CYWRITd of the flip-flop 330 occurs with a high level.

The flip-flop 309 of the clock control 2 20 had previously been set, since the signals CYWITE + OA and CYFIFO + QA during the previous Low level cycles occur. This occurs

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the Q output signal ADDRSO + at high level, and the 2: 1 multiplexer 208 according to FIG. 2 is set so that it accepts the memory address BAOR 05-22 +, i-lit the increase of the CLOCKO + signal, the logic signal CYFIFO + OA occurs at a high level, since the flip-flop 323 does not is set and there is the Q output of the relevant flip-flop is fed with a high level as an input signal to the AND gate. The input signal applied to AND gate 324 FEMPTY-20 also occurs at a high level. As a result, the input signal to be fed to the NAND gate 308 occurs CYFIFO + OA with a high level, whereby this logic element emits an output signal with a low level. Since the low level signal applied to the SET input of flip-flop 309 occurs, the Q output signal occurs ADDRSO + at low level. The 2: 1 multiplexer 208 of FIG. 2 is thereby set or switched so that it receives the address output signal FIFO * 00-17 + from the local Register 204 picks up. If flip-flop 323 is set, so will the next rise of the signal CLOCKO + reset because its Q output signal, which is fed to the input side of AND gate 324, with occurs at a low level. As a result, the SET input of the flip-flop 323 is supplied with a low-level signal which resets the flip-flop in question. This causes the Q output link signal CYFIFO to occur with a low level.

The UPDATE link signal occurs during an update operation, which is the one input signal for the NOR element 333, with a high level. If directory 202 indicates the presence of a hit, then the output signal occurs of the inverter 334, which is the logic signal NO HIT-, with a high level. When the link signal CYFIFO occurs with a high level, then the three input signals of the NOR gate 333 carry a high level, whereby the output-ngs-

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signal of the logic element in question will occur at a low level. This occurs at the output of the NOR gate 327 an output signal goes high. The next time the timing signal CLOCKO + rises, flip-flop 3 30 is set as before, indicating the presence of a cache write cycle.

The flip-flops 323 and 330 are logic circuits with the designation 74S175 as mentioned on page 5-46 of the above TTL data book are described.

Detailed description of the AOR and RAF control 235 -Fig. 4, sheet 1

Read address multiplexer 223 and write address counter 234 -Fig. 4, sheet 2

The outputs of the NAND gates 417 and 418 are at the inputs a NOR gate 419 connected. A logic signal BLOCKF + occurs between the NAND gate 417 and the - cycle control 232 on. The link signal FEMPTY-20 occurs between the clock control 220 and an input of a NOR gate 442, which with its output at the third Input of the NOR gate 419 is connected. The output of the NOR element 419, which carries the logic signal AORCNT, is at the inputs of delay lines 420 and 421 and at one input of a NAND gate 424 and at one Input of a NAND gate 416 connected. The logic signals MEMREQ- and CYQLTO + occur between the cycle control 232 and the inputs of a NAND gate 441. The link signal CYFIFO occurs between the FIFO read / write control 230 and a further input of the NAND gate, the output of which is connected to an input of the NOR gate 442 is. The logic signals CYQLTO-1A and CYQLTO-OB occur between the cycle controller 232 and the inputs of a

9 09828/0726

NAND gate 443, the output of which is connected to an input of the NOR gate 419 is connected.

The output of the NAND element 424, which carries the link signal BAORCK, is connected to the address register AOR 207. The output side of the delay line 421 is connected to an inverter 423, the output link signal of which AORCNT-30 is fed to the CLK inputs of flip-flops 426 and 427 will. The output of the delay line 420 is connected to the input side of an inverter 422, the output side at the inputs of the NAND gates 416 and 424 is connected. A link signal BAWRIT occurs between the output of the NAND gate 416, the input of the NAND gate 425 and the write scan port of the exchange address file 206. The link signal MEMREQ is fed to the input of the NAND gate 425 and the RESET inputs of the flip-flops 412 and 413 and the cycle control 232. The output of the NAND gate 425 is connected to the reset connections of the flip-flops 426 us? 427 and with the Inputs J and K of flip-flop 427 connected. The Q output of the flip-flop 426, the logic signal ADDRRO + is connected to the write address connection 2 of the exchange address file 206 and to the input of the NAND gate 418. The link signal MYACKR occurs between a further input of the NAND gate 418 and the cycle control 232 on. The Q output of flip-flop 426, viz the link signal ADDRRO- is fed to the inputs of the NAND gates 417 and 424. The Q output of the flip-flop 427, which carries the link signal ADDRRI +, is at the write address connection 1 of the exchange address file 206 and connected to the input of the NAND gate 417 BSDCND + occurs between cycle start 232 and the CLK connection of a flip-flop 409. The linkage

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signal BSAD23 + occurs between the SET input of flip-flop 409 and the output of receiver 217. The link signal MYACKD occurs between the cycle controller 232 and the Input of the NAND gates 410 and 411. The Q output of the flip-flop 409, which carries the logic signal BSAD23 + 1O, is connected to the other input of the NAND gate 410. The Q output of flip-flop 409, which carries the link signal BSAD23-1O, is at the other input of the NAND gate 411 connected. The output of the NAND gate 410 is connected to the CLK connection of the flip-flop 412, and the output of NAitfD element 411 is connected to the CLK connection of flip-flop 413. A link signal "1" is supplied to the PRESET, J and K terminals of the flip-flops 412 and 413. The Q output of the flip-flop 412, which carries the logic signal FCHONE +, is at the input of the FIFO bit position 43 of the FIFO buffer 203 according to Fig. 4 connected. The Q output of the flip-flop 413, which carries the logic signal FCHZRO +, is at the input of the FIFO bit position 42 of FIFO buffer 203 connected. The link signal BSAD23 + occurs at the input of the FIFO bit position 18 of the FIFO buffer 203. The output of the FIFO bit position 18 is at a selection connection 1 of the multiplexer 414 and 415 connected. The multiplexers are dual data selectors / multiplexers, the signals from four Take up lines and pass them on to a line and which is formed by circuits with the designation 74S153 as they are described on page 5-42 of the above mentioned TTL data book. Terminal 1 of a bank-like nested selection switch 407 is connected to ground. The connection 2 carries a logic signal "1". The logic signal BANKED + 00 occurs between the connection 3 and an input of the fm-Güedes 408, whose output ' Link signal ADDRWD + the selection connection 2 of the 4: 1-

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Multiplexers 414 and 415 is fed. The link signal CYQLTO- occurs between the cycle controller 232 and the other input of the NOR gate 408. The link signal BANKED + OO is also the Cycle control 232 is supplied. The release input and the input terminal 2 of the

4: 1 multiplexers 414 are like the enable input and the Input terminal O of the 4: 1 multiplexer 415 connected to ground. Input 3 of the 4: 1 multiplexer 414 and input 1 of the 4: 1 multiplexer 415 each carry a logic signal "1". The input O of the 4i1 multiplexer and input 2 of the 4; 1 multiplexer 415 are connected to the Output of the FIFO bit position 42 of the FIFO buffer 203 connected. The input 1 of the 4: 1 multiplexer 414 and the input 3 of the 4: 1 multiplexer 415 are at the output of the FIFO bit position 42 of FIFO buffer 203 connected.

9 0982 8/0726

The outputs of the multiplexers 414 and 415, the logic signals ADDRWD + OB and ADDRWD + OA are at read address connections 1 and 2 of the exchange address file 2o6 and also connected to the cycle controller 232. The link signal FIFO 41-will supplied to the read enable input of the exchange address file 2o6. The link signal BSDCNB + occurs between the RESET input of the flip-flop 409 and the cycle controller 232.

If the signal CACHRQ according to FIG. 3 occurs with a high level, this indicates that the central processing unit 2 is a data word requests. The central unit 2 also sends the memory location address BAOR o5-22 + to the main memory 3 according to FIG. 2 of the requested data word. The address BAOR O5-22 (PRA) occurs at the inputs of the address register. ' AOR 2o7 and in storage space oo of the exchange address file 2o6. In addition, the address is sent to the directory 2o2 and sent to the data buffer 2o1 as row address ADDR oo-o7-1o and as column address ADDR o8-17-1o. Of the 2 !! - Multiplexer 2o8 is due to the high level occurring Signal ADDRO + switched to the input signal BAOR o5-22 +. A search is also carried out in the directory 2o2 started. If the output signal FEMPTY-2o of the flip-flop 313 according to FIG. 3 assumes a low level, then occurs the output signal ÄORCNT of the NOR gate 414 according to FIG. 4 with a high level and the one input signal the NAND gates 416 and 424 occur high. Since the other inputs of the NAND gates -116 and 424 signals lead to a high level, the logic signals BAWRIT and BAORCK occur with a low level. The output signal of the Delay line 4o occurs fifty nanoseconds later high, causing the outputs of the NAND gates 416 and 424 the logic signals BAWRIT and

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BAORCK occur at a high level. The signal PRA is keyed into the address register AOR 2o7 and into the memory location oo of the exchange address file 2o6 when the signals BAWRIT and BAORCK appear at a low level. That with a high level Occurring logic signal AQRCNT- is through the delay line 421 delayed by 70 nanoseconds and inverted by means of inverter 423. The logic output signal A0RCNT-3O of inverter 423sdialtet on occurrence with low Level the write address counter 234 to the memory location o1. The write address counter consists of JK flip-flops 426 and 427, the operation of which has already been described above. The link signal ADDRRI + now occurs at a high level Level and the logic signal ADDRRO + now occurs at a low level, whereby the write address in the Exchange address file 2o6 is set in the storage location o1. Assuming that from the central processing unit 2 data requested from test memory 1 are not stored in read-only memory 1, then the signal MEMREQ + brought to a high level according to FIG. According to FIG. 2, the logic signal MEMREQ occurring at a low level leads to that the output signal of the NAND gate 241 occurs with a high level, through which the 2: 1 multiplexer 2o9 in such a way is controlled to receive the output AORoo5-22 + of the adder 211. The link signal ADDRR1 + occurs at a high level and since the logic signal ADDRRO + occurs at a low level, the output signal +1 of the exclusive-OR gate 237 occurs at a high level, whereby the Signal PRA + 1 via the address signal lines AORoo5-22 + is output, and the 2: 1 multiplexer 2o9 outputs the output signal BAORo5-22 via the output lines.

For the bank-like and nested memories, the first memory request is made the main memory 3 is sent out via the bus line 5 and

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an acknowledgment signal BSACCR is returned from the main memory 3 via the bus line 5 to the test memory 1 in order to Set logic signal BLOCKF + to a high level, as can be seen from FIG. When the BLCKF + signal is high Level occurs, the three inputs of the AND gate 417 lead 4 a high level, whereby the output signal of the logic element in question at a low level occurs. This occurs at the output of the NOR gate 419 Link signal AORCNT with a high level, whereby the link signal BAWRIT for the exchange address file 2o6 ■ is set. The write scan signal and the link signal BAORCK for the address register 2o7 are low Levels occur, as will be seen later. As a result, the signal PRA + 1 is in the address register 2ö7 and in the Storage space o1 of change address file 2o6 introduced. The logic signal A0RCNT.-3o, which occurs at a low level causes the write address counter 234 to switch to memory location o2 as before. Regarding the storage space o1 the logic signal ADDRRO + occurs at a high level, and · the logic signal ADDRO + occurs at a low level. . ' Mit.dem signal drop of the logic signal fORCNT-3o becomes the link signal ADDRRO + with high level] occur, and the ADDRRI + signal will appear at a low level. Of the . Write address counter 234 addresses the memory location o2. The bank storage system now awaits a response from the main storage 3 to the first storage request during this time the nested storage system sends out a second storage request.

This occurs at the end of the second memory request cycle Logic signal MYACKR + according to FIG. 5 with a high level and begins a first data response cycle from the main memory 3 to the test memory 1. Since the link signal ADDRRO + also occurs at a high level, the output signal occurs

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of the NAND gate 418 at a low level. This will the output logic signal AORCNT of the NOR gate 419 occur with a high level. As previously described, this takes Logic signal BAWRIT a low level, whereby the signal PRA + 2 is entered in the memory location o2 of the change address file. According to Fig. "2 that remains Signal PRA + 1 in the address register AOR. 2o7 saved. When the write address counter 234 is set to the memory location o2 is, then the output link signal ADDRRO + occurs with a high level, while the output signal ADDRR1 + occurs occurs at a low level. This results in a +1 output from the exclusive OR gate 236 at a high level will occur and that from the output of the adder 211 the Signal PRA + 2 is output to the address signal line, these are the output signals AORO o5-22 + and BAOR o5-22, the. get to the 2: 1 multiplexer 209. It should be noted that the link signal BAORCK the write scanning signal for the address register 2o7 and is not brought to the low level, namely the input link signal ADDRRO- occurs for the low level NAND gate 424. The write address counter 234 becomes storage location o3 advanced when the A0RCNT-3o signal goes low, as described below, and if the link signal ADDRRO + and ADDRR1 + each with occur at a high level. This has the result that the output +2 of the AND gate 236 according to FIG. 2 assumes a high level, as a result of which the output of adder 211 is set to PRA + 3. . The link signal MYACKR occurs at the beginning of the second Data word cycle from main memory 3 to cache memory 1 again with a high level on the first * 5 memory request there. As a result, the link signal AORCNT is on again brought high level and the logic signal BAWRIT occurs again with a low level. In the storage disks o3 the change address file 2o6 the signal PRA + 3 is introduced and the write address counter 234 is set to the

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28S5730 -YES-

Storage space switched oo.

If there is an interleaved memory, four data words are used from the main memory 3 via the bus line 5 to the cache memory 1 in four separate bus line 5 cycles. Figure 8C illustrates the format of the response signals. The lowest significant bit BSAD 23 of the function code sets determines whether the data word in response to the first memory. promotion or the second memory request for data words is delivered. The link signal BSAD23 + and the function code development flip-flops 412 and 413 designate the storage location of the change address file 2o6 in which the Main memory 3 relevant address for the transmitted data word is stored. The first data word is on the PRA location of main memory 3, and it is taken from the Main memory 3 is transferred to cache memory 1 with the function code set to 00g. The least significant bit, BSAD 23+ of the function code oog occurs at a low level and is used in the FIFO bit position 18 of the FIFO buffer 2o3 according to FIG. 2 is set, when the FIFO scan signal FWRITE- is low accepts. At this point in time, the function development sflip-flops 412 and 413 are also not set, and the output link signals FCHZRO + and FCHONE + occur low, causing the FIFO 42 and FIFO 43 bit positions lead to a low level. If the switch 407 is set to the interleaving mode, the logic input signal occurs BANKED for the inverter 4o8 with a low level, D ^ it has the consequence that the output link signal ADDRWD + occurs at a high level. This results in a high signal level at SELECT terminal 2. This will make the input connections 2 and 3 of the 4: 1 multiplexers 414 and 415 activated. By the Signal FIFO 18 becomes the SELECT connection 1 of the 4: 1 multiplexer 414 and 415 brought to a low level, whereby the Input 2 is made active. Since the FIFO 42 signal occurs low, the output link signals also occur

909828/0726

äDDrwd + OB and ADDRWD + OA the 4:! - Multiplexer 414 and 415 with a low level. As a result, the read address of the change address file 2o6 is stored in the storage location oo brought and the signal PRA appears on the address signal lines AORO o5-22 according to FIG. The relevant signal is then entered into register 2o4 when the logic signal CYFIFO occurs at a high level. The signal BSAD 23+ occurs with a low level when the Q output signal, which is the input side of the NAND gate 411 is supplied, occurs with a high level. Since the signal BSAD23 + occurs with a low level, the Q output signal, which is supplied to the input side of the NAND gate 411, then at a high level occur when the logic signal BSDCND + will assume a high level. When the link signal MYACKD occurs at the input of the NAND gate 411 with a high level, then takes the output of NAND gate 411 a low level. This sets the flip-flop 413 to 0.

When the next bus line 5 cycle occurs, the data word PRA + 2 is transferred from the corresponding memory location in the main memory / to the cache memory 1 and the function code on signal lines BSAD18-23 the bus line 5 remains at 00, with the signal BSAD 23+ as the lowest significant bit with low Level occurs. In this case, as shown in FIG. 4, the FIFO bit position 18 of the FIFO buffer 203 goes to a low level Value set and the FIFO bit position 42 set to a high value. Since flip-flop 413 is set, this occurs Q output link signal FCHRZO + high. At the outputs of the 4: 1 multiplexers 414 and 415 occur the logic signal ADDRWD + OB with a low level and the logic signal ADDRWD + OA with a high level, because the two input connections of the 4: 1 multiplexer

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lead an "O" while the two input connections of the 4: 1 multiplexer 415 will carry a "1". This turns the Storage location o2 of the change address file 2o6 read out, the address PRA + 2 was saved.

The third data word transmission cycle over the bus line leads to the fact that the data word from the memory location PRA + 1 of the main memory 3 with a function code of o1g will. In this case the signal BSAD 23+ occurs with a high level, and the FIFO bit position 18 of the FIFO buffer 2o3 according to FIG. 4 carries a high signal level, whereby the input connection of the 4: 1 multiplexers 414 and 415 is made active will. The FIFO-18 position 43 has a low signal level, and the FIFO bit position 42 does not matter. In this case, the FIFO bit position 18 becomes a high signal level lead, the output signal ADDRWD + OB of the flip-flop 414 occurs with a high level, and there?. Output signal ADDRWD + OA of flip-flop 415 occurs with a low level. In doing so, the size is read out of the memory location o1 of the change address file 2o6 in its memory location PRA + 1 is contained. The signal BSAD23, which occurs with a high level, causes the setting of the flip-flop 4I9 when the Link signal BSDCND + assumes a high level. The occurrence of the logic signal BSD23 + 1o at the Q output leads to the fact that the output signal of the NAND element 41 o occurs at a low level when the logic signal MYACKD + goes high. This sets the flip-flop 412 and the logic signal FCHONE + appearing at its Q output assumes a high level. The fourth bus line 5 cycle brings the data word from memory location PRA + 1 into main memory 3; the cycle in question has a function code of o1. Signal BSAD 23, which appears high as before, causes the FIFO bit position 18 has a high signal level and that the FIFO bit

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Position 43 has a high level because the logic signal FCHONE + has a high level.

Those appearing at the outputs of the 4: 1 multiplexers 414 and 415 Link signals - the link signal ADDRWD + OB occurs with a high level, and the link signal · 'ADDRWD + OA occurs high level - lead to the reading of the change address file 2o6, namely the storage space o3, which has the size PRA + 3 saves. The flip-flops 412 and 413 are reset when the logic signal MEMREQ + assumes a low level.

If there is a bank-like memory, two data words are sent from the main memory 3 via the bus line 5 to the
Cache memory 1 transferred in two separate bus line 5 cycles. In this case, the switch 407 is set to the terminal 2 (memory bank operation), whereby the input signal of the inverter 408 appears with a high level. This leads to the output of an output link signal ADDRWD + with a low level
Level. In addition, in the case of the bank-type memory, the
Function code 00 _β on the response to the memory request. Therefore the signal BSAD23 + occurs for both data words
low level, which are sent out from the main memory 3 via the bus line 5 to the cache memory 1. The FIFO bit position 18 of the FIFO buffer 203 therefore has a low level for both data words. The select input signals at terminals 1 and 2 of the 4: 1 multiplexers 414 and 415 are low, which is why input terminal 0 is activated. When the first data word in the FIFO buffer 203 is read from the bus line 5, the logic signals ADDRWD + OB and ADDRWD + OA occur with a low level, and that in
The signal PRA stored in the memory location 00 is read from the change address index 206. When the link signal
MYACKD is then raised to a high level, this occurs

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The output of the NAND gate 411 is low, and the flip-flop 413 is set. The Q output signal BSAD23-10 of the flip-flop 409 occurs at this time -high level. The Q output signal FCIIZRO + of the flip-flop 413, the occurs with a high level, is in the FIFO bit position 42 with the occurrence of the next FWRITE enable pulse of the FIFO buffer 203 saved. As a result, the output signal ADDRWD + OB of the 4: 1 multiplexer 414 will appear high, so that the address (PRA + 1) in the memory location 01 of the change address card 206 to the local register 204 with the second data word in response to the memory request will.

The flip-flops 412, 413, 426 and 427 are logic circuits with the designation 7 4S112, as described on page 5-34 of the TTL data book mentioned above. In which Flip-flop 409 is a logic circuit with the designation 74S175, as mentioned on page 5-46 of the Data book is described.

During the initial or initial operation, the CLEAR clear signal first the content of the address register 207 is brought to 0. As a result, the adder 211 gives on the output side only zeros. Accordingly, when the sampling signals BAOROCK and BAWRIT are brought to a low level, the Adder 211 produces an output consisting of all zeros into the address register 207 and the change address file 206 is written into the memory location 00.

In the QLT mode, the BAWRITs are the write scanning channels Change address file and the write strobe signal BAORCK of the address register lowered to a low level when the two input signals for the NAND gate 443 with low

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Level occur or when the two logic input signals CYQLTO-1A and CYQLTO + OB of the NAND element 443 with occur at a high level. As a result, the output signal of the NAND gate 443 occurs with a low level, whereby the output logic signal AORCNT of NOR gate 419 will occur high. As previously explained, the write strobe signals BAWRIT and BAORCK lowered to a low level. This makes the PRA address storage location 0000 in the address register 207 and the memory location 00 in the change address file 206 is set. The write address counter 23 4 of the change address file is advanced to storage location 01 when the output link signal AORCNT-30 of the inverter 423 is lowered to a low level. The Q output link signal ADDRR1 + of the flip-flop 427 and the Q output ADDRRO- of flip-flop 426 are brought high. This occurs at the connector +1 of the adder 211 is the output of the exclusive-OR gate with a high level, and on the signal lines A0R0-05-22 + appear the output signals of the adder 211 with 0001.

When the logic signal BLOCKF +, which is the input signal of the NAND element 417, is brought to a high level, the three input signals of the NAND element 417 occur according to E ¹ ig. 4 occurs at a high level and the output signal occurs at a low level. As a result, the logic signal AORCNT occurs at the output of the NAND element .auf. This leads to the output of write scan signals BAWRIT and BAORCK with a low level, whereby the address storage location 0001 in the storage location 01 of the change address file 206 and in the address register 207 are set. The write address counter 23 4 is then incremented to the memory location 02. The Q output link signal ADDRRO + of the flip-flop 426 occurs high, and the Q output-

909828/0726

Logic signal ADDRR1 + of flip-flop 427 occurs at a low level, as can be seen from FIG. DÄmit the output logic signal +1 of the exclusive-OR gate 237 assumes a high level again, whereby the output signal of adder 211 on signal lines AORO 05-22 + becomes 0002.

When the input signal MYACKR + of the NAND gate 418 of FIG. 4 goes high, then the output signal becomes assume a low level, whereby the output logic signal AORCNT of the NOR gate 419 a high level accepts. In this case, the write scan address BAORCK remains high as the input link signal ADDRRO of the NAND gate 424 has a low level. The write strobe signal BAWRIT needs to be low Level brought, as a result of which the size 000,002 'is introduced into storage location 02 of the change address file 206. The write address counter 234 is incremented to the memory location. The link signal MYACKR + resumes becomes high, and the address location 0002 becomes the location 03 of the change address file saved. The address counter is also switched to memory location 00.

Places 02 and 03 of the change address file 206 become regarded as "empty" spaces and not used in QLT operation.

If the input link signals MEMREQ-, CYQLTO + and CYFIFO of the NAND gate 441 occur with a high level, then occurs the output signal of the relevant NAND gate with a low level, whereby the output signal of the NOR gate 442 with a low level and the output logic signal AORCNT of the NOR gate 419 occurs with a high level.

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This makes the address memory location 0002 in the address register 207 and the storage location 00 in the change address file 206 are set, and the write address counter 234 stop at 01.

The sequence described above continues as long as until the address storage space 4096 in the address register 207 and the change address file 206 is set and until the QLT operation is complete.

The output link signal ADDRWD + of the NOR gate 408 remains high during the QLT operation, since the Input link signal CYQLTO- remains low. As a result, the connections 2 of the 4: 1 multiplexers 414 and 415 carry a high level. Since the FIFO bit position 18 of the FIFO buffer 203 according to FIG. 4 remains at a low level, select terminals 1 of 4: 1 multiplexers 414 and 415 are low. Accordingly are the input terminals 2 of the 4: 1 multiplexers 414 and 415 active, since the selection terminal 1 is low and the selection terminal 2 is high.

Detailed Description of the Cycle Controller 232-5, Sheets 1 + 2 .

The linking signals MYACKD, BSDBPL-, BSW.?IT, MYDCNI, +, MEMREQ +, BSDCND-, BSACKR, CLEAR- and CLRREQ-OA become the System bus controller 219 supplied. The MEMREMQ- signal is sent to the AOR and RAF controls 235 and the addresson controller 13 supplied. The logic signals CYFIFO, CYREAD + and FEMPTY + 30 are provided to the FIFO read-write controller 230. The link signal NOHIT + is fed to directory 202. The link signal MYACKD is the one Input of a NAND gate 506, and the signal BSDBPL-

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is fed to the other input of the NAND gate 506, the output of which is connected to an input of the NOR gate 507 is which the logic signal DATACK- den on the output side Clock inputs. the flip-flops 508 and 509 supplies. The logic signal · BSWAIT becomes one input of a NAND element 505 is supplied, and the signal MYDCNN + is supplied to the other input of the NAND gate 505 and a SET input of flip-flop 504. The logic signal BLOCKF + occurs between the Q output of flip-flop 504 and the other input of the NAND gate 505, the output signal of which is fed to the other input of the NOR gate 507. The link signal BSACKR is fed to the CLOCK input of the flip-flop 504, its Q output link signal BLOCKF- the one Input of the NOR gate 536 is fed. The logic signals CYQLTO-, NOHIT +, CYREAD + and FEMPTY + 30 are the Inputs of a NOR element 501, the output of which is connected to an input of a NOR element 502, which on the output side is connected to the D input of the flip-flop 503 «The logic signal CYQLTO + OD occurs between the Output of a NOR gate 565 and the PRESET input of the flip-flop 503. The Q output link signal MEMREQ-des Flip-flops 503 is fed to one input of the NOR gate 502, and the logic signal MEMREQ + OC is the other Input of the NOR gate 502 supplied. The CLOCKO + signal is fed to the CLK input of flip-flop 503, its Q output logic signal MEMREQ + is fed to the RESET inputs of flip-flops 508, 509 and 504. The logic signal "1" is fed to the SET input of the flip-flop 508, whose Q output link signal DATCO is fed to the SET input of the flip-flop 509. The Q output link signal DATCTI of this flip-flop 509 is fed to one input of the NAND gate 510, its output logic signal MEMREQ RESET is fed to the input of a NOR element 566, the output of which is connected to the RESET input of the flip-flop 503

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is bound. The link signal CLEAR occurs between the System bus control 219 and the other input of the NOR gate 566 on.

The logic signals ADDRWD + OA and ADDRW + OB are fed to the inputs of corresponding inverters 523 and 524, whose output logic signals ADDRWD-OA or ADDRWD-OB are fed to the inputs of the AND element 533, which is connected on the output side to an input of the NOR element 527 is. The signal FIF041 + is fed to a further input of the NOR gate 527. The logic signal FEMPTY + 30 is fed to the inputs of the NOR element 526 and to the inverter 534, whose output logic signal FEMPTY-3Q is fed to a further input of the NOR element 527. The logic signal CYREAD is fed to the inputs of the NOR gates 526 and 527. The logic signal NOHIT + is fed to the input of an inverter 525 whose output logic signal CäHIT is fed to one input of the NOR element 526 D input of flip-flop 529 is connected. The Q output logic signal CYCADN + of flip-flop 529 is fed to the inputs of inverters 520 and 532. The output of the inverter 530 is connected to the input of a delay line 531, which is connected on the output side to the RESET connection of the flio-flop 529. The output link signal CYCADN- of the inverter 532 is fed to the interface unit 6 between the cache memory and the central unit. The CLOCKO + signal is fed to the CLK input of the flip-flop 5.19. The logic signal BANKED + occurs between the AOR and RAF control 235 and an input of a NAND element 560, which is connected on the output side to an input of the NOV. Element 536 and the PRESET input of the flip-flop 508. That

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Link signal CYQLTO- is the other input of the NAND element 560 supplied. The signal CYFIFO is fed to the other input of the NAND gate 510. The link signals CYQLTO + and CLEAR- are fed to the inputs of a NAND gate 561, which is connected to the inputs of the delay lines on the output side 562 and 563 and to an inverter 567 is connected. The output link signal CYQLTO + OB of the Delay line 562 is provided to the input of an inverter 564 and the AOR and RAF controls 235. The output link signal CYQLT0-1B of the inverter 564 is fed to one input of a NOR gate 565, its output logic signal CYQLTO + OD is fed to the PRESET input of the flip-flop. The output link signal CYQLTO + OC the delay line 563 is fed to the other input of the NOR gate 565. The output link signal CYQLTO-1A of inverter 567 is fed to AOR and RAF controls 235.

The link signals REPLACE and FIFO 17+ intervene the inputs of an AND gate 567 and the local register 204. The link signal CYWJRIT occurs between the FIFO read / write control 230 and the third input of the AND gate 567, whose output logic signal MEMREQ + OD the input of a NOR gate 569 and a NAND gate 570 is supplied. The output link signal MEMREQ + OC des NOR gate 569 is fed to one input of NOR gate 502. The logic signal BAR10 + 10 occurs between the Address register 207, the input of an inverter 268 and the other input of the NAND gate 570. The output link signal QLTDUN- of inverter 568 occurs at the other input of NOR gate 569. The output of the NAND gate 570 is connected to the RESET input of a flip-flop 571. The logic signal 1 is the input PRESET and fed to the D-f input, and the logic signal CLEAR- occurs

909828/0726

between the system bus line controller 219 and the CLK input of the flip-flop 571. The Q output link signal CYQLTO + is fed to the third input of the NOR gate 569, and the Q output linkage signal CYQLTO- is one input of AND gate 533 supplied. The link signal CLRREQ + OB occurs between the output of the NOR gate 536 and one input of the NAND gate 535. The logic signals MYDCNN + and BSDCND- are sent to the other inputs of the NAND gate 535 supplied.

During the normal request operation of the central processing unit 2, the first memory request cycle flip-flop 503 becomes with the occurrence of the signal CLOCKO + set, provided that the address PRA requested by the central unit 2 is not in the directory 202 is stored. The output signal of the NAND gate 231 according to FIG. 2, that is the logic signal NOHIT +, occurs at a high level and causes the output signal of the NOR gate 501 of FIG. 5 to be lower ■ level occurs. As a result, the output signal of the NOR gate 502 occurs with a high level, whereby the flip-flop 503 is set will. The Q output link signal MEMREQ + assumes goes high and sets the cycle request flip-flop 511 of the system bus controller 219 so that a bus line 5 cycle is requested. The acknowledgment response from the main memory 3, the logic signal BSACKR, occurs with a high level and causes the setting of the flip-flop ^ 504, whose Q output signal BLOCKF + the input side of the AOR and RAF control 235 is supplied. This operation will be described later.

If during the first memory request cycle a so-called "Hit signal" occurs, the logic signal NOHIT + supplied to the input side of the inverter 525 occurs with a low level

909828/0726

Level up. This makes the input link signal CAHIT of the NOR gate 526 occur at a high level, whereby the input signal for the NOR gate 528 occurs at a low level. The D input signal of the flip-flop 529 is thus brought to a high level. At this point the signal occurs FEMPTY + 3O with a high level, since the FIFO buffer 203 is empty. When the control signal CLOCKO + rises, the flip-flop 529 is set, and the Q output link signal CYCADN + goes high. This results in the output link signal CYCADN- of the inverter having a low level assumes, whereby the central unit 2 is signaled that the requested data are available. The link signal CYCADN + is inverted by inverter 530 and delayed by delay line 531 by 25 ns. Then that happens Reset flip-flop 529. If in the first memory request cycle a so-called "hit signal" has occurred is, then during the cycle within which the PRA data word from the main memory 3 to the cache memory 1 is sent via the bus line 5, the signal CYCADN + assume a high level again, as shown below follows. The read address multiplexer 233 shown in FIG. 2 gives output link signals ADDRWD + OB and ADDRWD + OA which appear low and which are generated by inverters 523 and 524 are converted into a high level, by means of which the output signal of the AND gate 533 is brought to a high Psgel, while the output of the NOR gate 527 at a low level and the output of the NOR gate 528 at a is brought to a high level. Flip-flop 529 is set as before. At this point the FIFO buffer 203 is not empty. The signal CYREAD occurs at a high level because the logic signal CYFIFO according to FIG. 3 is in cyclic operation is not brought to a high level.

■ 0982S / 072S

The flip-flops 508 and 509 are constructed as counters. In the case of an interleaved memory, the logic signal MYACKD goes high during each bus line 5 cycle, in which the data word from the main memory 3 to the cache memory 1 via the bus line 5 upon the occurrence of a request is sent out by the central unit 2. The link signal BSDBPL- takes for the second word of the two-word answer or a low level when only one word from main memory 3 is transferred to cache memory 1 the bus line 5 is sent out. Only one word can be sent to the cache memory 1 if the main memory 3 was occupied by the cache memory 1 at the second word request. Thereby the output signal of the NAND gate 506 assume a low level, whereby the output logic signal DATACK- of the NOR gate 507 with a low level will occur and causing the flip-flop

508 on the occurrence of the second recorded from the main memory 3 Word is set. The DATACK- signal increases during the trend the occurrence of the fourth word to a low level, since the signals MYACKD and BSDBPL- are again high Accept level and lead to the setting of flip-flop 509, since the SET input link signal DATCTO occurs with a high level. The Q output link signal DATCTI of the flip-flop

509 occurs high and results in the output link signal MEMREQ-RESET of the NAND gate 510 with low: level occurs. This causes the flip-flop 503 to go through the NOR gate 566 reset. The CLEAR input and the other input to NOR gate 566 go low Level up and also cause the resetting of the flip-flop 503. The flip-flop 503 was held in the set state, meanwhile, the input link signal M? MREQ- for the NOR gate 502 occurred with a low level. This made the SET input of the flip-flop 503 with each Ans feigen of the signal

ion u / 0721

CLOCKO + held high. If the main memory 3 emits the logic signal BSWAIT with a high level in response to the second memory request, then the output signal occurs of the NAND gate 505 with a low level, whereby the output signal DATACK- of the OR gate 507 with low Level occurs. As a result, the flip-flop 508 is occupied. Since the second memory requirement is ignored, if the main memory 3 emits the signal BSWAIT as a response signal, the data counter flip-flop 508 must be set because only two data words are received from the main memory 3.

When using a bank-like memory, the input combination ssignal BANKED + of the NAND gate 560 occurs with a high level on, whereby the output signal of the logic element in question occurs with a low level and to set of the PRESET input of flip-flop 508, as a result of which the Q output link signal DATCTO occurs with a high level. ■ Since the storage banking system only requires storage and since the cache memory 1 then received two data words, the second data word then becomes the flip-flop 509 set as stated above and reset flip-flop 503. The logic signal MEMREQ + assumes a low level and resets flip-flops 504, 508 and 509.

During a system initiation cycle, the link signal CLEAR- is transmitted via the bus line 5 to the receiver 217 according to FIG Fig. 2 transmitted as a negative pulse, by which the flip-flop 571 is set according to FIG. 5, namely on the rising Trailing edge. This causes the link signal CYQLTO + with a high level, and the logic signal CYWLTO-occurs with a low level.

909828/0726

The output of NOR gate 561 normally occurs at a high level. If the logic signals CLEAR and CYQLTO + occur at the input side of the NOR gate 561 with a high level / then the output signal of the relevant Logic element occur with a low level. 16o ns later the output link signal CYQLTO + OB occurs on the delay line 562 with a low level. As a result, the logic output signal CYQLTO-1B of the inverter 564 occur at a high level. This signal is fed to the input side of the NOR gate 565. The other input of the NOR gate 565, the logic signal CYQLTO + OC is supplied from the output of the delay line 56 3, which at this point in time occurs at high level and continues to occur for 40 ns at high level. This leaves the output link signal CYQLTO + OD at low level for 40 ns. Flip-flop 503 is set and the Q output MEMREQ + goes low goes high, as before, from a main memory 3 request cycle outgoing.

When the logic signal MEREQ + occurs with a high level, the cache memory 1 receives two bus line 5 cycle requests undertaken. In the course of the first request, the even-numbered address is sent to main memory 3, and in the course of the second request, the odd-numbered address is sent to the main memory 3. Through the first Data word that has been sent out from the even-numbered address memory location of the main memory 3 to the cache memory 1, the data counter, that is the flip-flop 508 according to FIG. 5, is set. With the second data word from the odd number Address memory space of main memory 3 in cache memory 1 cycle the data counter flip-flop 509 is set, the Q output link signal DATCTI of which causes the output signal of the NAND gate 510 occurs at a low level when the signal CYFIFO occurs at a high level. This will make that

909828/0726

Memory request flip-flop 503 reset which in turn resets the data counters flip-flops 508 and 509.

The input link signal occurs during the second data cycle FIFO17 + of the AND element 567, that is the low-order address bit stored in the register 204, with high level. The other input link signals CYWRIT and REPLACE also appear high, which causes the Output signal of the relevant logic element with a high Level occurs. This becomes the output link signal MEMREQ + OC of NOR gate 569 occur at a low level. This has the consequence that the output signal of the NOR gate 502 occurs at a high level. The next time the CLACKO + v / ¯ signal rises, flip-flop 503 is set, and the Q output signal MEMREQ + will again occur high, starting the next bus line 5 cycle request will.

The input link signal CYQLTO- of the NOR element 501, which occurs during the low level QLT operation simulates the "no hit" condition with respect to of directory 202.

When the 4096th word is requested from main memory 3, address storage location becomes 7777g in the address register 207 according to FIG. 2 increased by +1 with the aid of the adder 211. The next address 10000g is set in the address register 207, as will be seen below. The output line BA0R10 + carries a high signal level, whereby the input side of the NAND gate 570 according to FIG. 5 is driven accordingly. During the cycle, meanwhile the 4096 th 'data word from main memory 3 is transferred to cache memory 1 via bus line 5,

909828/0726

the input signals CYWRIT, REPLACE and FIFO17 + occur for the AND gate 567 goes high. As a result, an output logic signal occurs MEMREQ + OD high. As a result, the output signal of the NAND gate 570 occurs at a low level Level, which leads to the resetting of the flip-flop 571 and to the fact that the Q output link signal CYQLTO + with a low Level occurs. The input link signal QLTDUN- for NOR gate 569 occurs high and prevents flip-flop 503 from being reset after the 4096th Data word has been recorded. The logic signal CYQLTO- at the input of the AND gate 533 occurs with a low Level up and prevents the setting of the flip-flop 529 »

Detailed description of the system bus controller 219 - Fig. 5, Sheet 3 + 4

The link signals BSADO8-15, 16+ and 17- intervene the output of the receiver 213 and an AND gate 546, the output link signal MYCHAN to the SET input of the Flip-flops 516 is supplied. The signal BS ^ REF + occurs between the receiver 217 and the inverter 547, the output of which BSMREF- is fed to the AND gate 546 on the input side. The link signal BSDCNN + occurs between the Receiver 217, the cycle controller 232, the input of a delay line 52.2 and an input of an OR gate 521 on. The output of the delay line 522 is connected to the other input of the OR gate 521, its output logic signal BSDCNB + the AOR and FAF control 235 as well as the test and checking logic 240 and the RESET connection the flip-flops 514,516,536,574 and the AOR and BAF control 235 is supplied. The output signal of the Delay line 522 is also applied to the CLK terminals of flip-flops 516, 536 and 574. The link signal MYACKR occurs between the Q output of the

909828/0726

Flip-flops 516 and the input terminals of the delay lines 517,518, as well as the AOR "and RAF control 235, the FIFO read / write controller 230 and the driver circuits 218 on. The output of delay line 517 is at one Input of the AND gate 520 connected, the output logic signal MYACKD of the AOR and RAF control 235 and is fed to an input of the NAND gate 506 in the cycle controller 232. The output of delay line 518 is connected to the input side of an inverter 519, the output of which is connected to an input of the AND gate 520 is.

The logic signal "1" is the SET input of the flip-flop 536, the Q output link signal BSDCND- to one input of the NAND gate 535 in the cycle control 232 is supplied. The logic signal "1" is the PRESET input and the D input of the flip-flop fed. The Q output link signal CYREQ + of the flip-flop 511 is fed to one input of the NAND gate 513. The link signal BSBUSY occurs between the output of the NOR element 540 and the other input of the NAND element 513, whose output link signal SETREQ-an PRESET input of flip-flop 515 is supplied. The logic signal "1" is a PRESET input of the flip-flop 514 supplied. The link signal BSDCND + is fed to the D input and the RESET input. The signal MYDCNN-occurs between a Q output of flip-flop 541, the CLK input of flip-flop 514 and the enable inputs of the

. Driver circuits 212, 214 and 218. The Q output link signal MYRBQR + of flip-flop 514 is fed to the CLK input of flip-flop 515. The link signal CLEAR- is fed to the RESET input of flip-flop 515. The logic signals BSWAIT and BLOCKF- are the inputs of the AND gate 512 supplied, the output logic signal MYREQ + assigned to the D input of flip-flop 515

. . will lead. The Q output link signal MYREQT of the flip

909828/0726

SS

Flops 515 will drive circuit 218 and one Input of AND gate 542 supplied. The signal BSDCNB + is fed to the input side of an inverter 544, the on the output side is connected to the input of the AND gate 512, whose output link signal SETDCN- to the PRESET input of flip-flop 541 is connected. The link signals BSACKR and BSW / ν, Τ occur between the Inputs of the NOR gate 543 and the receiver 217. The output of the NOR gate 543 is at the RESET input of the flip-flop 541 connected. The signal CLEAR occurs between the output side of the inverter 573 and the input side of the NOR gate 543. The signal CLEAR- occurs between the input side of the inverter 573 and the receiver 217. The signal BSDCNB- occurs between the output of the Inverter 544 and an input of the AND gate 538. The BSREQT + signal occurs between the input of the AND gate 538 and the receiver 217, and the signal CLEAR is fed to the input side of the AND gate 538, which is connected on the output side to the input of the delay line and to an input of the NOR gate 54o. The output of the delay line 539 is connected to the other input of the NOR gate 54o. The Q output link signal MYDCNN + of the flip-flop 541 is the driver 218 and the input of the NAND gate 535 in the Cycle control 232 is supplied. The output link signal BSDCNB- the NOR gate 53 6 is the input of the NAND gate 535 supplied. The priority combination signals BSAUOK-BSIUOK occur between the inputs of the AND element 542 and the receiver 217.

The logic signals MEMREQ + and CLRREQ-OA intervene of the cycle controller 232 and the inputs CLK and RESET .of the flip-flop 512. The link signal BSDBPL + occurs between the SET input of flip-flop 574 and the receiver

909828/0726

217 on. The Q - output of the flip-flop. 574 is connected to cycle controller 232.

During the first memory request cycle, in the event that the central processing unit 2 requests data that is not contained in the cache memory 1 is the input signal MEMREQ + CLK of flip-flop 511 assume a high level, whereby the Q output link signal £ YREQ + will appear with a high level, that of the input side of the NAND gate 513 is fed. The link signal BSBUSY- also occurs high level when the bus line 5 is not busy; the output link signal SETREQ- of the NAND gate 513 occurs with a low level, whereby the flip-flop 515 is set whose Q output signal MYREQT assumes a high level and an input-side control of the one bus line 5 cycle requesting AND gate 542 causes. If bus line 5 does not have a high priority request, then the logic signals BSAUOK to BTIUOK occur with a high Level up. If the bus line 5 does not transmit any information / then the link signal BCDCNB- occurs with a high level, and the logic output signal SETDCN- of the AND element

542 occurs low. This sets flip-flop 541 and Q output MYDCNN + goes high Level up. As a result, the driver circuits 212, 214 and 218 are correspondingly controlled, thereby being connected to the bus line 5 information is output in the format shown in FIG. 8b. When the main memory 3 receives the information from the Bus line 5 picks up, it sends the acknowledgment link signal BSACKR via bus line 5 to the cache memory back and causes the resetting of the flip-flop 541, namely by the fact that the output signal of the IOR gate

543 is brought low. The Q output link signal MYDCNN-causes the setting of the flip-flop 514 on occurrence with a high level, the one with a high level

909828 / Q726

9ο

occurring Q output linkage signal MYREQR + das Flip-flop 515 resets because the D-input oversignal MYREQ occurs with a low level. This has to As a result, the Q output link signal MYREQT occurs with a low level. One from main memory 3 again emitted signal BSWAIT indicates that main memory 3 is occupied. Furthermore, the flip-flop 541 is reset, since the output of the NAND gate 543 occurs at a low level. Since the output of the AND gate 512 but occurs at a high level when the flip-flop 514 is set, and since the Q output link signal MYREQR + occurs with a high level, the Q output link signal remains MYREQT of flip-flop 515 is high and the first memory request is repeated.

If, in the interleaving mode, the main memory 3 acknowledges the first memory request by sending out the link signal BSACKR, the flip-flop 511 remains set State in which the Q output link signal · CYREQ + appears with a high level. This becomes the second Memory request cycle started. The flip-flop 511 remains set during the interleaving operation State, since the output signal of the NAND gate 535 remains at a high level, as is the case for the CLK input signal MEMREQ + applies. The input signal CLRREQ + OB of the NAND gate 535 occurs at a low level as long as like the input signal BLOCKF- of the NOR-GIi3des 536 with high Level occurs. The logic signal BLOCKF- occurs η'ich Occurrence of the first acknowledgment signal BSACKR with low Level up. When the MYDCNN + signal goes high during the second memory request cycle, will the flip-flop 511 is reset because the signal BLOCKF- is low.

However, when the system is in the memory bank mode, the flip-flop 511 is reset, namely the

909828/0726

The output signal of the NAND gate 53 5 in the cycle controller 232 assumes a low level at the end of the first memory request cycle. The input logic signal CLRREQ + OB of the NAND gate 535 has a high level, whereby the output logic signal CLRREQ-OA of the NAND gate 535 has a low level when the signal MYDCNN + assumes a high level. A second memory request cycle begins when the input link signal BSREQT of the AND gate 538 assumes a low level and when there is no request with respect to the bus line 5. As a result, the output of the AND gate 538 will appear at a low level, whereby the input signal of the NOR gate 54o will appear at a low level. 2o ns later, the other input signal of the NOR gate 54o also assumes a low level, as a result of which the output link signal BSBUSY- is given a high level. It should be noted that normally the CLEAR signal occurs at a high level and a low level with respect to Rückset'zfunktionen obtained during system initialization. If both input signals of the NAND gate 513 have a high level, the output link signal SETREQ occurs with a low level, whereby the Q output link signal MYREQT of the flip-flop 515 is set to a high level again. This requests a bus line 5 cycle. The output link signal SETDCN- of the NAND gate 542 occurs again with a low level, whereby the flip-flop 541 is set. The Q output link MYDCNN +. then occurs at a high level, as a result of which the driver circuits 212, 214 and 218 are controlled in such a way that the second memory request is sent out to the main memory 3 via the bus line 5 in the format shown in FIG. When the main memory 3 returns the handshake signal BSACKR, the flip-flop 541 is reset as before. This sets flip-flop 514 and resets flip-flop 515. As a result, the

909828/0726

Q output link signal MYPEQT of low level occurs. The input link signal JlYDCNN + of the NAND gate 535 occurs with a high level, whereby am RESET input of the flip-flop 511 a low level occurs. This then causes the Q output linkage signal to appear CYREQ + with a low level. In this way the delivery of subsequent memory request bus line 5 cycles is avoided. The input logic signal CLEAR of the NOR gate 543 also causes the reset of the flip-flop 541.

If the main memory 3 were occupied and in answer would send back a logic signal BSWAIT in response to a second memory response, the flip-flop 541 would be reset because the logic signal BSWAIT assumes a high level. This makes dinn the output signal of the NOR gate 543 occur at a low level. Furthermore, the Q output link signal MYDCNN- is des Flip-flops 541 occur with a high level, whereby the flip-flop 514 is set. The Q output link signal MYREQR of this flip-flopr will then assume a high level. The D input signal of the flip-floj rs 515 leads a low level because the logic signal BLOCKF + is high at this point. As a result, the output of the NOR gate 572 occurs at a low level on. As a result, the output link signal MYREQ + of AND gate 512 occurs at a low level. If the logic signal MYREQ + assumes a high level, the flip-flop 515 is reset. This makes the Q output link signal MYREQT low Level set or brought. Since the flip-flop 511 was reset during the second memory request cycle / As before, the second memory request is ignored. In the QLT operation, however, the input link signal occurs CYQLTO- the NOR gate 572 with low

909828/0726

93 2Bb5730

Level, whereby its output signal has a high level. If the response signal BSWAIT is asserted, then the output signal of the AND gate 512 occurs with a high Po.gel, whereby the flip-flop 515 is set. That with a high Level occurring Q output link signal MYREQT begins another memory requirement.

The flip-flops, 5o3, 5o4, 5-11, 514, 515, 529, 541 and 571 are circuits with the designation 74S74 as they are described on page 5-22 of the above mentioned TTL data book. the Flip-flops 5o8 and 5o9 are logic circuits of the designation 74S112 as they are on page 5-34 of the relevant Data book is described, and the flip-flops 516, 536 and 574 are logic circuits of the designation 74S175, v / ie it is described on page 5-46 of the relevant data book.

The main memory 3 sends the link signals BSDCNN + and the information in the format shown in FIG. 8c via the bus line 5 to the receivers 213, 215 and 217. The • information is keyed into the FIFO buffer 2o3. The input signal BSAD o8-17 is fed to the AND gate 546 together with the logic signal BSMREF-, which has been inverted by the inverter 547. If the cache memory 1 identification is given with ooo2g, then this means that the signals BSAD16 +, BSAD oo-15 and 17- are high and that there is no write operation relating to main memory 3, which means that the signal BSMREF - occurs at a high level. In the case, the output logic signal of the AND gate 546 MYCHAN occurs with high ⁿ egel. The logic signal BSDCNN + occurring at a high level causes the output logic signal BSDCNB + of the OR gate 521 to appear at a high level. As a result, the RESET input signal of the flip-flop 516 also occurs with a high level. The link signal BSDCNN + is delayed by the delay lines 522 by 60 ns and causes the to be set

909828/07 26

Flip-flops 516 whose output link signal MYACKR when the level occurs, the FIFO write address counter advances flip-flops 32o and 321 according to FIG. This operation has been described above. The logic signal MYACKR, which occurs at a high level, causes this Set the flip-flop 3o5 according to FIG. 3. The Q output link signal INTERG + goes high and causes data to be transferred through the buffer bypass drivers 2o5 according to FIG. 2 to the connection point 216, since this first data word from the main memory 3 is issued in response to the request from the central unit 2. The link signal MYACKR also occurs on the Bus line 5 to acknowledge the main memory 3 that the cache memory 1 has sent out the main memory 3 and has received information addressed for the cache memory 1. According to FIG. 5, the logic signal MYACKR is through delay line 517 delayed by 20 ns. The input of the AND gate 52o, the output logic signal MYACKD 2o ns after the signal rise of the signal MYACKR assumes a high level. The link signal MYACKR is delayed by 40 ns by delay line 518 and the other input after inverting by inverter 519 of the AND gate 52o at a low level. The link signal MYACKD is a positive one that lasts 20 ns Pulse delayed by 20 ns from the rise of the MYACKR signal. The link signal MYACKD delays the setting of the Function code development flip-flops 512 and 513 according to FIG. 4 until the one received from the bus line 5 'Data have been brought into the FIFO buffer 2o3.

The sequence described above is used in the nesting operation repeated for the four cycles within which the data words from the main memory 3 to the cache memory 1 in response to the first and second storage requests. In memory bank operation, the sequence is during two cycles for the occurrence of a memory request

909828/0726

ir *
repeated.

Formats on the system bus line - 5

FIG. 8 illustrates the formats used on the system bus line 5, which are from the cache memory 1 and / or the main memory 3 are processed. 8a. Shows the memory address field with an 18-bit main memory word address BSAD o5-22 of a 20-bit data word BSDT oo-15, A, B, DSDP oo, o8. This format is used by the central unit 2 to transfer the main memory 3 via the system bus line 5 to update. The cache memory 1 reads the address and data in the FIFO buffer 2o3 from the system bus line 5 via the Receivers 213, 215 and 217. The cache memory 1 determines that the logic signal BSMREF occurs at a high level, whereby it is indicated that the address field contains an address relating to the main memory 3. Furthermore, the cache memory determines that the BSWRIT; n signal is high, indicating that this is a write operation. It is also checked whether the address memory location is written into the cache memory 1. If the address is in the directory 2o2 has been found in accordance with FIG. 2, then the data word stored in the data memory 2o1 is updated. if the address is not found in the directory 2o2, then the data is given up or ignored. One The peripheral control device can have a 19-bit byte main memory address Send out BSAD o5-23. In this case, cache memory 1 would update byte ο or byte 1, if any byte is stored in the data buffer 2o1.

The main memory request which is sent out from the cache memory 1 to the main memory 3 is illustrated in FIG. 8b. The address field contains the word address BSAD o5-22 of the main memory 3. The data field contains the 12-bit identification code ooo2 ₈ relating to the cache memory 1, namely

BSDT A, B, oo-o9, and the 6-bit function code oo ₀

909828/0726

ο1 _ο . The function code oo _Q identifies the bus cycle as the first memory request cycle. The function code o1η identifies the bus line cycle relating to the bus line 5 as the second memory request cycle. The signal BSMREF occurs with a high level, since it is a request from the main memory 3.

In FIG. 8 c, the response format of the main memory 3 to the memory read request according to FIG. 8 b is illustrated. The address field contains the destination number of the cache memory 1, namely ooo2 ", and the function code oo", whereby a response to a first memory request or the function code o1 _R are identified. This defines a response to a second memory request. The signal BSWAIT + indicates that the main memory 3 is requesting the cache memory 1 in order to write the data word in the cache memory at the address which is indicated by the main memory read request indicated in FIG. 8b. The BSSHBC signal is high, indicating that this is a response to a memory request. A main memory request occurring in the interleaving mode in the format shown in FIG. 8b contains the signal PPA for the first request address and the signal PRA + 1 for the second request address. The main memory 3 responds with the data words PRA and PRA + 2 to the first request and with the data words PRA + 1 and PRA + 3 to the second request.

A main memory request occurring in memory bank operation contains the data word PRA in the format shown in FIG. 8b. The main memory 3 responds with the data words PRA and PRA + 1.

909828/0726

-28G5730 -96 -

Circular writing device 224 - FIG. 6

The link signal CYWRIT occurs between the FIFO read / write control 23o, the inputs of delay lines 6o3 and 6o5 and the CLK inputs of the flip-flops 61o and 611. The output of the delay line 6o3 is connected to the input of an AND element 6o4. Of the The output of the delay line 6o5 is connected to an input of an inverter 614, the output of which is connected to the other AND gate 6o4 is connected. The output of the AND gate 6o4 is at the inputs of an inverter 6o6 and a NAND gate 6o7 connected. The output of the inverter 6o6, which carries the logic signal WRTPLS-, is at the enable connection ENABLE of the 2: 1 multiplexer 223 connected. The link signal REPLACE occurs between register 2o4, the other input of the NAND element 6o7 and the selection connection SELECT of the 2: 1 multiplexer 223. The output link signals LEVELO-3 + of AND gate 613a-d become the "1" input terminals of the 2: 1 multiplexer 223 is supplied. The output link signal RNDWRT- of the NAND gate 6o7 is fed to the write enable connections of the memories 6o1 and 6o2, which Random access memories are and their read enable ports are grounded.

The signal lines ADDR o8-17 + are between the 2: 1 multiplexer 2o8 and the address selection terminals of the RAM memories 6o1 and 6o2. The logic signal RNDADD + occurs between the NOR / AND element 612 and the data input of the RAM memory 6o2, the data output of which is ROUNDO + OA is connected to the D input of a flip-flop 61 o.

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The link signals BAOR 11 + 1 ο and BAOR 12 + 1 ο occur between the address register 2o7 and the inputs of a NOR element 608, whose output link signal ROUNDR-dem D input of a flip-flop 6o9 is fed. The FIFO link signal occurs between the FIFO quiet / write control 23o and the CLK input of the flip-flop 6o9. The Q output link signal ROUNDO-OR becomes the CLR inputs of the flip-flops 61 o and 611 supplied. That Link signal CYQLTO + occurs between the cycle controller 232 and the CLR input of the flip-flop 609.

The output Q of the flip-flop 61 ο leading the logic signal ROUNDO + is at the inputs of the NOR / AND element 612, of AND gate 613c and AND gate 613d connected. The output Q leading the logic signal ROUNDO is comprehensive at the inputs of the 2-NOR element and the AND element Logic element 612, the AND element 613a and the AND element 613b connected. The Q output of the flip-flop 611 carrying the logic signal R0UND1 + is at the inputs of the logic element 612 comprising a NOR element and AND element, the AND element 613b and the AND element 613d connected. The Q output leading the logic signal R0UND1 is at the inputs of the two NOR elements and a logic element 612 having an AND element, the AND element 613a, the AND element 613c and at the data input of the RAM 6o2 connected. The data output of the RAM memory 6o2 gives a logic signal R0UND1 + 0A to the D input of the Flip-flops 611 off.

The signal lines HITO-3 + run between the outputs COMPARE 221a-d and the 0 port of the 2: 1 multiplexer 223. The signal lines WRITEO-3 run between the connector 2 of the 2: 1 multiplexer 223 and the data buffer 2o1 as well as the directory 2o2.

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The circular writer 224 selects the next level of the data buffer 2o1 and directory 2o2 accordingly Fig. 2, in which new information is written. The relevant circulation device 224 shows the oldest information relating to the column address ADDRo8-17. Included is the information available for exchange.

The two 1-bits from the 1o24 RAM memories 6o1 and 6o2 are set to level ο for the respective column address. This means that the 1024 addresses in the RAM memory 6o1 and the 1o24 addresses in RAM 6o2 during QLT operation can be set to O.

At the beginning ', the logic signal CYQLTO + occurs at the CLR input of the flip-flop 6o9 with a high level. The two input link signals BAOR 11 + 1 o and BAOR 12 + 1 o of the NOR element 6o8 are given low levels, as a result of which the output link signal ROUNDR- occurs at a high level. When the logic signal CYFIFO assumes a high level, the ¹ flip-flop 6o9 is set and the Q output logic signal ROUNDO-OR assumes a low level, whereby the setting of the flip-flops 61o and 611 is prevented. The logic signals ROUNDO - and ROUNDi - have a high level, as a result of which the output logic level LEVELo + of the AND element 613a is given a high level.

The two input link signals ROUNDo- and R0UND1-for which includes the two NOR elements and an AND element Logic element 612 have a high level, as a result of which the output logic signal RNDADD + occurs at a low level will. Accordingly, it becomes the data input to the RAM memory 6ot occur at a low level. Since the Q output link signal R0UND1- of the high level flip-flop 611 occurs

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the data input to the RAM memory 6o2 at high level.

During the QLT operation, the first 4o96 in the Main memory 3 written data words contained in the data buffer 2o1, and the corresponding line addresses ADDRoo-o7-1o of the relevant data words are stored in the Directory or table of contents 2o2 inscribed. The first 1o24 data words with their line addresses are written in level ο, the second 1o24 data words with their line addresses are written in level 1, the third 1024 data words are grounded with their Line addresses are written in level 2 and the last 1o24 data words are entered with their line addresses in the Level 3 enrolled. The levels concerned are stored in the RAM memory 6o1 and 6o2 of the Uniaufeinrichtung selected.

The logic signal occurs for each of the first 1024 write cycles CYWRIT at the input of delay lines 6o3 and 6o5 with a high level. That happens later Output of the delay lines 6o3 at a high level. The two input signals of the AND element 6o4 are high and the output link signal WRITPLS + occurs high. The signal REPLACE occurs with a high level in QLT operation. This receives the output logic signal RNDWRT- of the NAND gate 6o7 has a low level, as a result of which the write function of the RAM memories 6o1 and 6o2 is enabled. The output signal of the inverter 6o6, that is the logic signal WRTPLS-, occurs low and enables the 2:! Multiplexer 223. 5o ns later the output of the delay line ^ o5 with high Level, whereby the output signal of the inverter 614

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JM

occurs at a low level. As a result, the AND gate 6o4 emits an output signal with a low level, whereupon the output link signal WRTPLS- of inverter 606 high occurs. The output link signal RNDWRT- des NAND gate 6o7 occurs high, causing the write enable pulse is finished.

In the 1024 consecutive addresses of the RAM memory 60I only zeros are introduced and in the 1024 consecutive Addresses (0-1o23) of the RAM memory 6o2 are introduced only with ones.

If the address 1o24 (2ooog) is stored in the address register 2o7, the signal BAOR 12 + 1 o occurs with a high level, as a result of which the NOR element 608 emits an output logic element ROUDNR with a low level. When the logic signal CYFIFO occurs at a high level, the flip-flop 609 is reset and the Q output logic signal ROUNDO-OR occurs at a high level. The flip-flops 6I0 and 611 are now activated. The address oooog of the RAM memories 60I and 6o2 is selected with the signal ADDR08-I8 +. The data output signal, namely the logic signal ROUNDO + OA, occurs at a low level and the logic signal ROUND1 + O £ occurs at a high level. When the logic signal CYWRIT assumes a high level, the flip-flop 611 is networked and reads the Q output. Linking signal ROUNDH- occurs with a high PcK / el. In the case of a high level logic logic R0UND1 + and ROUNDO-, the output pre-link iingaMigna L IFVEL 1+ of the AND element 613b is selected. In addition, the output signal of the NOR / AND equation occurs every; 612 with a high level autf, whereby a ¹ M "in the RAM G0I and a: "<■>" in the ΡΛΜ memory 6o2 under the AdriifjHu 0OO., Eino: schri <-bc-n.

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This sequence continues until 1o24 storage locations level 1 in data buffer 2o1 and in directory 2o2 are filled; the RAM 6o1 stores as a whole Ones and the RAM memory Go2 stores a total of zeros.

The logic signal BAOR 11 + 1 ο occurs with a high level for the transfer of data words to addresses 2o48 to 4o96, with the flip-flop 6o9 held in the reset state remain. For writing the third 1o2l data words with The flip-flop 61 ο and the flip-flop 611 remain set to their line addresses in the dcitenbuffer 2o1 and the directory 2o2 reset. In this case, the output link signal LEVEL 2+ of the AND gate 613c occurs with a high level. During this third sequence, ones are written into all addresses of the RAM memories 6o1 and 6o2.

During the fourth sequence, the flip-flops 61o and 61o are set, as a result of which the output link signal which occurs at a high level LEVEL3 + of AND gate 613d is selected. This leads to a total of zeros in the RAM memory 6o1 and 6o2. During the sequence, during the 4o96. Data word from the main memory / is transferred and written into the cache memory 1, the logic signal CYQLTO + occurs with a low level, whereby the flip-flop 6o9 is reset. This enables the flip-flops 61 o and 611 for the subsequent replacement operation.

The flip-flop 6o9 is a logic circuit called 74S74, as it is written on page 5-22 of the above-mentioned data book! The flip-flops 61 o and 611 are logic circuits with the designation 7 4S175, as described on page 5-46 of the above-mentioned data book. That NOR / AND gate 612 is a logic circuit called 74LS51, as described on page 5-16 of the above mentioned data book.

■ 909828/0726

Test and Check Logic - Fig. 1 0.

The logic signals MYACKR and BSDCNB + occur between the system bus controller 219 and the CLR and RESET connections of one Flip-flops 150 on. The link signal BSSHBC + occurs between the receiver 217 and an inverter 62, whose output link signal BSSHBC- is fed to the D input of the flip-flop 50. A link signal 1 is fed to the input PRESET of flip-flop 50, the Q output logic signal BSSHBH is fed to the inputs of AND gates 51, 57 and 58. The logic signals BSDT08, BSDT14 and BSDT12 occur between receiver 217 and the other inputs of the AND gates 151, 57 and 58 respectively.

The output of AND gate 150 is at the CLK terminal of the Flip-flops 52 connected. The output of the AND gate 57 is connected to the CLK connection of the flip-flop 59. Of the The output of the AND element 58 is connected to an input of an OR element 60. The link signal BSMCLR occurs between the receiver 217 and the other input of the OR gate 60, whose output link signal CLEAR + dem Input of an inverter 161 is supplied. The output link signal CLEAR- is sent to the cycle controller 232, the The PRESET terminal of the flip-flop 59 and an input of a NOR gate 54 are supplied. The logic signal MEMREQ + occurs between the cycle controller 232 and the input of a NAND gate 53 and the input of a NAND gate 55. The link element CACHRQ + occurs between the interface 6 between the cache memory and the Central processing unit CPU is provided, und'dem input of an inverter 56 and the input of a NAND element 55. That Output link signal CACHRQ- of the inverter 56 is the

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The input of the NAND gate 53 is supplied, the output of which is connected to the input of the NOR gate 54. The exit the NOR gate 54 is connected to the RESET terminal of the flip-flop 52. The one leading the logic signal TESTMD The Q output of the flip-flop 52 is connected to the input of the NAND gate 55, the logic signal of which CNOMEM- leading output at the RESET connection of the flip-flop 59 and at the interface unit 6 between the cache memory and the central processing unit CPU is connected. The Q output link signal CACHON of the flip-flop 59 becomes the interface unit 6 is supplied. The link signals BSDTO9 and BSDT15 occur between the receiver 215 and the D inputs of the flip-flop 52 and 59, respectively.

The central unit 2 begins a T + V cycle in that it sends information to the bus line 5. The information includes cache identification 0002g, the Data bits BSDT3, 9, 12, 14 and 15, the low level memory reference size BSMREF and the second half logic signal BSSHBC + with low level indicating the bus cycle.

The cache memory 1 receives in the course of its normal monitoring the bus line 5, the information, as has been described above. The cache identification bits are supplied to the input side of the AND gate 546, and the output signal MYCIIAN appears at a high level, since the Logic signal BSDCNN + occurs with a high level. The output link signal BSDCND + of delay line 522 goes high, causing flip-flop 516 to be set will. The Q output signal MYACKR of this flip-flop then occurs with a high level, whereby it is acknowledged that the cache memory 1 has received the information that has occurred on the bus line 5.

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The link signal MYACKR at the CLK input of the flip-flop 50 of FIG. 10, when it occurs at a high level, causes the flip-flop 50 to be set, and the Q output link signal BSSHBH goes high.

During normal operation, the main memory 3 sends the data word requested by the cache memory 1 with the Cache ID 0002g, and the ^ nit high Line signal BSSHBC occurring at level indicates that this is the second half-bus line cycle in response is a memory request.

When the high level data bit BSDT12 occurs, this indicates indicates that the central processing unit 2 is requesting an initialization of the cache memory and that the 409 6 words of low significance of the main memory 3 are to be transferred into the cache memory. Then the output signal of the AND gate 58 occurs high level, which also causes the output of the OR gate 60 occurs at a high level. The logic signal CLEAR +, which occurs at a high level, causes the output logic signal CLEAR- of the inverter 61 occurs at a low level. If the data bit BSDT12 at the end of the Bus line 5 relevant bus line cycle assumes a low level, the logic signal CLEAR occurs with a high Level, whereby the flip-flop 571 of FIG. 5 is set. This gives the Q output link signal CYQLTO + given a high level, thereby starting the QLT cycle. The flip-flop 50 shown in FIG. 10 is at the end of the relevant Bus line cycle reset when the logic signal BSDCNB + occurs at a low level.

The central unit 2 sends the data bit BSDT12 in T + V mode with a high level, which means that in the cache memory 1 the first 4096 address storage locations from the Main memory 3 can be loaded.

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The central unit 2 now sends the T + V information to the bus line 5 in order to make the cache memory 1 independent of the computer close. In this case, the high level data bit BSDT14 and the low level data bit BSDT15 appear. Since the logic signal BSSHBC + occurs at a low level, the flip-flop 150 is for the bus line cycle duration described above set again. When the Q output link signal BSSHBH goes high, occurs the output of the AND gate 57 at a high level, whereby the flip-flop 59 is reset. The Q output signal If the level occurs, CACHON signals to the central processing unit 2 that the cache memory 1 is computer-independent is. The flip-flop 59 was at the beginning of the QLT cycle been set when the logic signal CLEAR- applied to the PRESET input occurred with a low level.

A number of tests are now possible. The central unit 2 can check whether or that the directory 202 the .Saves line addresses of the first 4096 address storage locations in main memory 3.

The central processing unit 2 causes the cache memory line request signal CACHRQ to appear at a high level and, as shown in FIG. The first address memory location sent by the central unit 2 to the cache memory 1 is given by 000000g. The column _{address 0000 g} is read out from a corresponding memory location on each of the four levels. The output signal is compared with the line address 000 «. In this case, level 0 stores row address 000g. As a result, the output of the comparator 221A becomes high

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on, whereby the output logic signal NOHIT + of the NAND gate 231 occurs with a low level.

The logic signal CACHRQ, which occurs at a high level, as shown in FIG. 3, causes the flip-flop 3 to be reset 13, - and the occurrence of the Q output signal FEMPTY-20 leading to a low level begins the cyclical occurrence of the timing signal CLOCKO +. The rise of the CLOCKO + signal sets the flip-flop 529. That with logic signal NOHIT + occurring at low level causes the output signal of the NOR gate 526 with occurs at a low level. As a result, the D input of the flip-flop 529 is supplied with a high level signal. That The Q output link signal CYCADN + causes the output link signal CYCADN-des when it occurs at a high level Inverter 532 occurs at a low level. This signal picked up by the central unit 2 indicates that the line address sent to the cache memory 1 was stored in the directory 202, namely under the related to of the cache memory 1 specified column address.

Cyclically running through the 4096 address memory locations above Sequence, all address storage locations in all levels of directory 202 are checked.

If there was a "NOHIT" response signal indicating that the variables compared with one another did not match, i.e., if directory 202 does not have a row address stored, then the output link signal is asserted NOHIT + of the NAND gate 531 according to FIG. 2 occur with a high level. This is the output of the NOR gate 501 of FIG. 5 occur with a low level, whereby the output signal of the NOR gate 502 appear with a high level becomes ... When the CLOCKO + signal rises. will that Flip-flop 503 is set, and the Q output link signal MEMREQ + occurs at a high level, whereby, as above

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wrote, a bus line cycle relating to bus line 5 is requested.

According to FIG. 10, the central unit 2 had previously sent a T + V cycle via the bus line 5, the signal bits BSDTO8 and BSDTO9 occurring at a high level and the logic signal BSSHBC + at a low level. The flip-flop 50 is set again, and when the Q output link signal BSSHBH occurs high, the flip-flop becomes 52 set. The input signal bit BSDTO9 occurring at the D input occurs with a high level when the output signal of the AND gate 51 is given a high level, whereby the flip-flop 52 is set. The flip-flop 52 becomes is set to test the error logic circuit that responds when no match occurs.

When the three input signals of the NAND gate 55 occur with a high level, the output link signal takes CNOMEM- a low level, whereby the central processing unit 2 is signaled that the transmitted to the cache memory 1 Line address was not in cache 1. The three input signals appearing at a high level of the NAND gate 55 indicate that the NOHIT fault test operation (TESTMD) was effective that the central unit also requested a main memory address (CACHRQ +), and that the Line address was not stored in the directory (MEMREQ +).

If the central unit 2 picks up the logic signal CNOMEM- occurring at a low level, this indicates a no match reporting error. The central unit 2 causes the link signal CACHRQ + with low Level occurs. As a result, the output of the inverter 56 as shown in FIG. 10 appears at a high level. There

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the logic signal MEMREQ + occurs at a high level, the output signal of the NAND gate 53 takes a low Level, whereby the NOR gate 54 emits an output signal with a low level. This resets the flip-flop 52. The logic signal CNOMEM-, which occurs at a low level, also resets the flip-flop 59, whereby the cache memory 1 is brought into the bypass mode.

The central unit 2 controls by means of the signal bits BSDT14 and-BSDT15 causes flip-flop 59. During T + V operation when flip-flop 50 is set and when the Q output signal occurs BSSHBH with a high level, the signal bit BSDT15 that the D input of the flip-flop 59 has a high signal level. As a result, the cache memory 1 is so to speak switched on to the relevant line, while at a low level leading D input of the relevant flip-flop, the cache memory 1 is controlled independently of the computer, if the dem • CLK input of the flip-flop 59 supplied output signal of the AND gate 57 occurs with a high level.

In a corresponding manner, the central unit 2 controls the flip-flop 52 in the via the signal bits BSDTO8 and BSDTO9 T + V operation. The signal bit BSDTO9 results in the connection D of the flip-flop 52 is high, thereby discontinuing the error mode indicating no match becomes, while when the corresponding low-level signal occurs, the signal that does not indicate a match Error operation is reset. When the Q output link signal BSSHBH of the flip-flop 50 occurs with a high level, the flip-flop 52 is set, provided that the CLK input of the flip-fl-ps 52 supplied output signal of the AND gate 51 occurs at a high level.

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The flip-flops 50, 52 and 59 are logic circuits with the designation 74S74, as described on page 5-22 of the TTL data book mentioned above.

Description of operation - test and test mode The central unit 2 controls the test and test (T + V) logic of the system components, including the cache memory, two instructions relating to the central unit 2, the copy register for A (CRA) and the Copy A for the register (CAR) to allow T + V access to registers and the control associated with central processing unit 2.

Two types of CRA commands are available for testing the cache memory 1, namely loading the cache memory and storing the cache.

When the cache memory is loaded, the Α register 2a according to FIG. 2 in the central processing unit 2 contains those from the main memory 3 Number of words to be transferred to the cache memory 1. The index register 1 2b stores the stick address of the segment of main memory 3 to be loaded into cache memory 1.

The central unit 2 requests a data word from the cache memory 1 by sending to the cache memory 1 via the private interface 6 between the central unit and the cache memory sent out a cache memory request signal will. The main memory 3 address is stored in index register 1. The cache memory 1 requests this Data word from the central unit 2 from the main memory 3 via the bus line 5. The main memory 3 sends this Data word to the cache memory 1, where da3 relevant

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Data word is stored in the data buffer 201, and also the relevant data word is sent to the central unit 2 sent out. The central unit 2 ignores the data word and increases the content of the index register 1 2b and reduces the content of register A 2a. The above operation is repeated until the content of the register A 2ä is counted down to zero. The central unit 2 then terminates the command by connecting the system bus line 5 relevant system bus line transmission from of the central processing unit is executed towards the cache memory, whereby the cache memory is in a bypass mode is brought, i.e. made "computer independent". It is now possible to load the cache memory 1 used segment of the main memory 3 to change without destroying the content of the cache memory 1.

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In the cache storage mode, the Α register 2a contains the number of times to be read from the cache memory 1 and in the main memory 3 stored words. The index register 2 2c contains the main memory 3 relevant start address for the access to the main memory 1. The index register 3 contains 2d the start address relating to the main memory 3 for the storage of the data words from the cache memory 1 are read.

The central processing unit 2 performs the cache memory bypass operation reset, which means that the cache is "hosted" and that there is no match indicating error mode is set. The central unit 2 requests a data word from the main memory 1 Use of the address which is stored in the index register 2 2c, and causes the data word to be stored in that memory location of the main memory 3 which is designated by the index register 3 2d. After each cycle the The content of the Α register 2a is reduced and the content of the index registers 1 2b and 2 b is increased in each case. When the logic signal CNOMEN- occurs at a low level, this indicates that the requested data word is in the cache memory 1, the relevant signal being sent to the central unit 2 will. The CPU 2 is performing an illegal storage operation indicating that a hardware directory error exists. Since the processing of errors in the central unit is not part of the invention, it will not be discussed further.

If no error occurs, there is no match between them compared sizes or no hit, then the above cycle is repeated until the content of the A register 2a has been reduced to zero, whereupon the Central unit 2 transferred the cache memory to a bypass operation. In addition, on the next command, the test

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/ 115

program output.

Therefore, under the control of the central processing unit 2, utilizing the CRA instructions, the cache memory 1 becomes a main memory 3 loaded. The cache memory 1 is then unloaded into a further part of the main memory 3. If not If an error indicating a match did not occur, the central unit 2 compares the data words in the two areas of the main memory 3 with regard to the occurrence of discrepancies. An arrangement contained in the cache memory 1 is checked under the control of the central unit 2, whether or that data word address storage locations are written into the cache memory 1 and also cache memory 1 becomes at the eligible times during the above sequence Made "computer-independent" or "computer-dependent".

For the purpose of explaining the present invention, it should be noted that that the operations identified by the above CRA instructions are conventional operations. The copy A of the register (CAR) instructions, which initiate the test and inspection operation, is illustrated in Fig. 1o.

The CAR commands that are requested by the central processing unit 2 of the cache memory 1 are listed in the table below.

Management states

12 14 15

CAR commands BSDT
8th signal
9 Resetting the No.
Hit failure 1 O Setting the no hit
Error 1 1 Cache memory
initiation - - Cache memory
byway Resetting the
Cache memory
By the way Q Π Q P 9 0 / (179

It should be pointed out that each control function has a separate bus line cycle relating to bus line 5 requires, in which the logic signal BSSHBC + occurs with a low level.

The test and inspection operation begins in block 15o according to FIG. like any other connection to cache 1. In decision block 151, the cache clearing occurs 1 not required. Since there is a bus line cycle relating to bus line 5, logic signal BSDCNN occurs at a high level in decision block 152 on, whereby a write cycle relating to the FIFO buffer 2o3 begins in block 153. As a result, according to block 154, the write pulse link signal relating to the FIFO buffer 2o3 is generated FWRITE generated.

The FIFO buffer 2o3 stores, as in connection with described in block 155, cache memory identification ooo2g, the data information BSDT 08, o9, 12, 14 and 15. Das Bus line signal BSSHBC + occurring at a low level and affecting the 2nd half indicates a T&V control function, and the low level memory reference signal BSMREF indicates that it is not a the main memory write operation concerning the main memory 3.

The bus line information relating to bus line 5 is written into the FIFO buffer 2o3 according to FIG. 2 and is also fed to the input side of the T&V logic 245. The information stored in the FIFO buffer 2o3 is not used if the link signal BSSHBC with occurs at a low level and requests T&V operation.

In accordance with decision block 156, the cache memory

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Identification checked, and the link signal MYCHAN occurs at a high level. According to decision block 157 the logic signal BSSHBC + is checked, and if the relevant logic signal occurs at a low level, this denotes a bus line cycle relating to bus line 5. This will request a T&V operation and according to block 159 the signal MYACKR is set, whereby it is acknowledged that the cache memory 1 is on the bus line 5 has assumed the bus line cycle concerned, as has been described above.

initialization

In accordance with decision block 16o, the central processing unit 2 sends to the cache memory 1 the high level Bit position BSDT 12 off, if the central processing unit 2 wishes, the data buffer 2o1 with the first 4o96 data words of the main memory 3 and the directory 2o2 with the line addresses of the relevant data word memory locations to fill. This enables the central processing unit 2, all four levels of the directory 2o2 and the wraparound logic circuit 224 to test. According to block 161, the cache memory clear signal is generated which the OLT operation according to FIG Fig. 9 initiated. Referring to Fig. 10, the Q output link signal occurs BSSHBH of the flip-flop 5o with a high level. Since the signal bit BSDT 12 occurs with a high level, the output signal occurs of the AND gate 58 with a high level, whereby an output signal of a high level is output from the OR gate 6o. As a result, the inverter 61 emits a logic output signal CLEAR- with a low level. At the end of the bus line 5 The signal CLEAR- occurs with a high level in the relevant bus line cycle. As a result, the flip-flop 571 according to FIG. is set and the Q output link signal CYQLTO + occurs with a high level, as can be seen in block 162. This will begin the QLT operation. At the end of the initialization operation the central unit 2 sends the bypass

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Cache memory instruction to cache memory 1 via the system bus line 5 off.

Set the 'mismatch reporting' error

In order to check the correct operation of the directory 2o2 and the circulation device 224, the central unit sets 2 the NO HIT error flip-flop 52 according to FIG. 1o. the Central unit sends out information corresponding to block 163 via bus line 5, the signal bits BSDT o8 and BSDT o9 are both formed by "1" bits. The flip-flop 52 according to FIG. 1o is set and the Q output link signal TESTMD, corresponding to block 114, occurs high.

Setting the bypass cache operation

To ensure that cache memory 1 is not updated while it is in test mode, the cache memory is controlled by the central unit 2 independently of the computer in that the signal bits BSDT 14 high and BSDT 15 low on the cache memory 1 according to decision block 167. According to Fig. 1o this leads to the fact that the flip-flop 59 is reset. The linkage signal CACHON-receives according to the block 168 a high level, whereby the Central unit 2 is indicated that the cache memory 1 is independent of the computer.

Test operation on directory 2o2 and circulator 224

The central unit 2 sends the link signal CACHRQ the private interface 6 between the central unit 2 and the cache memory 1. The logic circuit checked

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the various decision blocks 151 (if a cache memory clear signal has been included), decision block 152 (if a bus line cycle relating to bus line 5 is present), decision block 171 (if the FIFO buffer 2o3 is empty), and decision block 175 (if the link signal CACHRQ occurs at a high level).

According to block 176, when the logic signal CACHRQ is high, the signal CLOCKo + occurs cyclically, since the flip-flop 313 is set according to FIG. 3, the Q output logic signal FEMPTY-2o being low. The first address memory location to be tested is sent out from the central unit 2 to the cache memory 1. Initially, the address signal bus line BAOR o5-22 carries the address storage location ooooooo for the row address oooo _R. According to block 178, block request flip-flop 3o1 is set according to FIG. 3 in order to prevent a further cyclical occurrence of signal CLOCKo + by giving the output signal of NAHD element 3o2 a high level. As a result, the output signal of the NAND gate 3o4 occurs at a low level, whereby the output link signal FEMPTY-2O of the flip-flop 313 occurs at a high level. As a result, the output timing control signal CLOCKo + of the NOR gate 311 appears at a high level.

According to decision block 18o, directory 2o2 becomes according to Fig. 2 checked with respect to the row address. In this case the level 0 output signal should be the address bus signal ADDR oo-o7-2o, equal to the line address ADDR oo-o7-1o. In addition, the output link signal HITO + of the comparator 221A given a high level. Furthermore, the output logic signal NO HIT + of the NAND gate 231 occurs with a low level. As described above, the flip-flop 529 of FIG. 5 is set and the Q output link signal CYCADN + occurs high Level up. This causes the output link signal CYCADN-

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yffif

of the low level inverter 532. In this way, the central unit 2 is signaled that the cache memory 1 cycle in question has ended. The central processing unit 2 now causes the signal CACHRQ to have a low level occurs. The data sent to the central unit 2 from the data buffer 2o1 via the data bus line, CADP oo-19, are not taken into account.

The central unit 2 gives the link signal CACHRQ a high level again and sends a _{signal relating to the address memory location 00000I ß} via the address bus line BAOR o5-22, and the above sequence is repeated. If the operation is cycled for the 4096 consecutive JPdress storage locations, then the link circuitry of the directory 202 and the circulator 224 is operating properly.

The central unit 2 checks the NO HIT logic in that it sends out an address to the cache memory 1 which designates an address memory location which is higher than 4096. In in this case a "hit" signal is determined in decision block I80 and corresponding to block 181 it becomes Memory request flip-flop 503 according to FIG. 5 set. That Q output link signal MEMREQ + occurs high. The output signal of the NOR element 5o1 occurs at a low level, since the logic signal NO HIT + which at the output of the NAND gate 231 of FIG. 2 occurs, leads to a high level. The flip-flop 5o3 according to FIG. 5 is on the rise of the timing signal CLOCKO + is set.

Corresponding to decision block 182, the NO HIT error flip-flop becomes 52 is checked according to FIG. 1o, and if it is set according to block 183, then that is Output link signal CNOMEN- the NAND gate 55 with

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occur at a low level, namely because the three input logic signals TESTMD, MEMREQ + and CACHRQ + of the logic element in question occur at a high level. The link signal CNOMEN- signals to the central unit that a NO HIT error, that is to say an error that does not indicate a match, has been detected. The logic signal CNOMEN-, which occurs at a low level, also causes the bypass cache memory flip-flop 59 to be reset according to FIG. 1o, as a result of which the cache memory is made computer-independent. The central unit 2 causes the logic signal CACHRQ to appear at a low level, which when the signal MEMREQ + occurs at a high level according to FIG. As a result, the NOR gate 54 emits a low level output signal, by means of which the flip-flop 52 is reset. In addition, the Q output link signal TESTMD goes low. The operation is completed according to block 184.

The central unit 2 carries out a corresponding measure when it picks up the logic signal CNOMEM- occurring at a low level. In the example above, the Logic signal CNOMEM occurring at a low level denotes a correct operation. When the logic signal CNOMEM- is at a low level during the above-described Sequence of operations of the central processing units 2 requesting the first 4096 address storage locations had occurred, this would be the case indicate an incorrect operation and the central processing unit 2 would take corrective action. Since the operation of the Central unit 2 is not part of the invention, it will only be described to the extent necessary for the context of FIG Description is required.

Reset if there is no match. In accordance with decision block 165, the NO HIT error

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Flip-flop 52 according to FIG. 1o reset according to block 166, since the signal bits BSDT 08 occur with a high level and BSDT o9 with a low level.

Resetting the bypass cache

In accordance with decision block 169, the bypass cache memory becomes flip-flop 59 according to FIG. 1o are reset in accordance with block 17o, since the signal bits BSDT 14 and BSDT 15 are high. That with low Level occurring U-output link signal CACHON-shows the central processing unit 2 that the cache memory 1 is, so to speak, computer-dependent. The central unit 2 connects the cache memory to the line or makes it computer-dependent in that a T&V information is sent out.

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During the bus line cycle relating to bus line 5 the logic signal BSDCNN is checked in accordance with decision block 171. When this signal occurs with a low level, then the signal MYACKR is reset in accordance with block 172, whereby the relevant bus line cycle is completed in accordance with block 193.

In Fig. 12, the timing relationships during the test and verification cycle and also during the mismatch or error cycles ν causing no hits.

The signal BSDCNN27O, which occurs at a high level, signals the cache memory 1 that information is on the bus line 5. The information is in the cache 1 is decoded, and when the cache memory identification code O002o occurs at low level Logic signal BSMREF + is determined, then the output signal of the flip-flop 546 according to FIG. 5 occurs with a high Level to, and also the flip-flop 516 is set. The high-level Q output signal MYACKR271 according to FIG. 12 causes the setting of the flip-flop 150 according to FIG Fig. 10. The high-level Q output signal In accordance with block 273 in FIG. 12, BSSHBH causes the T + V logic in accordance with FIG. 10 to be set accordingly will. One or two signal bits BSDT08, 09, 12, 14 or corresponding to block 272 according to FIG. 12 occur for the relevant High cycle on. If the signal bits BSDTO8 and BSDTO9 occur with a high level, then this occurs Output signal TESTMD274 of the flip-flop 152 shown in FIG. High level. If the signal bit BSDT12 according to the

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4U

Block 272 occurs with a high level, then the signal CLEAR- occurs according to the block 275 with a low level, whereby the signal CYQLTO +, according to 276, occurs with the signal rise of the signal CLEAR-, 275, with a high level. This initiates the QLT operation, through which the first 4Q96 address storage locations of the main memory 3 are transferred to the cache memory 1.

The central unit 2 tests the cache memory 1 during the no match or hit signals Error cycles, and signal TESTMD, 274, is made high by the signal CACHRQ '277, being high Level is given. This causes the FEMPTY-2O, 278, signal to appear low, and also leads to a cyclical output of the clock signal CLOCKO +, 279. If the signal HITO-3, 280 goes high this indicates that the row address sent out by the central processing unit 2 to the cache memory 1 is in the column address memory location of directory 202 has been stored. Then the negative pulse is CYCADN-, 231, is output to the central processing unit CPU2, and the signal CACHRQ-, 277, appears at a low level.

The central unit 2 sends another signal CACHRO / 277, the end. In this case there is no match or no hit signal. The signal HITO-3, 280, remains at a low level, and the signal MEMREQ, 282, is given a high level, whereby the negative pulse CNOMEM-, 283, which is sent to the central unit 2. The central unit 2 then causes the signal CACHRQ, 277, occurs low.

The central unit 2 also takes the necessary corrective action which is not further described as it is not

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Is part of the invention.

The signal CACHON, 284, occurs at a low level, when the signals BSDT14 and BSDT15 appear high. The CACHON signal, 284, also occurs low when the CLEAR-, 275, signal is low Level occurs. The signal CNOMEM-, 283, occurring at a low level causes the signal CACHON, 284, to be high Level occurs, whereby the central unit 2 is indicated that the cache memory 1 is computer-independentxg.

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■ Explanation of the operating mode

In Fig. 9, there is the quality link test operation by means of a flow chart (QLT). As a result of a system start-up, a negative CLEÄR signal is transmitted the bus line 6 is sent out to the cache memory 1. As a result of the reception of the CLEAR- signal, the content of the The first 4096 address storage locations are stored in the main memory 3 in the four levels of the data buffer 2o1 according to FIG. The directory 2o2 is loaded with the corresponding row addresses of the first 4o96 address memory locations and the RAM memory of the recirculation circuit are set to go to level O as the first level in the data buffer and in indicate the directory 2o2 as the level in which an exchange or replacement is to be carried out.

Fig. 7 illustrates on the basis of a. QLT operation timing diagram; the relevant timing diagram is used in conjunction with FIG. 9 in the course of explaining the overall mode of operation can be used.

A transmission cycle relating to bus line 5 is designated by START 901. The cache memory 1 takes over all the bus line 5 takes place for a possible update or a possible exchange.

In QLT operation, the link signal CLEAR- is received from the cache memory 1 via the bus line 5. This is marked by START 9oo.

In decision block 9o1, the QLT mode 9o2 is selected and, according to block 9o3, the flip-flop becomes 571 • -. (Fig. 5) with the rise of the logic signal CLEAR-

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-, and the Q output logic signal CYQLTC + assumes a high level. As a result, the NOR gate 561 outputs a low level output signal and the output link signal CYQLTO-1A of the inverter 567 occurs at a high level. The logic output signal CYQLTO + OB of the delay line 562 remains at a high level for a period of 16ons. According to FIG. 4, the output signal of the NAND gate 443 assumes a low level, as a result of which the NOR gate 419 emits its output logic element AORCNT with a high level.

After the block 904, the output signal lines AORO o5-22 + of the adder 211 according to FIG. 2 carry the address 00000068. That with a high The output signal of the NAND element 241 which occurs at the level switches the 2: 1 multiplexer 2o9 in such a way that the signal lines AORO o5-22 + can be connected to the input side of the address register 2o7.

By the logic signal AOROCNT according to FIG. 4, the output logic signals BAWRIT of the NAND gate 416 are on brought to a low level and the output signal BAORCK of the NAND gate 424 is brought to a low level. In addition, the data word PRA ooooo "is stored in the address register 2o7 according to FIG. 2 and the storage location 00 is written into the change address file 2o6. 7o ns later this occurs on Output of the inverter 423 occurring logic signal A0RCNT-3o with a low level, as a result of which the write address counter of the change address file is switched to the storage location o1 will.

I60 ns after the logic signal CYQLTO + has risen, the logic output signal CYQLTO + 00 of the NOR element 565 5 to a low level, whereby the flip-flop 503 is set. As a result, the Q output signal MEMREQ + occurs with a high level, as can be seen in block 905.

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and the flip-flop 511 is set. The Q output concatenation signal then occurs CYCREQ + according to block 906 with a high level, which results in that according to the block 9o7 a bus line cycle relating to bus line 5 is requested.

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According to FIG. 7, the timing control signal CLEAR-701 occurs at O ns of the first cycle request relating to bus line 5 with a high level, whereby the signal CYQLTO + 702 receives a high level. This leads to d'.e signals BAWRIT 710 and BAORCK 711 occur with a low level, whereby the address 000000g in the address register 207 and is keyed into the change address file 206. The AORCNT-30 713 signal causes the write address counter 234 of the change address file has been moved to location 01. 160 ns after the CYQLTO + signal rises 702 the signal CYQLTO + OD 703 falls, whereby the signal MEMREQ + 704 occurs with a high level, which has the consequence that the signal CYCREQ + 705 occurs with a high level.

At decision block 907a, the input link signal occurs BSBUSY of the NAND gate 513 according to FIG. 5 with a high level. Since the logic signal CYCREQ + has a high level occurs, the flip-flop 513 is set and the Q output signal MYREQT goes high according to block 907b.

If there is no request for a higher priority with regard to bus line 5, then the block 907c, the output signal of the NAND gate 542 assume a low level and set the flip-flop 541. The Q output link signal MYDCNN + goes high, causing drivers 212, 214 and 218 are enabled for this, corresponding to block 907c on bus line 5, the output signal of the address register 207 ,, namely 000000g, the cache 1 identifier and send out the function code, BSDBPL and BSMREF.

The response signal BSACKR from main memory 3 corresponding to decision block 907f acknowledges the transmission of the information from cache memory 1 and is sent back via bus line 5. Characterized the output signal of the NOR gate 543 5 occurs according to Fig. Low _Pege i _on.

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This means that the flip-flop 543 is set again in accordance with the block 907i, whereby the flip-flop 514 is set which resets the flip-flop 515. The Q output signals MYDCNN + and MYREQT are now occurring low and, corresponding to block 907k, the bus cycle request is made closed.

If according to decision block 9O7f from main memory 3 the response signal BSWAIT has been provided, then in accordance with decision block 907g, the output signal becomes of the NOR gate 543 according to FIG. 5 assume a low level, whereby the flip-flop 541 is reset will. The Q output link signal MYDCNN + assumes a low level. Corresponding to blocks 907h and 907j, the output signal of NOR gate 572 occurs according to FIG 5 with a high level, whereby the output signal of the AND gate 512 is given a high level. This will the flip-flop 515 is held set and the Q output logic signal MYREQT is high. The" requests another bus line cycle for the bus line 5 at.

The address PRA + 1 (000000g) now appears at the output of the Adder 211 according to FIG. 3 corresponding to block 908.

The response signal BSACKR to the first bus cycle request relating to the bus line sets flip-flop 504 as shown in FIG. 5, and the Q output signal BLOCKF + occurs with a high level. Since the write address counter 234 is set to the memory location 01, the output signal of the NOR gate 417 according to FIG. 4 occurs with a low level. As a result, the output logic signal AORCNT of the NOR gate will have a high level. As a result, the size 000001 _{g is} loaded into the address register 207 and the memory location 01 of the change address file 206 in accordance with block 909. If that

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Link signal AORCNT-30 has a low level assumes, the write address counter of the change address file advances to storage location 02.

Referring to Fig. 7, when the signal MYREQT 706 goes high, the signal MYDCNN + 707 goes high lead when the bus line 5 is available. The information of the cache memory 1 is keyed to the bus line 5, and when the main memory 3 receives the information, it sends the signal BSACKR. 708, which resets the MYDCNN + 707 signal and sets the BLOCKF 709 signal. That with low Level occurring signal MYDCNN + causes the resetting of the signal MYREQT 706. If the bus line 5 is no longer is occupied, the signal MYREQT 706 occurs with a high level, whereby another, the bus line 5 concerned Bus cycle is requested. When the BLOCK F 709 signal is high at the beginning of the second bus cycle request assumes, the signals BAWRIT 710 and BAORCK 711 sample the address appearing at the output of the adder 211 according to FIG into address register 207 and change address file 206. The AORCNT-30 713 signal then sets the write, address counter 234 of the change address file is switched to storage location 02.

Since the signal CYCREQ + 705 is still at a high level on the second bus cycle request, the signal MYREQT also decreases 706 goes high, requesting the bus cycle.

After block 907-i ·, _{the 2nd}

Bus cycle requested and according to the blocks

907-j becomes the next address in the sequence to the bus line 5 with the cache identification 0002, the function code, BSDBPL and BSMREF.

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According to FIG. 7, the signal occurring at a high level conducts MYREQT 706 the second bus cycle request relating to bus line 5 in that the signal MYDCNN + 707 is on high level is given. This resets the CYCREQ + 705 signal and the signal that occurs on bus line 5 Information is sampled as before. When the main memory 3 receives the information, the signal BSACKR 708 becomes over the bus line 5 is sent out to the cache memory 1, and furthermore the signal MYDCNN + 707 is reset, which leads to a reset of the signal MYREQT 706 leads.

According to block 910, cache memory 1 waits for the first data word from main memory 3. Corresponding In the block 900, the information is on the * bus line 5. In decision block 901, the signal CLEAR is not asserted, whereby the selection of decision block 911 occurs, according to which the signal BSDCNN + is high Level occurs. This indicates that the information on the bus line 5 is in the FIFO buffer 203 according to the Block 912 is to be written. After block 912a, the logic output signal causes the NAND gate to FWRITE according to FIG. 3, that the write enable connection of the FIFO buffer 203 a low level occurs. In addition, as shown in FIG. 2, the output signals of the receivers 213, 215 and 217 become keyed into the FIFO buffer 203. As illustrated by block 912b, the FIFO buffer 203 is filled with the data word loaded on the occurrence of the first bus cycle request, the size PRA 000000 to the main memory 3 was sent out. The cache memory identification (0002g) and the function code are also stored in the FIFO buffer 203 (00g) loaded, the link signals BSDBPL and BSSHBC occur with a high level and the logic signal BSMREF with a low level.

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In accordance with decision block 912c, the cache identification code checked with respect to 0002g, the signal BSMREF occurring at a low level. In case of Fig. 5 occurs the logic output signal MYCHAN of the AND gate 546 with a high level, whereby the second Half bus cycle is started according to block 913.

According to block 913a, when the logic signal MYCHAN is present, this occurs CLK input link signal BSDCND + of fliflop 516 high. The fliflop 516 is set and the Q output linkage signal MYACKR joins high level and acknowledges the main memory 3 that the information has been recorded.

According to the block 913b, the output logic signal F + 1 of the NAND gate 322 according to FIG. 3 sets the write address counter flip-flop 320 of the FIFOrBuffer 203, whereby the counter is incremented. This causes the output signal to occur of the comparator 318 with low level * uf, which leads to the setting of the flip-flops 313. The Q output * link signal FEMPTY + 20 occurs low, causing the timing signal, CLOCKO +, to be the output signal of the NOR gate 311, is started with regard to the cyclical delivery corresponding to the block 913c.

Since the function _{code is given as 00 g} , the signal BSAD 23 occurs in accordance with decision block 313d with a low level. Then, corresponding to the block 913f, the signal FCHZRO is set by the fliflop 413 according to FIG. 4, and a ¹¹ 1 "is introduced into the bit position 42 of the FIFO buffer 203.

According to decision block 913g it is checked whether the signal BSDBPL occurs with a high level. In the QLT mode, the BSDBPL signal is low and the flip-flop 574 of FIG. 5 remains reset. The Q output link signal BSDBPL- occurs at a high level 909828/0726

do

on, whereby the output of the NAND gate 506 a low level is given. As a result, the output logic signal DATACK- of the NOR gate 507 occurs at a low level Level up. This in turn has the consequence that the data counter flip-flop 508 is set in accordance with block 913h.

According to decision block 9132 it is checked whether the flip-flop 509 according to FIG. 5 is set. In this case, flip-flop 509 is not set, and so is the output signal of NAND gate 510 remains high. After decision block 913j is the logic signal BSDCNN + checked, and 60 ns after. Point in time at which it drops to a low level according to block 913k, the flip-flop 516 is reset. Furthermore, the Q output link signal goes down HYACKR off and the cache memory 1 goes into an idle cycle wait state according to this Starting block 900 over.

The second data word in response to the second bus cycle request, 907-1, is transferred to the cache memory 1. When the BSDCNN + signal occurs high, the FIFO write block 912-1 is activated because the data word comes from an odd-numbered address memory location in the main memory 3.

The FIFO write sequence described alone is run through of blocks 912a-c through the second half of the bus cycle repeats according to block 913-1. The second half of the bus cycle sequence corresponding to blocks 913a-g becomes repeated. According to block 913h, the data counter becomes a flip-flop

509 is set in accordance with FIG. 5, and cause the Q output link signals CYFIFO and DATCTI occurring at a high level corresponding to decision block 913i that the NAND gate

510 emits a low output signal, upon the occurrence of which the flip-flop 503 corresponding to the block 913n

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is reset. In addition, the Q output link signal goes down MEREQ +.

The MYACKR flip-flop 516 is reset according to block 913m / if in decision block 9131 that Logic signal BSDCNN + occurs at a low level. After block 913n, the logic signal takes MEMREQ + to a low level, whereby the flip-flops 508, 509, 504 of FIG. 5 and 413 of FIG. 4 are reset. As a result, the logic signals DATCTO, DATCTI, BLOCKF + and FCHZRO take a low according to block 913o Level on.

The cache memory 1 returns to the start 900 for the first read cycle of the FIFO buffer 203.

Referring to Fig. 7, the signal BSDCNN + 714 occurs high to begin the FIFO write cycle according to which the The first data word is transferred from the even-numbered address memory location of the main memory 3 to the cache memory 1 will. The information on bus line 5 is scanned into FIFO buffer 203 by signal FWRITE 715. The MYACKR 716 signal is asserted high when the FIFO buffer 203 receives the cache identification 0002g and when the signal BSMREF is low. The high level signal MYACKR 716 thereby switches the FIFO write address counter further that the signal F + 1 717 is given a low level.

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The FIFO buffer 203 is now not empty, and the signal FEMPTY + 2O assumes a low level, which means that the cyclic The signal CLOCKO + 719 is started and the first read cycle of the FIFO buffer 203 is initiated.

During the first word cycle with respect to the cache memory, the low level signal BSDBPL causes that the data counter clock pulse DATACK 728 occurs low. Occurs during the second FIFO write cycle the BSDBPL signal reappears at a low level, and the DATACK 728 signal also occurs at a low level, whereby the DATCTI 729 signal occurs again at a high level. This resets the MEMREQ + 704 signal, which resets the signals BLOCK F 709 and DATCTI 729.

According to block 913b, in the second half of the bus cycle the FIFO write address counter is incremented. This makes the output of the comparator 318 shown in FIG Fig. 3, namely the logic signal FEMPTY + brought to a low signal level, which is in the decision block 916 indicates that the FIFO buffer 203 is not empty. This is used to control the clock cycle by setting the flip-flop 313 is started according to block 913c, and a FIFO read operation according to block 914 is also started.

Select FIFO read address counter flip-flops 316 and 317 in accordance with block 914a, the FIFO address from which information from the FIFO buffer 203 to the register 204 is transmitted.

Since the output of decision block 914b is high level occurs, this means that the bit position 41 of the FIFO buffer 203 has a high level. aside from that the replacement or exchange block 915 is selected. Update block 914c is not on the QLT operation active.

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The change address file 206 stores the address for the data word which is in the selected address storage location FIFO buffer 203 is stored. According to that Block 915a selects the read address multiplexer of the change address file, these are the 4: 1 multiplexers 414 and 415 4, the memory location 00 from. The logic signal CYQLTO- occurs at a low level and causes that the output of the NOR gate 440 occurs with a high level. This makes the one that has a high signal level Port 2 of the 4: 1 multiplexers 414 and 415 selected. There the bit position 18 of the FIFO buffer 203 carries a low level, the selection connections 1 lead to the 4: 1 multiplexer 414 and 415 have a low level, whereby the input terminal 2 is enabled. The input port 2 of 4: 1 multiplexer 414 is low, like input terminal 2 of 4: 1 multiplexer 415.

According to block 915b, the address is au3 the memory location 00 of the change change file 206 as well as the data word and the control signals from the FIFO buffer 203 with the Transfer increase of the logic signal CiTFIFO to the register 204. The output signal of the AND gate 3 occurs at a high level, and on the signal rising edge of the timing control signal CLOCKO +, the flip-flop 323 is set and the Q output latching signal CYFIFO goes high, which loads the register.

In the decision block 915c, the signals BA0R11 and BA0R12 checked. When both signals are low occur, this indicates that the first 1024 data words are being transmitted. Then, in accordance with block 915d the circulation register is held in the reset state, whereby the Level 0 of data buffer 201 and directory 202 is selected. According to FIG. 14, the output link signal occurs ROUNDR- the NOR gate 608 with a high level. When the logic signal CYFIFO assumes a high level, the FÜpflop 609 is set, and the Q output linkage signal ROUND-OR goes low, whereby the

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Flip-flops 610 and 611 are held in the reset state. Therefore, according to block 915e, the Q output link signals appear ROUNDO- and R0UND1- with a high level, whereby the output link signal LEVEL 0+ of the AND gate 613a leads to a high level.

Corresponding to block 915h, the data word is written into the data buffer 201 under the selected column address, and the row address is written into the directory 202. The RAM memories of the circulator are increased by +1. The output signal of the NOR element 340 according to FIG. 3 occurs at a high level, as a result of which the output signal from the NOR element 325 occurs at a low level when the logic signal CYFIFO has a high level. As a result, the NOR gate 327 outputs a high level output signal. As a result, flip-flop 330 is set and the Q output signal CYWRIT occurs with a high level. According to FIG. 14, the logic signal CYWRIT occurring at a high level generates a negative 30 ns pulse which is delayed by 20 ns and which is fed to the enable input of the 2: 1 multiplexer 223. As a result, the logic signal WRITEO occurs at a high level, as a result of which the data word is written into level 0 of the data buffer and as a result of which the row address is written into the directory 202 under the selected column address. The output signal of the NAND gate assumes a low level, whereby the write inputs of the RAM memories 601 and 602 are enabled in such a way that a "1" is introduced into the RAM memory 602 and a ¹¹ O "into the RAM memory 601 , namely under the selected column address ADDR 08-17 +, since the logic signal R0ÜND1- occur with a high level and the logic signal RNDADD + with a low level.

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28B5730

In accordance with decision block 915c, there is the data words at the address location between 102 4 and 4095 at the bit positions BAOR 11 + 10 and / or BAOR 12 + 10, where the Output signal of the address register 207 of FIG. 2 occurs with a high level. A normal is running in block 915f Operation of the circulator 224, refer to FIG. 14 related means that the output signal of the RAM memory 601 and 602 at the column address memory location ADDR 08-17 + is loaded into the flip-flops 610 and 611 when the logic signal CYWRIT rises. The output signals of the flip-flops 610 and 611 are by means of the AND gate 613a-d in the block 915g is decoded to that level in directory 202 and in the data buffer 201 into which the data word is written. This has already been seen above.

The FIFO read timing is. illustrated in Fig. 7 by that the signal F + 1 717 advances the write address counter flip-flops 320 and 321 according to FIG. 3 of the FIFO buffer 203. This causes flip-flop 313 to be set causing the Q output signal FEMPTY + 20 718 to be low Assumes level, whereupon the output of the signal CLOCKO + 719 is started. The data word is then loaded and the control bits from the FIFO buffer 203 and the address memory location from change address file 206 into register 204. Register 726 illustrates this Time control.

The signals CYREAD 721 and CYWRITE 722, the two output signals Q and Q of the flip-flop 330 according to FIG. 3 are switched on in response to the rise of the signal CLOCKO + 719 if the signal CYFIFO 720 occurs at a high level. The REPLACE 723 signal occurs high because the FIFO bit position 41 is high for the QLT operation. The signal REPLACE 723 occurs when the CYFIFO 720 signal rises high and stays high for the 4096 data word QLT transmission.

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-yrr -

The WRITE 0-3 727 signal is in the circulator 224 according to FIG. 14 is generated. The output logic signal CYWRIT of the AND gate 604 has a positive pulse a duration of 30 ns; it is delayed by 20 ns and output inverted by the inverter 606. There is the 2: 1 multiplexer 22 3 free. Since the selection input link signal REPLACE appears high, the 1 input terminal is activated. With the occurrence of the increase in the logic signal CYWRIT becomes the selected output of RAM memories 601 and 602 into flip-flops 610 and 611 introduced whereby one of the logic output signals LEVEL 0-3 + of AND gate 613a-d is brought to a high level. This selected signal is applied to input terminal 1 of the 2: 1 multiplexer 223, and the am Terminal 2 occurring output signal is inverted by the inverter 255 shown in FIG. 2 and causes the release of the Writing into the data buffer 201 and the directory 202 as a negative pulse WRITE 0-3-, which has a width of 30 ns.

The FIFO read address counter is activated by the BUMP UP 724, thereby causing the FEMPTY + 20 718 signal to go high and causing the cyclic output of the signal CLOCKO + 719 is stopped. However, the odd word becomes' from main memory 3 from the cache memory I, so that the signal F + 1 717 advances the FIFO write address counter again. This causes the FEMPTY + 20 718 signal to go low Level brought, as a result of which the cyclical output of the signal CLOCKO + 719 is achieved. This will make the odd number Word is stored in the data buffer 201 and its line address is stored in the directory 202. After this the odd word is stored, the FEMPTY + 20 718 signal remains high and the CLOCKO + 720 signal remains high at the end of the cycle in which the data word is transferred from the odd-numbered memory location to the Cache memory 1 is stored.

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Referring to Figure 9, at decision block 9151, a Checked for the 4096 password. If the last word has not been recorded, then, corresponding to block 915j, the address is output of the adder 211 according to FIG. 2 is increased by +1 and the RAF write address counter 234 is incremented.

A check is then made according to decision block 915k. If the word in the FIFO buffer 203 is received from an even-numbered address storage location in main memory 3, then returns the cache memory 1 returns to the START 900 to wait for the next word from the main memory 3, namely from the odd numbered address space. If the data word received in the FIFO buffer 203 consists of a Odd-numbered address storage space of the main memory 3 originates, then according to the block 9151 the next Address loaded into address register 207 and change address file 206, and the write address counter 234 is switched on. It should be noted that, corresponding to block 915j, the write address counter a separate counter setting for each transmitted data word is continued. The reason for that in that the write address counter 234 has the even address location in location 00 of the change address file 206 and the even-numbered address location in location 01 of the change address file 206. Positions 02 and 03 are not used.

. In accordance with block 915, flip-flop 503 becomes in accordance with Fig. 5 is set in the following manner. The output of AND gate 567 occurs at a high level. the Link signals CYWRIT, REPLACE and FIFO 17 + 20 occur with a high level. This causes the output link signal to occur MEMREQ + OC of NOR gate 569 with a low level, whereby the NOR gate 502 has an output signal with a high level, upon the occurrence of which the flip-flop 503 is set with the next increase in the timing signal CLOCKO +. The Q output signal occurring at a high level

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Link signal MEMREQ + begins a memory request cycle by returning to block 906, according to which the cycle request flip-flop 511 is set and according to which the Q output link signal CYCREQ + occurs with a high level.

Referring to Fig. 7, the signal MEMREQ + 704 occurs at the end of the cycle with high level within which the data word from the odd-numbered address storage space in main memory 3 is written into cache memory 1. This then occurs when the CYWRITE 722 signal is high the last time the CLOCKO + 719 signal rises.

The cache memory 1 continues the cyclical operation, whereby initially 2 data words are requested from the main memory 3 whereupon these data words are written into the data buffer 201 and the line address into the directory 202 is entered until, in accordance with decision block 915i, the 4096-th word is received in register 204 according to FIG is. In this case occurs the one input signal BAOR 10 + 10 of the NAND gate 570 according to FIG. 5 with a high level on. If the output of AND gate 567 goes high during the cycle within which the Data word from the odd-numbered address memory location is written into the cache memory, then takes the output signal of the NAND gate 570 goes low, whereby the flip-flop 571 is reset. After block 915n this causes the Q output link signal CYQLTO + to be low, thereby completing the QLT operation will.

The signal BAOR 10 + 10, which occurs at a high level, has the effect that the output link signal QLTDU- of inverter 568 occurs at a low level. As a result, the NOR gate inputs 569 Output link signal MEMREQ + OC from high level. This in turn leads to the output signal of the NOR gate .502 occurs at a low level. If the D input * gnal

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285573Ö

p 503 on

leads to a low level, the flip-flop will the next rise of the timing signal CLOCKO + reset, and the Q output link signal MEMREQ + occurs at a low level. This means that there are further inquiries or requests to the main memory 3 avoided.

7, the QLTDUN 712 signal occurs during last, the bus line 5 related cycle request with high level, whereby the signal MEKREQ + 704 with occurs the next low level rise of the CLOCKO + 719 signal. The signal CYQLTO + 702 carries low during the next cycle when the CYViRITE 722 signal is high. The data word from the odd-numbered address memory location is with the last rise of the signal CLOCKO + 719 in the "Register 7 26.

Although the system has been written in terms of loading the cache from main memory, no special indication is given regarding the exact values of the information stored in the main memory been. It should be noted that under certain conditions, as part of the introductory operation, i.e., as part of the power-up sequence that clears the main memory that is in the cache memory to be transferred part of the main memory stored initial values are given in total by zeros. In those cases in which it is desired to carry out certain types of special operations, e.g. diagnostic operations, the portion of main memory would be preloaded with values to perform the particular operation. Under other conditions, the cache would be a valid copy of everything in main memory information to be saved.

The preloading of the main memory for the present

909828/0726

System is carried out in a conventional manner.

The invention thus creates a data processing system with a large number of system units, which are all connected together to a system bus line. The system units contain a central processing unit, a storage system, and a high speed buffer or cache system. The placement in the cache is effected throughout the initiation process the transfer of information from the main memory to the cache memory for all address storage locations of the cache memory. The transfer of information from the main memory to the cache memory starts from the least significant address in main memory and continues from successive ones Memory locations until the cache memory is full. The cache memory has an arrangement which sends a display to the central unit regarding the reference to such variables in the main memory, those in the cache memory during a test and Check operation do not exist.

909828/0726

Claims (1)

DIPL. ING. HEINZ BARDEHLE Müichm, DIPL. CHEM. DR. PETER FÜRNISS PATENT LAWYERS 2855730 File reference: Our reference: P 2808 Applicant: Claims Data processing system with a system bus line to which an addressable main memory is connected, which has a multiplicity of sets of "word memory locations, each sentence of which is defined by an address, and with a number of word memory locations storing a multiplicity of test and check commands, characterized in that A central processing unit (CPU) is connected to the system bus line and sends requests to the main memory for reading test and verification commands and data for transfer to the system bus line, that a cache memory is connected to the system bus line and the central unit, the one Data buffer containing a variety of sets of word storage locations in a variety of rows or sets of word storage locations are arranged, which are defined by the address for the storage of the data are specified that a directory with a large number of word storage locations is provided, the number of which corresponds to the number of sets of word storage locations in the Data buffer corresponds, with each word storage location in the relevant directory having an address e. stores a corresponding word of the words of the respective set of word memory locations which are in the data buffer are stored, that the cache memory contains a device which responds to the test and verification commands and the one operating mode connected to the system bus line Q09828 / 0726 ORDINAL INSPECTED Office: Herrnstrasse 15, Munich 22 Control device and one connected to the system bus line and to the operating mode control device Device comprises which emit a signal indicating the presence of an error-free condition able to and that the central unit in response to the occurrence of a first test and verification command a plurality generated by signals for transmission over the system bus line, the operating mode control device is so effective on the occurrence of one of the signals in question that they have a for a test and verification operation is switched on, and when the Operation responsive device controlled by the relevant signals generates an output signal, which is indicative of whether the data as a result of a request to the cache memory by the central processing unit are stored in the data buffer. 2. Data processing system with a system bus line to which an addressable main memory is connected having a plurality of storage locations, with sets of word storage locations respectively are defined by an address and a number of memory locations a variety of test and test commands stores, and with a central unit connected to the system bus line, the Requirements for the main memory for reading out the test and verification commands and the data for transmission generated via the system bus line, characterized in that on the system bus line and · A cache memory is connected to the central unit, which has a data buffer with a large number of of storage locations and a directory with a large number of storage locations, their number 909828/0726 corresponds to the number of storage locations in the data buffer, with in the relevant storage locations an address can be stored which designates a corresponding memory location in the data buffer, that the cache further includes means responsive to the test and verify instructions responds and the one connected to the system bus line mode control device and one device connected to the system bus line and the relevant operating mode control device includes, which in the absence of a match signal indicating an error indicates that the central unit on a first command of the test and test commands is operated so that a plurality of signals for transmission to the System bus line is generated that the operating mode control device on one of the signals in such a way is operated that a setting or switching takes place in a certain state, which is characteristic is for a test and verification operation, and that an error reporting device in the absence of a match signal by the relevant Signals is controlled in such a way that they are directed to one of the central processing unit to the cache memory Request generates an output signal which is indicative of whether the data is in the data buffer are stored. . System according to Claim 1 or 2, characterized in that the cache memory also has one on the system bus line and includes bypass cache memory means connected to the mode control means, that the central unit on the occurrence of one of the test and test commands out a further plurality of signals for transmission to the system bus line that the operating mode controller generates 909828/0726 is operated on the occurrence of one of the signals in such a way that a switch-on or switchover upon a certain state occurs that the bypass cache memory means is made by the mode control means as well as other signals when encoded in a first manner is to make an adjustment in a first state which provides an indication that the Cache memory for processing the central processing unit requests is in operation for data, and that the by-path cache memory means in the first state is the cache memory by the other Signals ineffective while the bypass cache facility when encoding in a second way provides a signal that the cache memory for processing the Central unit requirements is bypassed. 4. System according to claim 3, characterized in that the bypass cache memory means such is operated that they cause a setting in the second state on the occurrence of the Output signal indicates that the cache memory is in the inactive state in this case is that the output is in a first state, which is an indication of this provided that the data designated by the central processing unit request is not in the data buffer are stored and that there is an error condition. 5. System according to claim 3, characterized in that the cache memory also has one on the system bus line and cache initiator connected to the mode controller 909828/0726 contains that the central unit in such a manner in operation in response to the occurrence of one of the test and verification commands is that there is another plurality of signals for transmission to the system bus line is generated that the operating mode control device is operated in such a manner in response to the occurrence of one of the signals that a power-on occurs in a certain state and that the cache memory initiator by the operating mode control device and by a further signal from the relevant Signals is controlled in such a way that a request from successive word storage locations of the main memory read out data words for the purpose of writing into the memory locations of the data buffer occurs as part of the test and verify operation. 6. System according to any one of claims 1 to 5, characterized in that the cache memory also has a Contains connecting device with which it is connected to the system bus line and by means of the a test signal is generated in response to the reception of the plurality of signals by the central unit. 7. System according to claim 6, characterized in that the operating mode control device is a bistable Circuit element with a set, reset and clock connection contains that the bistable Element can be set in a first state in that the test signal is applied to the clock input terminal and the set terminal is supplied with a signal of those signals which are used to designate the Test and test operations are coded accordingly, and that the bistable element has the first state can then be switched to a reset state if another of the from the central unit 909828/0726 generated signals is supplied to the reset terminal in a certain state, the relevant bistable element in the specified state mentioned that the absence of a match signal reporting error device releases. 8. System according to claim 6, characterized in that the absence of a match signal an error device issuing a message is a bistable circuit element with set, reset and clock input connections contains, which in a first state from the operating mode control device is adjustable in the event that the clock terminal of one of the signals and the set terminal another the signals generated by the central unit is supplied that the bistable element of the first State can be switched to a reset state in the event that the reset terminal has a signal is fed from the central unit after it has received an output signal which provides an indication that the requested data is not in the data buffer, and that the bistable element generates a test operating signal in said particular state, on the If a logic device occurs, the output of the test operating signal with other signals continues while generating an output signal intended for the central unit, which one Indicates whether the data is stored in the data buffer. 9. System according to claim 8, characterized in that the logic device is a NAND logic circuit with a variety of input connections 909828/0726 and an output terminal that has a first input terminal for receiving the test operating signal serves that a second input connection for receiving one of the cache memory request corresponding Signal is used that a third input terminal is used to receive a memory request signal, which is indicative of the fact that the data requested by the central unit is not in the data buffer are located, and that the output connection is connected to the central processing unit and to this emits a certain signal, which is indicative of the fact that the central unit requested data is not in the data buffer during the test and verification operation. 10. The system of claim 3, characterized in that the bypass cache memory device is a bistable Circuitry with preset, set, clock and reset input terminals includes that the bistable Element adjustable by the operating mode control device in a first state in the case is that one of said signals is fed to the clock terminal in the event that the set terminal is on Another of the signals generated by the central unit is supplied that the bistable element in a Reset status in the event that a certain signal is sent to the central unit, which provides an indication that the data requested from the central unit during the test and Check operations are not stored in the data buffer, and that the bistable element is in said certain state generates a signal which is indicative of the fact that the cache memory is in operation is. 909828/0726 11. Data processing system with a system bus line to which an addressable main memory is connected is that of a multitude of sets of word storage locations each set of which is identified by an address, and one connected to the bus line Central unit, characterized in that a cache memory is connected to the bus line is, that a data buffer with a variety of word storage locations is provided, which are arranged in a plurality of sets of word storage locations, which are designated by the address that a directory with a plurality of word storage locations provided, the number of which corresponds to the number of records in the data buffer, each word storage location in the relevant dictionary having an address of a corresponding word which stores words of the sentence stored in the data buffer, that the cache memory contains a mode control device which is connected to the bus line and which is a trigger signal from the relevant bus line to designate a trigger or Initial operation receives, that a memory request device is connected to the operating mode control device, which a sequence of main memory requests for activation by the operating mode control device generated that an address generating device is provided which is contained within the requirements Main memory addresses generated and those with the bus line and the main memory request device connected is, that the address generating device is controlled by the main memory request device 909828/0726 a particular sequence of addresses contained within corresponding sequences of requests to the system bus line, and that the main memory on the occurrence of the requirements on the system bus line the information read out from those word storage locations outputs which correspond to the sequence of addresses, with corresponding write operations in the data buffer and the directory and the cache memory, thereby in a known State can be brought. 12. Data processing system with a system bus line to which an addressable main memory is connected which has a plurality of memory locations, characterized in that on the system bus line a cache memory is connected, which has a data buffer with a large number of memory locations and a directory with a plurality of storage locations, the number of which the number of sets of storage locations in the data buffer, each storage location being the relevant directory stores an address, which a corresponding memory location of the Identifies the data buffer, that the cache memory further comprises a mode control device that is connected to the system bus line and that of the relevant An initiation signal is supplied to the system bus line receives, which defines an initial operation, that at the operating mode control device a main memory request device is connected, which when controlled by the operating mode control device a sequence of main memory requirements 909828/0726 - ίο - generated, that an address generating device is provided which is contained within the requirements Main memory addresses generated and those on the system bus line and on the main memory request device is connected that the address generating device is controlled by the main store requesting device a specific sequence of addresses that contain within corresponding sequences of requirements are, to the system bus line, and that the main memory to the relevant Requirements for the system bus line from those word memory locations, which the Sequences of addresses correspond to information read out for writing into the data buffer and to the directory in question, transferring the cache memory to a known one State. 13. System according to claim 11 or 12, characterized in that with the address generating device and a detector transmission device is connected to the operating mode control device, which is controlled by the address generating means in response to the generation of a specific address a reset signal to the mode controller to terminate the initiation operation. 14.System according to claim 11 or 12, characterized in that that the addressing device has an output device connected to the system bus line. gister, with the help of which the main memory request addresses are transferred to the main memory 909828/0726 and that the initiation signal causes the determined main memory address to store, and that an adder is connected to the output register, which in allows the address stored in the output register to be increased by a certain value in the event that that the output register is caused by the main memory requester, the relevant To transfer the address to the system bus line. 15. System according to claim 14, characterized in that the addressing device is one on the output register and holds random access file attached to the adder in which the Main memory request addresses can be stored and the system bus information read out from the main memory for each request, the address the directory and the data buffer for the purpose of writing the address and the data. 16. System according to claim 14, characterized in that the adding device on the operating mode control device is connected to increment each main memory request address by one. 17. System according to claim 12 or 13, characterized in that that in the known state mentioned, all storage locations of the data buffer contain information which corresponds to the content of the information, velche in the memory locations of a corresponding one addressable area of the main memory is stored. 18. System according to claim 17, characterized in that the addressable area of the main memory Contains 4096 memory locations and that each of the 909828/0726 corresponding memory locations contains binary zero information in the event that the initiation signal is generated during a power-up sequence. 19. System according to claim 16, characterized in that that the mode controller is a bistable Switch element with set, reset and clock connections contains that the bistable element through the initiation signal supplied to the clock input terminal is switched to a first state and from the first state to a reset state in happens that a signal generated by the address generating means is sent to the reset terminal is supplied, and that the bistable circuit element in the specific state the memory request device causes the sequence of main memory requests to be generated. 20. A method for initializing a data processing system according to any one of claims 1 to 19 »containing a system bus line to which a main memory is connected that has a certain number of initial values in successive memory locations, with on the system bus line a cache memory is connected, which is a mode control device, the main memory request device and address generating means, the mode control means is connected to the system bus line, the main memory request device with d ^ r Operating mode control device is connected and wherein the address generation device is connected to the system bus line and is connected to the main memory requester, characterized in that a) that an initiation signal is generated on the system bus line, 909828/0726 b) that on the occurrence of the initiation signal in question, a specific memory request address is set in the address generation device, c) that on the initiation signal in question the Operating mode control device is set to a certain state or switched on, d) that upon activation of the memory request device by the operating mode control device, a first main memory request is generated when the specified state is present, e) that the specific memory request address is transmitted to the main memory as part of the main memory request via the system bus line, f ) that a sequence of main memory addresses and requests is generated by the address generating device or main memory request input, g) that the addresses as part of the requests to the main memory on activation by the main memory request device be transferred to h) that addresses are given to the system bus line in response to each of the relevant requests, wherein one of the lead-in values from main memory is one of those memory locations is read out until a corresponding address of the addresses concerned is designated, i) that the relevant introductory value is stored in a corresponding memory location in the cache memory Transfer of the cache memory to a known state is written. 21. The method of claim 20, wherein the cache memory includes a detector transmitter which with the address generation device, the system 909828/0726 bus line and the operating mode control device is connected, characterized in that a) that the transmission device detects the occurrence of signals from the address generating device and the system bus when all of the determined preamble values are stored in the cache memory are, b) and that with the help of the relevant transmission device, the operating mode control device of the determined state is switched to a reset state terminating the initiation operation will. 909828/0726