DE2843493B2 - Circuit arrangement for generating phase-difference-modulated data signals - Google Patents

Description

The invention relates to a circuit arrangement for generating phase difference modulated Data signals that an encoder contains, which is from a Data source output input signal representing the phase positions in two orthogonal channels divided code signals assigned using a read-only memory at predetermined sampling times Sums of products from the code signals and the time-limited impulse response of a Forms supporting values representing transmission filters and those with instantaneous values of orthogonal carrier signals outputs multiplied sums as data signals

From a publication "Microprocessor Implementation of High-Speed Data Modems" IEEE Transactions on Communications, Vol. Com-25, No. February 2, 1977, pages 238-250, it is known modems for a transmission of data with a transmission speed of greater than 1200 bit / s below Use of bipolar microprocessors to build. In the data transmitter of the modem, the Microprocessor the task of an encoder, which corresponds to a phase difference modulation two Outputs components of a vector to two orthogonal channels, a transmission filter and a modulator in each channel and an adder for the signals output at the outputs of the modulators. For the implementation of the transmission filter with the aid of the microprocessor is in the known modem Reference values of the impulse response of the transmission filter are stored in a read-only memory. The impulse response is limited in time and extends over several periods of the at the output of the encoder emitted code signals. The support values must therefore be used when generating the output signals of the Transmission filter are each multiplied by a corresponding number of code signals. It is also conceivable, instead of the reference values of the impulse response, the products of the components of the code signals and to save the support values as coefficients. In any case, a large number of commands are required by the Microprocessor required to depend on the code signals according to the transfer function of the .Sendefilters to generate the output signals. If the reference values are stored in the read-only memory these must be between two sampling times

are first multiplied by the code signals and then added up.

Ali's another publication, “Digital Generation of linearly modulated data waveforms ", IEEE Transactions on Communications, VoL Com-23, no. 11, p November 1975, pages 1259 to 1270, a digital filter is described in which the code signals in a Circulation register are stored, its output are connected to the first inputs of a multiplier, at whose second inputs a memory with ι ο is connected to the support values. The output of the multiplier is followed by an accumulator, the the products calculated with the aid of the multiplier are summed up

In the case of a high transmission speed, the stands for the multiplication and the subsequent Summation required time not available, so that a generation of the phase difference modulated data signals using an arithmetic unit is no longer possible without further ado.

DE-OS 26 44 478 discloses a circuit arrangement for generating phase-difference-modulated data signals, in which the data signals assigned to a dibit are generated alternately in two channels. The data signals generated in the two channels are multiplied by Arnplitudensigmalen and connected alternately to the transmission path in each channel is a shift register provided that the respective phase angle representing binary contains These binary bits to a multiplexer are supplied to the ATE binary alternately applies it to a read-only memory in the read only memory are Data words are stored which represent the products of the carrier signals affected by the phase angle and the amplitude signals. The output of the read-only memory is connected to a digital-to-analog converter via a complementing device that evaluates the sign of the instantaneous values. The two channels do not represent any orthogonal channels and only serve to generate soft transitions in the phase positions of the data signals in conjunction with the amplitude signals. Furthermore, the known circuit arrangement does not implement a transmission filter with a predetermined impulse response 4

It is already known phase difference modulated data signals using components of the Build up analog technology. However, these circuit arrangements have the disadvantage that the components of environmental conditions, such as the so Temperature and are dependent on manufacturing tolerances and that they do not readily affect others Change transmission speeds.

The invention is therefore based on the object of a Specify circuit arrangement for generating phase-difference-modulated data signals that largely works digitally and in which there are no multiplications and accumulations to implement the transmission filter, i.e. additions with subsequent storage are required.

According to the invention, the object is achieved in the circuit arrangement of the type mentioned at the beginning solved that a shift register is provided, each one associated with the duration of the impulse response Number of consecutive code signals stored 6Ί chert that the shift register is followed by a multiplexer which alternates the code signals of the two Channels to the first address inputs of the read-only memory are switched through that an address counter is provided is that is advanced by a sampling clock and its outputs with the second address inputs of the read-only memory are connected so that the read-only memory partial sums of the! products from the Contains supporting values and the code signals and at times determined by the content of the address counter outputs the partial sums simultaneously and that an adder stage is provided which multiplies the values with the instantaneous values of the orthogonal carrier signals Partial sums are summed up and the data signals emitted

The circuit arrangement according to the invention has the advantage that it requires little effort since neither multiplication nor accumulation is required, it enables high transmission speeds since no complex calculations have to be carried out. The circuit arrangement works with great accuracy because it stores the partial sums instead of the interpolation values or of the products, the rounding errors of the reference values or the products do not add up. In addition, the circuit arrangement requires, because of the division of the sum into several partial sums a low memory requirement. It would be conceivable, instead of the possible partial sums, also the possible To store total sums, but this would currently require a large amount of memory chips mean. The circuit arrangement is largely made up of digital components and therefore it is largely independent of component tolerances and environmental influences. Plus, it's easy to use Way switchable to other transmission frequencies.

The circuit arrangement is particularly advantageous for high transmission speeds Way usable when the adder is digital-to-analog converter contains to which the partial sums are fed and an analog working summing stage contains which is connected to the outputs of the digital-to-analog converter and which emits the data signals.

If the transmission speed allows it, it is advantageous if the adding stage is digital working full adder is formed, whose inputs the partial sums are fed and the to its output via a digital-to-analog converter Emits data signals

The modulation of the filtered signals with two orthogonal carriers, of which only the main values and the zero crossings are taken into account, is achieved in a particularly simple manner when in the connection path a buffer is provided between the read-only memory and the adder stage which, depending on the polarity of the carrier signals, inverts the partial sums or not get saved. The intermediate memory also eliminates the runtime tolerances of the read-only memory balanced.

A particularly favorable course of the transmission spectrum within the voice band is achieved when the filtered and modulated signals to the digital-to-analog converter not in the form of a step curve, but in The form of individual pulses can be supplied. For this purpose, it is beneficial if a reset input of the Buffer the sampling clock is supplied. This sampling cycle sets the after each sampling time Shift register back so that the digital-to-analog converters binary data words are only supplied for a short period in each case.

Addressing the read-only memory is particularly easy if it is represented by a vector of the phase differences, the resulting phase star is rotated in such a way that the vectors are always divided by two orthogonal components are represented. With an eight-stage phase difference modulation, it becomes rotated by 22.5 °. A favorable coding of the phases is achieved if the code signals match the phase positions encode by three binary characters, one binary character being the sign of the one assigned to the first channel horizontal component, a binary sign the sign of the assigned to the second channel vertical component and a binary sign the amount of the horizontal or vertical component indicates

If no suitable read-only memory is available that has the required storage capacity and which outputs two partial sums at the same time, it is advantageous if the read-only memory consists of several Storage units are formed from which the respective partial sums are read out simultaneously.

In the following an embodiment of the circuit arrangement according to the invention is based on Drawings described. It shows

F i g. 1 shows a vector illustration of phase positions in the case of an eight-stage phase difference modulation,

F i g. 2 timing diagrams at different points in the circuit arrangement,

F i g. 3 is a circuit diagram of the circuit arrangement. ■

In Fig. 1 shows the possible endpoints of vectors in a vector representation of an eight-stage phase difference modulation.The endpoints are rotated counterclockwise by a phase angle of 224 ° compared to a conventional representation so that none of the endpoints come to lie on the abscissa or ordinate axis. that a vector Vn is assumed which corresponds to a phase position of 67.5 ". The vector Vn has a small positive component pn in the abscissa direction and a large positive component qn in the ordinate direction each combined into tribits Assuming that the vector Vn is followed by a vector V (n + 1) in which the tribit corresponds to an angle M / of 135 ", this vector V (n +1) has a large negative component p ( n + 1) in the abscissa direction and a small negative component q (n + 1) in the ordinates direction. Depending on the further tribits, the following vectors can assume the endpoints shown. The vectors then form a phase star.

By rotating the phase star by ttfi " a particularly simple coding is achieved; the vectors and thus the phase positions. Whenever the vector has a small horizontal component, it has a large vertical component. It also has a large vertical component whenever it has a large horizontal component always a small vertical component. The horizontal component corresponds to the cosine and the vertical component to the sine of the angle between the vector and the positive branch of the abscissa axis. The phase positions can therefore be represented by code signals S, C and B. The code signal S gives the sign of the vertical component assigned to the sine, while the code signal C indicates the sign of the horizontal component assigned to the cosine are required to The amounts are coded using the binary character B, with, for example, the binary value B -0 being assigned to a short component and the inverted binary value B- 1 being assigned to a long component

In the case of the FIG. 2 shows the time t in the abscissa direction and the instantaneous values of signals at various points in the circuit arrangement in the ordinate direction . Furthermore, coefficients Kl, K 5 and K 6 are shown the products of components ρ of the vectors and the impulse response Hn of a transmitter provided in the circuit arrangement assigned.

It is assumed that the impulse response Hn extends over six period lengths Γ of the code signals QS and B representing the components ρ and q . Furthermore, it is assumed that nine reference values H of the impulse response Hn are present during each period Γ. Since the impulse response Hn upper extends six periods T of Sendefüters have the proportions of six impulse responses Hn are taken into account for determining the output signals. Since the values of the impulse responses Hn are only available at the sampling times, the output signals are only determined at these sampling times. The output signals are obtained according to the equation:

An = Σ Di-H {N-M + η-i ■ M) N = 0 ... MI.

where Af indicates the number of period durations over which the impulse response extends O / indicates the components ρ or q of the corresponding vector, H indicates the reference value of the impulse response and M indicates the number of samples per period T. In order to determine each sampled value An , for the assumed case, N -6 products must be formed from D wi and supporting values, and these products then added up. The sample values A 1 to A 9 result according to the following table:

Al = D \ ■ HAS + Dl // 36 + Z> 3 · HZl + DA ■ HlS + DS H9 + D6 HO Al = Dl- H46 + Dl - # 37 + D3 ■ HIi + DA ■ H19 + DS - ClO + D6 ■ St.

A9 = Dl HS3 + Dl - HAA + DT, ■ H3S + DA ■ HTA + DS ■ ΗΠ + D6 H ».

According to the table, for example, the output signal of the transmission filter is determined Time <3 according to the equation:

Al = Dl · // 46 + Dl // 37 + Di HlH + D4 ■ // 19 + DS ■ // 10 + D6 HX.

In the illustration in FIG. 2, for the sake of clarity, only the components ρ and not the components q are shown. In addition, the components ρ are shown uncoded. The components ρ 5 and ρ 6 correspond to the components pn and p / 7 + 1 in FIG. 1. To determine the output signal of the transmission filter between times ti and f4, the impulse responses assigned to the components ρ 1 to ρ 6 are taken into account. The coefficients Ki, K 5 and K 6 represent the basic values H of the impulse response Hn multiplied by the components ρ Ij η S and ρ 6 Impulse response Hn is made up of a main oscillation that extends over two periods Γ and two pre-oscillations and two post-oscillations. It corresponds to one Function and is based on the six periods T.

limited

The output signals of the transmission filter are matched with two orthogonal carrier signals 7771 and 77? 2 multiplied The repetition frequency of the carrier signals TR 1 and 7772 is matched to the intervals between the samples determined by the sampling signals AT that only the main values and the zero crossings of the carrier signals 7771 and 777 2 are used at the sampling times when one of the carrier signals 7771 and 777 2 assumes the main value, the other carrier signal 7772 or 7771 has a zero crossing. There is also no need for an adder to add the modulated signals, since one of the trigger signals 7771 and 777 2 always has the value 0

Further details of the timing diagram are given together with the circuit diagram shown in FIG described.

In the case of the in FIG. 3, a data source DQ outputs the signals DS i representing the data to be transmitted at a repetition rate of, for example, 4800 bit / s to an encoder CD . This, controlled by clock pulses TA 1, combines three binary characters of the signals DSi to form a tribit and assigns this tribit in each case a predetermined phase difference that corresponds to the rotation of the vector in FIG. 1. The coder CZ? emits code signals £ B and C that describe the position of the vectors. The code signals 5 indicate the sign of the component 9, the code signals C indicate the ss sign of the components ρ, while the code signals B indicate the magnitude of the component 9. The inverted code signals B then give the magnitude of the components pan.

The circuit arrangement contains a shift register formed from three registers Ri to / 73, which, controlled by clock pulses TA 2 with a repetition frequency of 1600Hz, stores the code signals S, B and Cin the registers Rl to R 3 Output signals of the transmission filter each have to take into account six coefficients assigned to the impulse responses of the various components. The outputs of the shift register are connected to the data inputs of a multiplexer M in such a way that it alternately switches the signals S or C and B or B through to its outputs. The multiplexer M is controlled by clock pulses MTmii with a repetition frequency of 3.6 kHz. With this repetition frequency of the multiplexer M to be at the output alternately ρ the two orthogonal components and q values assigned to be the result of signals Z to first address inputs of a switched from two memories SPl and SP2 only memory formed on the second address inputs of a continuously connected by the sampling clock AT scan counter AZ to be submitted.

All possible partial sums in which the code signals S1 to 5 3, C1 to C3 and Bi to B 3 or Bi to B 3 are involved are stored in the memory SPi. In a corresponding manner, all possible partial sums T2 , in which the code signals 54 to 56, CA to C6, B 4 to B 6 and B 4 to B6 are involved, are stored in the memory SP 2. The partial sums Ti and Tl are issued simultaneously, namely at the times determined by the count of the address counter AZ. The partial sums Π and Tl are stored in a buffer ZS by means of an acquisition clock UB with a repetition frequency of 7.2 kHz. The stored partial sums Γ11 and Γ21 are then sent to an adder stage. The adding stage consists, for example, of a digital full adder which adds the two partial sums 7Ί1 and Γ21 available in digital form and which is followed by a digital-to-analog converter, at the output of which the phase-difference-modulated data signals DS are output. The adder stage can also be formed from two digital-to-analog converters DA 1 and DA 2 and a downstream, analog-working adder SL '. The digital-to-analog converters DA 1 and DA 2 generate the analog signals 7Ί2 and Γ22 assigned to the partial sums Γ11 and Γ21 and the adder composed of an operational amplifier V and three resistors / 71 to / 73 adds the analog signals Γ12 and T22 and outputs the data signals DS from its output.

As already indicated, the modulation of the output signals is of the transmission filter by alternating multiplication by the main values of the carrier signals 7771 and 777 2. For this purpose, the buffer ZS a modulation signal MD supplied at a repetition frequency of 1800Hz, the always in the buffer store ZS Stores partial sums Ti and Γ2 inverted or non-inverted if the carrier signals 7771 and 7772 have a negative or positive sign. The buffer ZS is also reset with the sampling rate ΑΓ with the repetition frequency of 14.4 kHz, so that the signals Γ12 and Γ22 do not have a step-shaped course, but a pulse-shaped course and a favorable spectral distribution of the data signals DS is achieved.

At time f2 in FIG. 2, all components ρ 1 to ρ 6 and 91 to 9 6 are stored in the shift register by the code signals S, C and B. The clock pulse AfThat has the binary value 1 and the multiplexer M switches

10

the values assigned to the components ρ to the read-only memory. The sampling counter AZ, which is continuously counted from 0 to 8 in order to obtain the nine samples of the data signal DS , has the counter status 0. The partial sums Ti and T2 are read out of the read-only memory, those below that of the signals Z and that of the multiplexer M signals given are stored. The partial sum Tl is the sum of the products

p \ C45 + p2 ■ C36 + p3 C27,

while the subtotal T2 is equal to the sum of the products

p4 * C18 + p5 * C9 + p6- CO. _{| 5}

The products ρ 1 · // 45, p5 · // 9 and p6 · HO are represented by the coefficients Ki ₁ KS and K 6 at time 12. The carrier signal 77? 1 has the value 0 at time r2 and is not taken into account for the modulation. The carrier signal 7 "2 has a positive sign and the modulation signal MD therefore has the binary value 1. The partial sums Π and T2 are thus not inverted by the signal UB in the character memory ZS stored with the trailing edge of the sampling clock AT is the buffer store ZS cleared so that Pulse-shaped signals 7 * 12 or Γ22 are emitted at the digital-to-analog converters DA 1 and DA 2.
At time / 3, the clock pulse MT has the binary value 0 and therefore the code signals C 1 to C6 and Bi to B6 assigned to the components q are switched through to the read-only memory.The sampling counter AZ has the value 2 and the data signal DS becomes this from the read-only memory Time associated partial sums 7Ί and T2 read out. The carrier signal 77? At this point in time, 2 has the value 0, while the carrier signal Tl has a negative sign. The modulation signal MD has the binary value 0 and the partial sums T1 and T2 are inverted and stored in the intermediate memory ZS for modulation. Similarly, the data signals DS to the sampling instants 4, 6 and 8 are determined At the sampling 1,3,5 and 7, the data signals DS only during the next following period T determined Subsequently, again the determination of the data signals DS to the even sampling instants.

It is also possible not to store partial sums T1 and T2 in the read-only memory, but rather all possible total sums. However, this requires a very large amount of memory. By storing two or more partial sums, which are then summed without accumulation, this memory requirement is greatly reduced For example, the read only memory can then from the two memories SFl and be constructed SP2, each having a storage capacity of 8 kbit.

For this purpose 2 sheets of drawings

Claims (8)

Patent claims: 1. Circuit arrangement for generating phase difference modulated data signals which contains a coder, the input signals emitted by a data source, the phase positions assigns representative code signals which are divided into two orthogonal channels and which are generated using a Read-only memory sums of products from the code signals at specified sampling times and forms support values representing the time-limited impulse response of a transmission filter and the sums multiplied by instantaneous values of orthogonal carrier signals as data signals dispenses, characterized in that that a shift register (R 1 to R 3) is provided which stores a number of successive code signals (S, B, C) assigned to the duration of the impulse response,
that the shift register (R 1 to A3) is followed by a multiplexer (M) which alternately connects the code signals (S, B or QB) of the two orthogonal channels (p, q) to the first address inputs of the read-only memory (SP 1, SP2) ,
that an address counter (AZ) is provided which is incremented by a sampling clock (AT) and whose outputs are connected to second address inputs of the read-only memory (SP 1, Sf 2),
that the read-only memory (SPI, SP2) partial sums (Ti, T2) of the products from the supporting values (H) and the code signals (S, B, C) and by the content of the address counter (AZ) fixed times the partial sums (Ti, T2) outputs and at the same time that an adder stage (DA i, DA 2, SU) is provided which sums the partial sums (TU, 7 * 21) multiplied by the instantaneous values of the orthogonal carrier signals (TRi, TR 2) and outputs the data signals (DS) 2. Circuit arrangement according to claim 1, characterized in that the adding stage contains digital-to-analog converters (DA i, DA 2) to which the partial sums (TU, T2i) are fed and contains an analog summing stage (SU) which is connected to the Outputs of the digital-to-analog converter (DA 1, DA 2) is connected and which emits the data signals (DS ^ 3. Circuit arrangement according to claim 1, characterized in that the adding stage is formed from a digitally operating full adder, the inputs of which are supplied with the partial sums (TU, T2i) and which emits the data signals (DS) at its output via a digital-to-analog converter 4. Circuit arrangement according to one of claims 1 to 3, characterized in that a buffer iZSJ is provided in the connection path between the read-only memory (SPi, SP2) and the adder, in which the partial sums depending on the polarity of the carrier signals (TRi, TR 2) (Ti, 7 * 2) can be saved inverted or non-inverted. 5. Circuit arrangement according to claim 4, characterized in that the sampling clock (AT) is fed to a reset input of the intermediate memory (ZS). b5 6. Circuit arrangement according to one of claims 1 to 5, in which the phase positions of the data signals are represented vectorially, characterized in that the resulting phase star is rotated such that the vectors (Vn, V (n + 1)) always by two orthogonal components (pn, qn and p (n + 1), φ + 1)). 7. Circuit arrangement according to claim 6, characterized in that the code signals (S, QB) encode the phase positions by three binary characters, a binary character (C) the sign of the horizontal component (q) assigned to the first channel, a binary character (S) the The sign of the vertical component (p) assigned to the second channel and a binary sign (B ) indicates the amount of the horizontal or vertical component (q or p) 8. Circuit arrangement according to one of the preceding claims, characterized in that the read-only memory is formed from a plurality of memory units (SPi, SP2) from which the respective partial sums (Ti, 72) are read out simultaneously.