DE2843217A1 - HIGH-RESOLUTION ANALOG-DIGITAL CONVERTER - Google Patents

Description

GENERAL ELECTRIC COMPANY, 1 River Road, Schenectady, New York 12305 (USA)

High resolution analog to digital converter

The invention relates to a high-resolution analog-to-digital converter with cargo transport.

The resolving power of such devices is well known determined by two factors:

a) The size of the measured charge packages can be determined by

the voltage value of the measured signal will be affected. That is, the forward voltage of the MOS transistor, which is used for charge measurement can be a function of the drain voltage of this component so that the twist source reaction in the so-called bucket chain circuit increases the accuracy of the measurement can limit.

b) The storage capacitor that absorbs the measured charge packets is a MOS capacitor that is placed on the same Chip like the MOS transistor component of the converter circuit is formed. It has been assumed that this capacitor acts linearly; however, in fact, the semiconductor surface area next to be depleted the metallic capacitor coating as it is a

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19-3) heavily doped p + region (for example 10 cm is, depending on the signal voltage on the other side of the capacitor metal plate. Of the Capacitor is consequently non-linear and this non-linearity is an elementary limitation the resolving power of the converter.

It is the object of the invention to provide an analog-to-digital converter in which the forward voltage of the transistor measuring the charge packets has a smaller influence on the charge packet size and in which the storage capacitor acts linearly. To solve this problem, the inventive high resolution Analog to digital converter characterized by the features of the main claim or the secondary claim 6 .

In the subject matter of the invention, this is the control voltage sampling capacitor completely contained in the capacitance of the p-n junction. This leads to how later is shown to the fact that the size of the capacity at the end of the transfer cycle of the measured charge packets reaches its smallest value, so that the effect of changing the forward voltage is minimized.

Furthermore, the storage capacitor, which was previously a MOS capacitor, is part of the subject matter of the invention optionally also designed as a discrete capacitor, which is supported by an oxide layer on the chip isolated and on a first electrode made of molybdenum or the like on the oxide coating of the chip Applied metal is formed, with a dielectric oxide coating on the molybdenum electrode is applied and based on the

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dielectric oxide coating, which is an aluminum or corresponding metal coating
serves as the second electrode of the storage capacitor. The aluminum coating is also used as a source electrode for one of the measuring transistors.

In the drawing is an embodiment of the
Subject of the invention shown. Show it:

Fig. 1 shows a semiconductor wafer on which the inventive Circuit is formed, the circuit shown being part of the analog-to-digital converter is, in a cross section,

FIG. 2 shows a part of the wafer according to FIG. 1, in a plan view,

3 shows a circuit diagram of the arrangement according to FIGS. 1 and 2. as

Fig. 4 pulse diagrams and a timing diagram for

the circuit according to FIGS. 1, 2 and 3 over a common time axis.

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The novel way in which a capacitor is used to Sampling of the control voltage and a charge storage capacitor is shown for capacitors C. and nC in FIGS. 1 and 2, respectively. Marriage, however describes the novel design used for these capacitors, the circuit (the one common circuit) using these capacitors described in connection with Figs. 3 and 4, so as to provide a suitable background for understanding the invention.

In FIG. 3 and the following explanation, the circuit is described as if it were on a common Semiconductor wafer is integrated; the circuit is also shown in p-channel design. Accordingly, are related to ground, all voltages negative. The circuit can also have an n-channel design, wherein then all polarities are reversed.

The circuit shown in FIG. 3 has five MOS transistors T ₁ , T-, T-, T. and T ₅ , respectively. One electrode of the capacitor C. for sampling the control voltage is connected to the node X between the transistors T ₁ and T ^ , while its other electrode is connected to the ground of the circuit. One electrode of the charge storage capacitor nC is connected to the node Y between the transistors Tj and T- and its other electrode is connected, as shown, between the signal input transistors T ₄ and T ₅ .

A voltage source V _DD is connected to the source electrode of the transistor T ₃ , while the control voltage Vp is connected to the source electrode of the transistor T ₁ . An analog input voltage that is converted into a

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28A3217

digital value is to be converted is, as shown, applied between the connections V ₁ and V ₂ . The node Y is connected to the input terminal of a Schmidt trigger A, which in turn supplies an output signal for the logic circuit 10. A clock generator 11 is also connected to the logic circuit 10 and a digital counter 12. The logic circuit 10 controls the counter 12, which generates the digital display which corresponds to the analog input signal present _{at the connections V 1} and V _2.

The operation of the circuit according to FIG. 3 can best be understood with reference to the voltage pulse diagrams and the timing diagram according to FIG. 4. During an interval in Fig 4 depicted t. .. the transistor Tc is turned on and thus a node Z with the relatively positive terminal V ₁ (which may be grounded or connected to the positive input of the differential input), respectively. The transistor T ₃ is also turned on and the node Y is instantly charged _{to the voltage V 1.} It should be noted that the voltage V ₁ must be more negative than the switching voltage V._ of the comparator A.

The transistors T ₁ , T ₂ and the capacitor C are used to generate and transfer charge packets q. from node Y to node X. In this way, when T ₁ is on, node X is set to the value of the S expensive voltage V-. brought. When T _{1 is} blocked and T ₂ is turned on, the node X consequently assumes a voltage (V -V-,), where V is the amplitude of the _{gate voltage applied to T 2} during the turn-on and V_ is the input voltage of the transistor.T ₂ is. The size of the charge transferred to node 'Y during each clock cycle

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packages is;

With each clock cycle during the time t .. therefore increases the voltage of the node X in the positive direction by an amount z-JW, where:

δ ν = q./nc= ^c j <yw

nc

At the end of t .. the voltage of the node Y exceeds the switching voltage V ^ of the comparator A, which is recognized by the logic circuit and thus the states. from JZL and jfj- are reversed, so that now T ^ is blocked and T. is controlled through. As a result, the node Z is connected to the signal voltage terminal V ₂ and the node Y is negatively charged to the voltage V ".

An interval t ₂ now begins, during which again charge packets q. fed into node Y and counting the number of charge packets, '. which are necessary to reload the node Y to the value of the switching voltage V .. of the comparator A. This counter reading is now a measure of the input voltage of the analog signal.

At the end of interval t ₂ , node Y is again precharged to voltage V- and the cycle is repeated.

In the past, the capacitor C. was designed so that it had a relatively constant value, while the capacitor nC was a MOS capacitor, the value of which changed nonlinearly when the

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Voltage at node Y has been changed. The construction of the capacitors C. and nC is now so improved that the resolving power of the circuit is increased.

FIGS. 1 and 2 show the novel structure of the chip. A single crystal silicon chip 30 is provided with a silicon dioxide coating 31 on its upper surface 30a. A first metallic pattern is formed on the silicon dioxide, it being possible for the metal to be molybdenum, which is shown in FIGS. 1 and 2 as molybdenum sections 33 to 38. In Fig. 1 only the sections 33, 34 and 38 are shown. The molybdenum coatings 33 to 37 correspond to the gate electrodes for the transistors T ₁ and T ₅ , while the coating 38 serves as the lower electrode of the capacitor nC.

On the chip 30, p-doped regions, for example the regions 40, 41 and 42 according to FIG. 1 and the regions 40 to 46 according to FIG. 2, are formed by a self-registration process, so as to form the source and drain regions of the transistors T .. to T ₅ to generate. Accordingly, eimp-doped silicon dioxide coating 50 is applied over the entire area of the neutral oxide coating and the metallic coating 33 to 38. The chip is then heated in order to cause the p-ions of the coating to diffuse into the single-crystal silicon chip 30 and to fill the p-doped regions up to 46. A more detailed description of this process can be found in U.S. Patent No. 4,002,513. It should be understood that other techniques, such as ion implantation or the like, can just as well be used to form self-inserting transistors, ie the source and drain regions are to be closed.

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limited at least partially by the outer delimitation of the gate electrode regions previously produced on the chip ¹ .

The p-doped oxide coating 50 is then masked and provided with recesses leading down, so that a second metallic coating made of aluminum or similar material, the connections and contacts for predetermined p-regions, (e.g. terminal 60 makes contact with p-region 40 and is carried by the neutral oxide region 70, furthermore the terminal 62 makes contact with the p-region 42 and is supported by the p-doped oxide region 50c lying above the first metallically coated region 38) . In this way, the first oxide coating 31 is now divided into insulating areas, for example the areas 70, 71 and 72, whereas the second (doped) oxide coating 50 in other areas is divided, for example, areas 50a, 50b and 50c, each of the latter areas being a Covering patterns from the first metallic coating, e.g. patterns 33, 34, 38.

It should be noted that all of the other components shown in FIG. 3 can also be included on chip 30, however none of these components in FIGS. 1 and 2 become apparent shown.

As shown in Fig. 1, the capacitor C. is a pure one p-n capacitor, while capacitor nC is a molybdenum-silicon dioxide-aluminum capacitor (or a sandwich of two * metals and a non-conductive film).

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The capacitance of the capacitor C decreases with the voltage V.

2 V /

(U

-1 where: q is the electron charge constant (1.6 χ Coulomb), k is the relative dielectric constant of Silicon, £ the dielectric constant of the vacuum (8.85 χ 10 Farad / cm), N the doping density the heavily doped side of the junction between the p-doped region 41 and the substrate 30 and V. die Voltage at the junction. Accordingly, at the end of the charge transport process, C. has its smallest value, as V. is at its greatest value at this time. The charge transferred during each cycle is given by:

where V is the initial voltage at node X, V the c g

Amplitude of the gate voltage applied _{to transistor T 2 and V "T is} the forward voltage of T ₂ when the amount of charge q has been transported to its drain electrode. Although V can vary with V from cycle to cycle, the corresponding change in the total transferred charge is on this is noticeably reduced because the capacity is at its minimum value at the end of the transmission interval

(3)

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ie q _NL - A [(V _g -V _T ) ¹ Z ² -V // ² ^ where q _{NL is} the total amount of charge transferred and A = 2qke N, The following applies to the charge transferred in conventional circuits:

q _L = C | V "-V _m -Vj (4)

here q is the total transferred charge and C. a linear one. Capacity.

When the sensitivity to the measured charge packets in relation to the changes in the forward voltage is defined as /

S for ZXLX (5)

^d V ^V G

then for the conventional (linear) case:

and for the non-linear case from the execution example applies:. ·

i (7)

1/2 1/2

₃ ⁽ VV

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so that the improvement of the sensitivity, the from the use of the non-linear capacitance C. results, is described by the following equation:

² 1 VV * c ^c WI

(8th)

A close look at equation S shows that the nonlinear case at V = O is the least sensitive; at this point the circuit is 2 times less sensitive than a conventional circuit. At the other extreme _f ie if V = V - V, they are

c g T

Sensitivities of both circuits are the same and both become extremely large _r so that optimal operation requires a V whose operating point is set as close as possible to Mull.

L e r s e i t e

Claims (8)

Patent attorneys Dipl.-Ing. W. Scherrmann Dr.-Ing. R. RUger 7300 Etslingen (Neckar), Webergasse 3, PO Box 348 • i never + · 1978 'phone ■ * · ? 7T ' Stu .. "art (0711) 356539 PA 151 bawa 359619 Telex 07 25H10 smru Telegrams patent protection Esslingenneckar Claims (\) High-resolution analog-digital converter with charge transport, characterized in that it is a control voltage source (V ). a capacitance (C.) for scanning ^c j the control voltage (V ). a storage capacitor (nC) and for transferring the charge packets between the the control voltage (V) sampling capacitor (C.) ■ c] and the storage capacitor (nC) has a measuring transistor circuit (T. / Tj) and a circuit device (T., T _g ) for the analog signal input voltage is connected to the storage capacitor (nC), while for counting the number of charge packets that are used for Charging of the storage capacitor (nC) are transmitted to a value determined by the input signal, the storage capacitor (nC) is connected to an output circuit device (A, 11,12) and a digital counter reading related to the analog value of the analog input signal can be generated as a result, and that the sampling capacitor (C.) consists only of the capacitance of a pn junction. 2. A circuit according to claim 1, characterized in that the sampling capacitor (C, ) _/ the .messende transistor circuit (T ₁ J _7, the input circuit device (T., T ₅ ) and the output circuit device (A, 11, 12) on a common Semiconductor substrate (30) are formed. 909815/0945 3. A circuit according to claim 2, characterized in that the storage capacitor (nC) has a first on the surface of the chip (30) applied metallic coating (38), which is a first electrode of the storage capacitor (nC) forms a dielectric coating (50c) applied to the first electrode (38) and a second metallic coating (62) applied to this dielectric coating (50c) which represents a second electrode of the storage capacitor (nC) and that the storage capacitor (nC) is free from the properties of the depletion coating. 4. A circuit according to claim 2 or 3, characterized in that the measuring · transistor circuit (T ₁₁ T ₂ ) * the input circuit device (T ,, Tg) and the output switching device (Ä, 11,12) each components of the type of MOS -Transistors have. 5. A circuit according to claim 4, characterized in that the MOS components each have metallic electrodes (33 to 37) and the metallic electrodes (33 to 37) are MOS devices on the same plane as the first electrode (38) of the storage capacitor (nC) lie. 6. High-resolution analog-to-digital converter with charge transport, characterized in that it is a control voltage source (V_), a capacity (C.) zuipkbtasten ^c J the control voltage, a storage capacitor (nC) and for the transfer of charge packets between the capacitor (C.) which samples the control voltage and the storage capacitor (nC) has a measuring transistor circuit C5, T ₂ ) and with the storage capacitor J 0 9 8 1 5/0 9 4 5 (nC) a circuit device (T-, T ₅ ) is connected for the analog signal input voltage , while for counting the number of charge packets that are transferred to a reference value for recharging the storage capacitor (nC) based on an initial value determined by the analog input signal , the storage capacitor (nC) is connected to an output circuit device (A, 11,1.2) and thereby a digital counter reading related to the analog value of the analog input signal can be generated, and that the storage capacitor (nC) has one on the surface (30a) of the semiconductor chip (20 ) applied, metallic coating (38), which represents a first electrode (38) of the storage capacitor (nC), a dielectric coating (50c) applied to the first electrode (38) and a second metallic coating applied to the dielectric coating (50c) (62) which forms a second electrode (62) of the storage capacitor (nC). 7. A circuit according to claim 6, characterized in that the sampling capacitor (C), the measuring transistor circuit (T ₁ JT ₂ ), the input _{circuit device (T., T 5} ) and the output circuit device (A, 11,12) on the dem- the same semiconductor chip (30) are formed. 8. A circuit according to claim 7, characterized in that the measuring transistor circuit (T ^, T ₂ ), 'the input _{circuit device (T., T 5} ) and the output circuit device' (A, .1.1 _£ 12.) each components of the type the MOS transistors included. 909815/0945