DE2842546A1 - REFERENCE SOURCE ON AN INTEGRATED FET BLOCK - Google Patents

Description

SIEMENS AKTIENGESELLSCHAFT Our reference Berlin and Munich VPA ^ _{6245 BRD}

Reference source on an integrated FET chip.

The invention relates to an electronic arrangement, namely a special reference source, that is, a Reference voltage or a reference current more defined.

Size. The invention was particularly made in n-channel technology for feeding the R / 2R networks from D / A converters, i.e. PCM / AM decoders, and above especially from A / D converters, i.e. AM / PCM encoders, in particular also for charge-to-voltage and voltage-to-charge converters belonging to the converters CCD filters of a special PCM telephone switching system made up of highly integrated components developed. This includes the reference sources, R / 2R networks and other converter components and also the filters on the same FET chip. the However, the invention is also suitable for any FET components that have a subsequently precisely adjustable Reference voltage or a subsequent very accurate

Be 1 Ky / 25.9.1978

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need adjustable reference current.

The invention is based on a reference source on an integrated FET module, with - two separate stages fed by the same DC power supply, each connected in series contain at least one IG-FET and at least one working resistor,

- one tap between one of the IG-FETs and one of the work resistances is appropriate in each stage, and

- A differential voltage of a defined value occurs between the taps of the stages, which directly itself as a reference voltage, or indirectly for setting the value of a reference voltage or a Reference current, e.g. by means of a voltage divider, is used.

Such a reference source is already in ESSCIRC (European Solid State Circ. Conf.) 1977, Ulm

September 20-22, 1977, Digest of invited papers and contrib. papers, p. 43 to 47, especially p. 44, right column, penultimate paragraph described. For this purpose, it is suggested that the IG-FETs of both stages be constructed differently, namely on the one hand with a depletion type channel area, on the other hand with an enrichment-type channel area, «m to utilize their different threshold voltages. In conclusion, however, there is also a reference to the need for development work to be carried out first are necessary until a reference source for an integrated module is found that can also be used. The scattering of the properties due to the unavoidable tolerances in the production are in this Obviously very uncomfortable case. In particular, the installation of various types of duct areas in the

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both stages results in uncomfortably difficult problems with the associated tolerances.

The invention solves these difficulties with regard to manufacturing tolerances when using IG-FETs, which, in particular because of these manufacturing tolerances, have different characteristics, as in the case of the invention after the component has been manufactured, the size of the reference voltage can be subsequently easily implemented or the reference current should be freely, permanently and continuously adjustable.

The IG-FETs of the stages of the invention may each have any p-channel or η-channel, any of the depletion type or the enrichment type. The channel area can also be p ^{+ -doped with p-channel or n +} -doped with η-channel, i.e. represent a "blocking type" channel area that has a greatly increased control gate / source threshold voltage (threshold voltage or cut-off voltage), at which a source-drain current begins to flow. The structure of the IG-FETs, and also the structure of the driving circuit of these IG-FETs, is not limited to a single special variant, so that the range of use of the invention is correspondingly large.

The invention does not necessarily require the use of the for measures known to have balancing effects, such as subsequent irradiation with high-energy corpuscles, heating until the doping profile changes or point-by-point processing with a laser, ahead. In the case of tube circuits, such a subsequent adjustment would be known relatively easy by replacing resistors, rotating resistors etc. in the one controlling the tube Circuit feasible. With integrated modules

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As is well known, it is also possible to add adjustable components for adjustment outside the module, which is an inelegant, space-consuming adjustment measure. In the invention, therefore, the adjustment not carried out outside of the module, nor within the driving circuits of the IG-FETs.

The invention even allows this measure to be carried out completely if inadvertently initially too strong an adjustment or partially weakened again until the adjustment with the desired strength or accuracy is achieved. The adjustment can therefore even be carried out reversibly several times by means of certain adjustment measures, and with If necessary, it can also be adjusted to a different state.

It is in itself already used in many publications, e.g. LU-PS 72 605, for storing Signals used special IG-FET with source, channel area, drain, isolator and controllable control gate known, in addition to enabling the storage of the signal, between its control gate and channel area contains a conductive memory gate surrounded on all sides by the insulator. The threshold voltage is set by the charge reversal and the source-drain current / control gate-source characteristic, depending on the extent and polarity of the Reloading, more or less shifted to more positive or negative voltage values. Such storage gates are e.g. in an η-channel by electrons heated in the conductive channel area by means of an accelerating Source-drain voltage can be recharged, i.e. recharged by means of so-called channel injection. The storage gate can also be reloaded by charges generated and heated at the blocking channel area-drain junction, thus by means of the avalanche effect. The memory

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gate can also be reloaded by charges that are heated up by means of voltage pulses on the surface of the channel area are also reloaded by charges heated up by means of voltage pulses on the memory gate surface will. The memory gate is also through the Fowler-Nordheim tunnel effect reloadable, as well as by non-electrical measures, e.g. by means of irradiation with light. All of these reloading operations, i. H. Charging or discharging of the storage gate are with such IG-FSTs Memory gate known from a variety of publications. It is also known to use the memory gates to charge one of these effects and to discharge it again by means of another of these effects. These effects are used to shift the operating point or the characteristic curve of an IG-FET amplifier stage operated with alternating signals with memory gate in the German application filed at the same time as the present application P (= 77 E 6189a) suggested.

For example, Proc. 5th Conf. on solid state Dev., Tokyo / Supplem. to J. Japan Soc. of Applied Physics 45 (1974) 34S to 355, in particular p. 354, § 5, as well as by Electronics, July 11, 1974, p. 29/30, such IG-FETs with memory gate as analog signal memory to use. For this purpose, the storage gate is charged proportionally to the analog amplitude of the signal to be stored, later this stored analog amplitude is read out again by adding a has an analog amplitude corresponding to the stored analog signal.

The invention is based on a reference source on an integrated FET module, with

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- two separate stages fed by the same DC power supply, each the series connection contain at least one IG-FET and at least one working resistor,

- one tap between one of the IG-FETs and one of the load resistors is attached in each step, and

- A differential voltage of defined Wzrbts occurs between the taps of the stages, which is used directly itself as a reference voltage, or which is used indirectly to set the value of a reference voltage or a reference current, for example by means of a voltage divider.

The above object of the invention is achieved in that

- In at least one of the two stages, at least one of the IG-FETs is at least partially between the controllable Control gate and the channel area, surrounded on all sides by an insulator and therefore in electrically related floating memory gate contains.

The reference source becomes less sensitive to fluctuations ») if, according to patent claim 2, the parallel connection of both stages is in series with a high-resistance emitter follower resistor. *) The same power supply voltage

Such an IG-FET can match the reform source without affecting other components on the module are by, according to claim 3, the electrodes of this IG-FET containing the memory gate with their own Connections, e.g. with aluminum patches, of the integrated module, which after manufacture of the IG-FET, at least before the device is encapsulated.

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The level, i.e. the potentials, and also, if necessary, the amplitude of the differential voltage Mamsn according to patent claim 4 can be changed by having each of the two inputs of a differential amplifier each with is connected to the tap of a stage. In particular, such a reference source is basically both as a reference voltage source as well as a reference current source according to the selectable internal output resistance of the differential amplifier can be used. It can be used in particular as a reference voltage source if according to claim 5, an output of the differential amplifier is connected to a first voltage divider whose tap is connected to the control gate of one of the IG-FETs of the first of the two stages. She is particular can be used as a reference current source if, according to claim β, an output of the differential amplifier with a first voltage divider is connected, the tap of which is connected to the control gate of at least one of the IG-PETs the first of the two stages is connected, the same output of the differential amplifier with a second Voltage divider is connected, the first divider element of which is connected directly to the output of the differential amplifier and whose other divider element represents the load resistance to be supplied with the reference current, and the tap of the second voltage divider is connected to a third voltage divider whose tap in turn, at least one of the IG-FETs of the second stage is connected to the control gate.

The reference source not only supplies direct voltages or direct currents, but alternating voltages or currents with a later adjusted operating point, if according to claim 7 at least one of the IG-FETs and / or at least one of the associated f / i of the stands of the two stages is connected to a control input for superimposing a controlling alternating signal. There-

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through is the reference source namely at the control input controllable, whereby e.g. the direct currents or direct voltages can be switched on and off by according to claim 3, a binary alternating signal is fed to the control input. The direct currents or DC voltages can also be modulated with analog signals by using the control input an analog alternating signal is fed in.

The invention and its developments are further explained using the examples shown in the figures, whereby

1 schematically shows the reference element stimulated by the above-cited document ESSCIRC, Fig. 2 shows a stabilized against DC power supply fluctuations and against temperature fluctuations Example of the invention,

Fig. 3 threshold voltage / charging time diagram as an example for the effects of time and drain biases during charging by means of the Canal injection,

3 details of an example of a reference voltage source according to the invention,

5 shows a known example of a reference current source, and

Fig. Β the further developed by the teaching according to the invention Example of Fig. 5 show.

Fig. 1 shows that by using ESSCIRC two IG-FETs are excited with different types of channel areas, which apparently have at least one working resistance each R1, R2 should have. When loaded with currents J1, «3" 2 of the DC power supply source occurs between the taps a particular immediately as

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Reference voltage usable differential voltage RS. ESSCIRC does not specify how this is done in detail Differential voltage RS is used. For example, a change in level would be conceivable, possibly also amplification by means of a Differential amplifier DV in order to use its output signals U3 / J3 as references only indirectly. In ESSCIRC is also nothing about the size of ΌΊ, U2, U1O, U20 reports. But one can assume that there are constant potentials, e.g. earth or other constant Operating voltages are present that the IG-PETs F1, P2 in control their conductive state so that due to the diversity of their channel area types, viz Depletion type and enrichment t3rp, at the taps or at the inputs of the differential amplifier DV one of the desired reference voltage U3 or the desired reference current J3 corresponding differential voltage RS occurs. The manufacture of such IC-FETs P1, F2 requires but very tight, barely observable manufacturing tolerances to make such an arrangement as a reference source really to be able to use.

According to the invention, this difficulty is eliminated by at least one of the IG-FETs, e.g. F1, between its The control gate and channel area have a memory gate that is electrically floating, see FIG. 2. After the component has been manufactured, this memory gate is either positive or negative more or less chargeable or discharging, that is, reloading, and thereby the characteristic curve and the threshold voltage of the relevant IG-FET can be moved continuously as required. The IG-FET in question is thus operated in a similar way to the IG-FET described, for example, by Electronics, July 11, 1974, pp. 29/30, used as an analog signal memory with storage gate. In the invention, however, the IG-FET or IG-FETs concerned with memory gate F1, F2 are used not just for writing, storing and reading analog

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Signals, but for the stepless setting of the constant operating point of the entire reference source in order to compensate for the errors in the reference voltage or the reference current, which were initially caused by the inevitable manufacturing tolerances of such a complicated reference source. In order to reload the memory gate in such a way that the other components of the module are spared, the electrodes of the relevant IG-FET, see the control gates, sources and drains of the IG-FETs with memory gates F1, F2 in FIG connect directly to the module's own connections, e.g. with the aluminum patches A1, A2, A3 for F1 and A5, A2, A4 for F2. These connections, which should still be accessible after the IG-FET in question has been manufactured, can e.g. by touching live tips, are supplied with voltages that ¹ carry out the charge reversal of the memory gate and thus the precise adjustment of the reference voltage or the reference current, eg RS or U3 / J3. The differential amplifier DV thus supplies the reference variables U3 and J3 with the polarity and size that can be set as required by the polarity and size of the differential voltage RS after the reference source has been produced subsequently 'on the block steplesslySjz.B. accurate to 1 mV, in that the values of the load currents i1, i2 can be subsequently adjusted as required by reloading the storage gates of the IG-FETs F1, F2.

The example shown in Fig. 2 also differs from the example shown in Fig. 1 in that the potentials U10, U20 for both IG-FETs F1, F2 are the same because both stages F1 / R1 and F2 / R2 are conductive there are connected to each other. In addition, the stages F1 / R1, F2 / R2 is in this parallel circuit, a particularly

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high-ohmic emitter follower resistor RO connected, to which the load resistances R1, R2 are compared the resistance values have a significantly lower IVi the resistance values are known per se achievable, e.g. by choosing the respective length / width ratio of the two-pole channel areas FETs operated as resistors. The emitter follower resistor RO allows that from the DC power source VDD / YSS supplied total current i1 + 12 of the stages against fluctuations in the direct current supply to stabilize, so that the differential voltage RS and thus also U3 / J3 correspondingly independent of the respective The magnitude of the voltage is VDD / VSS.

In all of these charge reversals, a partial discharge corresponds to a previously positively charged storage gate an IG-FET F1, F2 negative charge. Likewise, a partial discharge corresponds to a previously negative one charged storage gate of a positive charge.

Because the various adjustment measures, i.e. reloading measures, can basically also be carried out one after the other on the same IG-FET, all adjustments are reversible, i.e. if the adjustment measure is mistakenly too strong, it can later be revised as required by erroneously adding Highly or too weakly or with the wrong polarity charged storage gate can later be reloaded again as desired can to improve the matching.

Because the IG-FET F1 and / or F2 in question has a memory gate in FIG. 2, its characteristic does not depend only from the originally existing channel area type (enrichment type, depletion type, blocking type), but rather also from the subsequent charging of the storage gate:

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If the storage gate is uncharged, then the following applies in principle continue to have the original characteristic as if no memory gate were present, depending on whether the channel area of the depletion type, enrichment type or lock type is.

If, on the other hand, its storage gate was subsequently charged, then it has, for example, an enrichment type channel area, even though it is has, no longer the. original characteristic, but a shifted characteristic, as if he would have a correspondingly different channel area.

Is namely the memory gate with majority charge carriers the source or the drain charged, i.e. with holes in the p-channel or with electrons in the n-channel, then there is such a first shift in the characteristic curve simply because of this storage gate charging instead of having a lock-type channel area, even though it has an enhancement-type channel area Has. In order to control the IG-FET in its conductive state, this must be done first in the channel area K repulsive effect of the charging of the storage gate, by means of the control gate, must be compensated before a channel can form between the source and the drain.

If, on the other hand, the memory gate is charged with minority charge carriers of the source or the drain, that is to say with Electrons in the p-channel or with holes in the n-channel, then take place simply because of this storage gate charge an opposite shift in the characteristic curve takes place, as if it were now a depletion-type channel area even though it has an enhancement type channel range. To control the IG-FET in its conductive state is namely the effect of this charge which enriches the majority charge carriers in the channel region K

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not even to generate by means of the control gate in order to create a conductive channel between the source and the Get drain.

However, if the IG-FET has a channel region doping which in itself corresponds to a depletion type, then it can you also get the first one by subsequently charging your storage gate with the majority charge carriers Achieve shifting of the characteristic as if the IG-FET was now e.g. an enrichment type or blocking type channel area would have; or by subsequent charging with the minority charge carriers also the opposite Achieve a shift in the characteristic as if it were an even more heavily doped depletion-type channel region would have.

However, if the IG-FET originally had a channel region doping that already corresponds to a blocking type in itself, then one can do the first one again through the subsequent charging with the majority charge carriers Shift, through subsequent charging with the minority charge carriers again the opposite Achieve a shift in the characteristic.

By subsequently charging the storage gate with the corresponding charges, a shift can be made of the characteristic curve to the left and right, depending on the strength of the charge the shift is strong or weak.

Fig. 2 shows an example for the stepless charging, or for the corresponding effect of the balancing measures on the characteristic curve or on the threshold value UE at which a noticeable source-drain current begins to flow.

This is an n-channel IG-FET with β / um

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long channel area, the storage gate of which discharged vcm during different durations t, in each case Starting state, by means of the canal injection is charged negatively. The source-drain voltages VDS applied during the adjustment are 15V, 17.5V, 20V and 22.5V. The control gate-source voltage is 25V during the adjustment. The curves show that the threshold voltage UE, depending in particular on the duration t, increases as a result of the adjustment, where yes and no Limit value of approx. 13 to 14V can be seen, in particular from the control gate-source voltage used depends and is largely achieved with long periods of several minutes. A slight general increase of the threshold voltage curve UE by the order of magnitude A tenth of a volt can still be seen between t = 10 see and t = 100 see, so that the limit value is actually is only reached completely after hours and days.

In the state close to the limit value which can be seen in Fig. 2, e.g. after 1 see, the memory gate is then located at a potential of approx. -10V with VDS = OV and with source potential at the control gate. This memory gate potential results from the threshold voltage shift from the control gate-source voltage of 25V of approx. 12V and the capacitive voltage division between control gate, memory gate, source, Channel area and drain taken into account.

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This IG-FET is also dependent on the channel region length with a control gate-source voltage From 25V a threshold voltage increase of e.g. 5 to 10V is possible in 100 msec. For an afterthought The adjustment carried out on the module, however, often only requires threshold voltage changes of e.g. 20 mV. Are control gate voltage iia-

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pulse of e.g. only 12V is used, whereby the storage gate is at a potential of about + 10V in the uncharged state due to the capacitive voltage division, when using pulse durations of 1 mseCy threshold voltage shifts often well below 1 mV per pulse. With pulse durations well below 1 msec, even lower threshold voltage shifts are obtained if required, even if the storage gate potential has meanwhile been somewhat charged /

Also because the peak value of the control gate voltage pulses increases from pulse to pulse by e.g. 10 mV is, a threshold voltage shift can be carried out with sufficient accuracy in a short time.

Charging is terminated when the required reference voltage of, for example, U3 = OV or U3 = XV is measured at the output of the differential amplifier, for example grounded inputs U1, OZ _{1 for use as a reference source.} This measurement can be carried out between the individual control gate voltage pulses.

The strength of the charge can thus be selected almost arbitrarily by a corresponding ΐ / ahl of the amplitudes and / or durations of the balancing measures used for charging - see the known use of such an IG-FET as an analog signal store. Therefore, the characteristic can be any waiting, not just by a fixed We, rt, moved, and the differential voltage RS can be arbitrarily set by polarity and Betrtuj. Since some of the calibration measures shift the characteristic curves in a positive direction and others in a negative direction, the memory gate can be almost infinitely variable

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arbitrarily, also reversibly several times alternately in positive and negative direction, and can be charged at will and partially or fully discharged again - especially with the help of the above, all known reloading measures for IG-FETs with memory gate, the adjustment measures here or represent adjustment voltages. One has when needed for adjustment only temporarily apply the voltages required for recharging to the electrodes of the IG-FET, until the desired adjustment is finally achieved.

The adjustment voltages can be transferred to the respective IG-FET, eg F1, eg during the wafer test or during the test of the finished chip _? by means of tips via aluminum patches provided for this purpose, ie via specially attached connections on the chip. In particular, in order not to permanently impair other components attached to the integrated module, all or some of the electrodes of the IG-FET containing the memory gate G1 can be connected directly to the aluminum patches, via which the adjustment voltages can be fed directly to this IG-FET, cf. the aluminum patches A1 / A2 / A3 for F1 and A5 / A2 / AA · for F2 in Fig. 2. It is also possible to provide corresponding housing connections that enable adjustment even after installation in the housing.

It is also possible to carry out a preliminary, rough, i.e. imprecise adjustment on the disk or on the Chip and the final fine adjustment after installation in the housing, e.g. with the help of UV light irradiation through a quartz window. If a UV laser is used here, the adjustment can be carried out in a few msec, see e.g. IEEE Trans.

on ED, Volume ED-24 (1977) Ho. 2, p. 159.

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Often it is sufficient, depending on the sign of the one to be compared Error in differential voltage, only reloading one IG-FET F1 or the other FG-FET F2.

The IG-FETs with memory gates can be implemented e.g. with the well-known double silicon N-channel technology, see e.g. DE-OS 24 45 030.

For a large reinforcement of the steps, a large width / length ratio of the channel area is often of e.g. 35, cheap, which is also possible with IG-FETs with memory gate, see also ISEE-J. of Sol. St. Circ, SC-11 (Dec 1976) 748-753.

The differential voltage RS arises from the mismatch between the two stages F1 / R1, F2 / R2 in particular because of the different geometries, dopings and charges of the IG-FETs F1, F2, which are also used for IL = Ü2 cause different currents i1 and i2.

To make RS = 0, for example, U1 + AU = U2 could be applied to input U2. In the invention, instead of applying AU + U1 = U2, when U1 = U2, at least one of the storage gates can be charged accordingly in order to make RS = 0 /. A more specific adjustment is useful, for example, when the differential amplifier DV supplies reference values U3 or J5, which are obtained at RS = 0 due to the dimensioning of all components. In this case, both stages are dimensioned the same as possible.

Because of the relatively small duct dimensions, in particular with respect to the channel length, the light correspondence of the steps that is then initially obtained becomes above all by the photolithographic fluctuations, i.e. Tolerances, the structure widths or the other geometric Dimensions, as well as the doping intensities

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works. The fluctuations in particular in the oxide thickness, the interface charges and thus also the threshold voltage are lower if the two levels R1 / F1, R2 / F2 are placed close together on the module are. The charge reversals of the memory gate required for the adjustment are correspondingly low.

With carefully applied insulation, the long-term storage behavior is the IG-FETs with memory gate are good. Because of the often very low charges that are necessary for adjustment, the field strengths in the IG-FETs of both stages are similar to one another. Therefore a later, undesired charge reversal during later operation of the reference source is generally no longer possible - expect as long as the source-drain voltages or control gate-source voltages in operation of the reference source at least approx. 5V below the values at which charging or discharging of the storage gate would noticeably set in after 1 minute, see Fig. 3.

The same applies if a differential voltage RS is to be set which deviates significantly from zero. A certain still inadequate adjustment is obtained, for example, if the width / length ratio of the channel areas of the IG-FETs of both stages is selected to be different, so that only a fine adjustment by charging at least one of the storage gates is necessary. The tolerances of the threshold voltages of the IG-FETs almost always require a certain adjustment if only a small tolerance ds3 reference voltage or reference current is permitted. V / ecen of the different voltage dependencies and, because of the different temperature dependencies of Yararmun type and enrichment type FETc * / & re, the achievable tolerance of the reference voltage or the reference voltage or the reference voltage or the reference voltage or the reference voltage, respectively, often much to ~ ro3, if one considers the known reference ^ uelly from Fi ;;. I.

BATH ORIGINAL

would use. Here, however, the invention can permit smaller tolerances.

In the invention, cf. en. In Fig. 2, all FETs are implemented as depletion type FETs. However, the FETs can also be designed, for example, as an enrichment FET or a blocking type FET. CMOS technology is also possible in that the load resistors R1, R2 have an oppositely doped channel region compared to the IG-FETs F1, F2. The constancy of the reference variables is significantly improved compared to the reference source in FIG. 1, since, if necessary, the two IG-FETs F1, F2 of the stages, with the exception of the different charges of the memory gate, can have almost the same properties as one another. Based on FIG. 4, an example is intended to show that, despite the same geometries and the same doping of both stages, a differential voltage RS strongly deviating from 0 can be achieved even without charging, so that only a fine adjustment by recharging is subsequently necessary.

FIG. 4 shows details of a variant of the example shown in FIG. 2, which is used in particular as a reference voltage source is usable. A voltage divider R31 / R32 is attached to the output of the differential amplifier DV, in order to feed a bias voltage U2 to the control gate of one of the IG-FETs, see F2 in FIG the bias voltage U1, e.g. earth, of the control gate of the other IG-FET F1 is very different. In this way In this example, the reference voltage U3 supplied by the differential amplifier DV can be comparatively much

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may be large, can also be used to generate the bias voltage U2. The supply line is different from one another Bias voltages U1, U2 to these control gates, i.e. a corresponding dimensioning of the Voltage divider R31 / R32, thus allows the desired to achieve subsequent adjustment of the stages with particularly low reloading of the storage gates, if RS or U3 is very large.

However, if U2 = U1 it is also possible to achieve a subsequent adjustment for very large RS or U3 without attaching the voltage divider R31 / R32 shown in FIG. 4 and without setting up the stages F1 / R1, F2 / R2 differently from one another . You can also achieve very high positive or negative charges of the memory gate during calibration by means of correspondingly large and correspondingly long-lasting calibration measures, e.g. charging to + 10V, whereby the threshold voltage or the differential voltage RS can still be set very precisely, e.g. to 1 mV is. This variant is particularly recommended if the final value to be set for the reference variable is not yet known when the module is manufactured and if the charging of the storage gate, once set, does not necessarily last for a very long time, e.g. over many years, with the same accuracy the storage gate should remain. The lower the charge, the longer the time in which the charge remains on the storage gate with the set accuracy.

The accuracy of the setting of the charge is particularly great if the IG-FET with memory gate F1 is a another IG-FET is connected in parallel in the same stage. Charging the IG-FET with memory gate F1 then has little influence on the resulting welding voltage of this parallel connection, especially if

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F1 has a relatively small width / length ratio of its channel area compared to the one connected in parallel IG-FET has. Correspondingly accurate, e.g. to 0.1 mV, one can easily determine the resulting threshold voltage the parallel connection during the adjustment.

In the variant described last, both IG-FETs of the parallel connection have their own memory gate on, with a separate control option for the control gates of both IG-FETs, e.g. through own aluminum patches and e.g. a switch in the connection between the two control gates both IG-FETs, is attached, then you can adjust both IG-FETs separately from each other. Hence one can the resulting characteristic curve of the parallel connection of these two IG-FETs into positive and negative as desired Move direction. In this further development, one can also determine the ratio of the channel length to the channel width the first of these two IG-FETs is comparatively small during manufacture and the second of these two Choose IG-FETs that are comparatively large. With this special variant, the first IG-FET can first be roughly adjust so that the resulting characteristic of the parallel connection approximates the desired course.

Then you can quickly and easily carry out a precise fine adjustment by adjusting the second IG-FET Achieve, since its adjustment only has a small influence even with a relatively strong charge reversal of its storage gate has on the resulting characteristic curve of the parallel connection.

For a PCM encoder and decoder with an R-2R network, a reference current source is often required, in particular can be operated with a load resistor RL lying on one side at ground potential. Fig. 6 shows

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an example constructed according to the invention, based on the reference power source example shown in FIG was developed. For this purpose, an output of the differential amplifier DV is provided with a first voltage divider KR / KR connected, whose tap with the control gate at least one of the IG-FETs, here F1, the first of the both stages F1 / R1 is connected. The same output of the differential amplifier DV is connected to a second voltage divider ccR / RL connected, the first divider element ocR directly to the output of the differential amplifier DV is connected and the other divider element RL the load resistor RL to be supplied with the reference current 13 represents, the tap of the second voltage divider connected to 'a third voltage divider (i-cc) * R / R whose tap in turn with the control gate of at least one of the IG-FETs, here F2, of the second stage F2 / R2 is connected.

Fig. 5 shows the circuit of a reference current source, which is called "Howland Current Source "is known, see Roberge, Operational Amplifier 1975, pages 452-455. The current 13 through the load resistance RL is with the dimensioning selected there

13 = Ui. -1 .

ccR

The power source property with infinite output Internal resistance requires e.g. the in

., Q Fig. 6 entered resistance ratios, where the Factors K and α can be arbitrary per se. Adequate compliance with such dimensions relatively little is required in the manufacture of the reference current source as part of an integrated module Trouble. The absolute value of the resistance R, which also determines 13, is when it is used as a polysilicon track or

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- VPA 78 ρ 6 2 ^ 5 BRD

is designed as a diffusion path, relatively constant. But it still shows the manufacturing-related fluctuations or tolerances. Therefore, the reference current 13 should still be accurate above the reference voltage Ui adjusted, i.e. adjusted. For this purpose, e.g.

the structure according to the invention according to FIG. 6 can be selected. Instead of the reference voltage Ui, in the invention for setting the reference current 13, the adjustable Stage F1 / R1 or F2 / R2 used, their differential voltage RS in the manner described above Subsequent need on the manufactured one. Block can be precisely matched. The adjustment of the reference current 13 can in particular by a suitable number of adjustment voltage pulses that the threshold voltage shift cause to be carried out. Even a reference current source with reverse current direction -13 can be carried out in particular by changing the sign of RS or of the threshold voltage shift. In this case, for example, the other IG-FET F2 can be charged instead of the IG-FET F1.

A reference source constructed in accordance with the invention can provide the constant reference variable without interruption during operation deliver that has been discontinued. However, this reference source can also be formed in such a way that it uses alternating signals is controllable and then a set reference voltage U3 or reference current 13 only temporarily, e.g. during the absence of controlling alternating signals. For example, at least one of the IG-FETs and / or at least one of the associated resistors, e.g. R1, RO, of the two stages with be connected to a control input U1, U2 for superimposing an alternating control signal. If the control input a binary alternating signal is fed in, the reference variable U3 / J3 is switched on and off.

If an analog animal signal is sent to the control input

030016/0163

conducts, the reference variable is modulated accordingly. In this case, the reference source serves as a subsequently adjustable source of modulatable Constant currents or constant voltages.

9 claims
6 figures

030016/0163

Claims (9)

Claims S. f 1. JReference source on an integrated FET module, whereby - two separate stages fed by the same DC power supply, each the series connection contain at least one IG-FET and at least one working resistor, - one tap between one of the IG-FETs and one of the load resistors is attached in each step, and - a differential voltage between the taps of the stages defined value occurs, the directly itself as a reference voltage, or the indirectly for setting the value of a reference voltage or a Reference current is used, e.g. by means of a voltage divider, especially for sources of reference currents or of reference voltages in A / D converters and D / A converters ζ 3. of a PCM telephone exchange system, characterized in that - in at least one of the two stages (F1 / R1, F2 / R2) at least one of the IG-FETs (F1) at least partially mounted between the controllable control gate and the channel area, with an insulator on all sides contains surrounded and therefore electrically floating memory gate (Fig. 2). 2. Reference source according to claim 1, characterized in that - the parallel connection of the two stages is in series with a high-resistance emitter follower resistor (RO) (Fig. 2). 30016/0183 3. Reference source according to claim 1 or 2, characterized in that - the electrodes of the IG-FET containing the memory gate with their own connections (A, A2, A3), e.g. with Aluminum patches, connected to the integrated module, after the IG-FET is manufactured, at least prior to the encapsulation of the module, are accessible (Fig. 2). 4. Reference source according to one of the preceding claims, characterized in that that - each of the two inputs of a differential amplifier (DV) each with the tap of a stage (F1 / R1, F2 / R2) is connected (Fig. 2). 5. Reference source according to claim 4, characterized in that - An output of the differential amplifier is connected to a first 'voltage divider (R31 / R32) whose tap is connected to the control gate of one of the IG-FETs (F2) of the first of the two stages (F2 / R2). 6. Reference source according to claim 4, characterized in that - An output of the differential amplifier (DV) is connected to a first voltage divider (K.R / K.R) whose Tap connected to the control gate of at least one of the IG-FETs (F1) of the first of the two stages (F1 / R1) is, - the same output of the differential amplifier (DV) is connected to a second voltage divider (ctR / RL), whose first divider (aR) is directly connected to the output of the differential amplifier (DV) and its Another divider element (RL) shows the load resistance (RL) to be supplied with the reference current (13). Q30016 / 0163 represents, -and - The tap of the second voltage divider with a third voltage divider ((1-cc) R / R) is connected, whose tap in turn with the control gate at least . at least one of the IG-FETs (F2) of the second stage (F2 / R2) connected is. 7. Reference source according to one of the preceding claims, characterized in that - at least one of the IG-FETs (F1) and / or at least one of the associated resistors (R1, RO) of the two stages with a control input (U1, U2) for Superimposition of a controlling alternating signal (U1 in Fig. 2 and 6) is connected. 8. A method for operating a reference source according to claim 7, characterized in that that - A binary animal signal (U1) is fed to the control input will. 9. A method for operating a reference source according to claim 7, characterized in that - an analog alternating signal (U1) is fed to the control input. 030016/0163