DE2838468A1 - Digital control for thyristor static inverter - regulates machine speed using first inputs of two AND=gates in changeover with connected to clock counter output - Google Patents

Abstract

The digital control has a decoder connected by its inputs to a clock counter and an up/down counter, a control unit and AND-gates. A change-over circuit comprising seven AND-gates, a NOR-gate and a delay line is also included. The first inputs of the first two AND-gates in the change-over unit are connected to the output of the clock counter. The output of the first AND-gate is connected to the gate of one main thyristor and one charging thyristor in the inverter. The second AND-gate's output is connected to one shut-off thyristor.

Description

description

The invention relates to control devices for a gas discharge, Electronic or semiconductor devices with a static built-up control electrode Converter and relates in particular to a device for digital control a thyristor pulse DC converter.

The present invention can be used in electrical train and industrial applications DC drive for regulating the rotational speed of electrical machines and for voltage regulation at an inductive active load.

It is a device for the digital control of a thyristor pulse-DC converter known, in which the outputs of a clock counter are connected to the input of a decipherer, at its input the output of a control generator and the outputs of a reversing counter are connected, its summation and subtraction input to the respective Outputs of a control unit are connected.

The separate output of the latter is with the control inputs for the initial state of the reversing counter and the control generator connected while the outputs of the decipherer and the separate outputs of the clock counter a switching unit containing AND circuits and a sign flip-flop electrically are coupled to the control electrodes of the thyristors of the converter The decipherer is provided with two outputs, which are electrically connected to the control electrodes of two Reloading and two main thyristors of the converter connected and for supplying the energy of pulse sequences shifted by 1800 each in time and on the output side are provided. The cycle counter has two outputs, the electrical one coupled with the expensive electrodes of two commutation thyristors of the converter and for feeding in temporally undisplaced, but against each other on the output side are determined by 1800 shifted pulses.

In this known device are in the first control stage the consequences of the time-shifted pulses from the decoder outputs via the switching unit to the control electrodes of the two charge reversal thyristors given of the converter, while in the second control stage these consequences on the control electrodes of the two main thyristors of the converter.

To control a two-stage thyristor-pulse-equal current transformer but, according to one described in the USSR copyright certificate No. 417880, class H02m 3/1 + Circuit is executed, are in the first control stage three and in the second Control stage to deliver two pulse trains.

Said known device does not ensure control of such a device two-stage thyristor pulse direct current converter, which operates in different control stages the feeding of various pulse trains to the control electrodes of its thyristors The invention is based on the object of a device for digital control of a Uhyristor pulse DC converter to create by creating a new circuit solution for the switching unit in the first control stage the feeding of three pulse trains to the control electrodes of the thyristors of the two-stage thyristor pulse direct current converter and in the second control stage is guaranteed by two pulse trains.

This is achieved in that in a device for digital control a thyristor pulse DC converter to the inputs of a deciphering device Outputs of a clock counter with the output of a control generator at its input and the outputs of a reversing counter are connected, its summation and Subtraction input connected to the respective outputs of a control unit are whose separate output with the control inputs for the initial state of the Reversing counter and the control generator connected while the output of the decipherer and the separate output of the clock counter via a AND circuits and a sign flip-flop containing switching unit electrically are coupled to the control electrodes of the thyristors of the converter, according to the Invention, the switching unit seven AND circuits, a NICHU circuit and contains a delay circuit, wherein the first inputs of the first and the second AND circuit connected to the separate output of the clock counter Output of the first AND circuit to the control electrodes of a main and a Charge thyristor of the converter and the output of the second AND circuit to the -Control electrode eirns quenching thyristor of the converter is connected, with which also the output of the third AND circuit is connected to the first inputs of the third and fourth AND circuit of the separate output Bur control pulses of the Dechiffrators - - and the output of the fourth AND circuit to the control electrode connected to an auxiliary thyristor of the converter and electrically via the delay circuit is connected to the control electrode of the charge-reversal thyristor of the converter to the first input of the fifth AND circuit is the subtraction output of the control unit, the summation output to the first inputs of the sixth and seventh AND circuits connected to the control unit, the first output for pulses for switching the Control stages of the deciphering device to the second input of the seventh AND circuit connected and electrically via the NOT circuit with the wide input the sixth AND circuit is connected, while the second output of the fifth AND circuit with the second output for impulses to switch between the control levels of the decoder is connected to the first separate input d's sign flip-flops the outputs of the fifth and sixth AND circuit to the second separate input of the directory flip-flop, the output of the seventh UTND circuit, the first separate one Output of the sign flip-flop to the second inputs of the second and fourth AND circuit connected and the second separate output of the sign flip-flop is connected to the second inputs of the first and the third AND circuit.

The inventive device ensures digital control of the two-stage thyristor pulse direct current converter, which is in the first control stage the feeding of three pulse trains to the control electrodes of its thyristors and in the second control stage requires two pulse trains.

The invention is based on the embodiment shown in the drawing Explained in more detail, FIG. 1 shows the block diagram of a present invention Device for digital control of a thyristor pulse-DC converter and that Schematic diagram of a controlled two-stage thyristor pulse-DC converter; Fig. 2 timing diagrams a), b2, c), d), e), f) for signals in different Points of the circuit of the device, stage in the first rule and Fig. 3 timing diagrams a), b), c), d), e), f) for signals in different points of the circuit of the device, In the second control stage the device for the digital control of a thyristor pulse direct current converter contains a control generator 1 (Fig. 1) in the form of a multivibrator, the outputs of which to the input of a binary counter with a continuous carry of sine executed clock counter 2 is connected, in which the number of outputs is the same that is twice the number of its flip-flop.

The device contains a deciphering device 3, one of which is input are connected to the outputs of the clock counter 2, a binary reversing counter 4, the outputs of which are connected to the other inputs of the decoder 3, and a control unit 5 including pulse generators and feedback generators.

The decipherer 3 is in the form of a known decryption matrix and has a separate output 6 for time-shifted sequences of control pulses offset from one another by a quarter of the pulse train period, a first separate output 7 for pulses for switching the control stages and a second separate output 8 for pulses to switch the control stages.

The clock counter 2 has a separate output 9 for Control impulses on.

The separate output 10 of the control unit 5 is connected to the control unit For the initial state of the control generator 1 and the reversing counter 4, the summation output 11 of the control unit 5 is connected to the summation input of the reversing counter 4 and the subtraction output 12 of the control unit 5 to the subtraction input of the Reversing counter 4 connected.

The device for the digital control of a thyristor-pulse-direct current converter contains according to the invention seven AND circuits 14, 15, 16, 17, 18, 19 and 20, a NOT circuit 21, a sign flip-flop 22 and a delay circuit Switching unit 13 having 23.

The controlled two-stage nhyristor pulse direct current converter 24 includes a main thyristor 25, a quenching thyristor 26, a charge reversal thyristor 27 and an auxiliary thyristor 28 * In addition, the landler 24 has one of a Series connection of a commutation capacitor 29 and a commutation choke 30 composite commutation circuit.

In the .Stromkreis of the main thyristor 25 is one of a series circuit of an armature 31 and a winding 32 shunted by a diode 33, existing Load switched.

To the first inputs of the first 14 and the second AND circuit 15, the separate output 9 of the clock counter 2 is connected, the output of the first AND circuit 14 is connected to the control electrodes of the main thyristor 25 and the Charge thyristor 27 of the converter 24 coupled, while the output of the second AND circuit 15 is connected to the control electrode of the erase thyristor 26 of the converter 24 to which the output of the third Ui4t circuit 16 is also connected.

To the first inputs of the third 16 and the fourth AND circuit 17, the separate output 6 of the deciphering device 3 is connected, while the output the fourth AND circuit 17 to the control electrode of the auxiliary thyristor 28 of the Converter 24 @ and electrically via the delay circuit 23 to the control electrode of the charge reversal thyristor 27 of the converter 24 is connected to the first input of the fifth AND circuit 18 is the subtraction output 12 of the control unit 5 and to the first inputs of the sixth 19 and the seventh AND circuit 20 of the Summation output 11 of the control unit 5 is connected.

The first output 7 for pulses to switch the control levels of the deciphering device 3 is connected to the second input of the seventh AND circuit 20 and electrically via the NOT circuit 21 to the second input of the sixth AND circuit 19 connected, while the second output 8 for pulses for switching the control stages of the deciphering device 3 with the second input of the fifth AND circuit 18 is connected.

At the first separate input of the signed flip-flop 22nd are the outputs of the fifth 18 and the sixth AND circuit 19 and to the second separate input of the sign flip-flop 22, the output of the seventh AND circuit 20 connected.

The first separate output of the sign flip-flop 22 is to the second inputs of the second 15 and fourth AND circuit 17 connected, while the second separate output of the sign flip-flop 22 with the second Inputs of the first 14 and the third AND circuit 16 is connected.

Fig. 2 shows the timing diagrams for signals at various points the circuit in the first control stage, where a) pulses 34 of the voltage U26, which on the control electrode of the thyristor 26 (Fig 1) are given, b) pulses 35 (Fig. 2) of the voltage U28, which is applied to the control electrode of the auxiliary thyristor 28 (Fig. 1) are given, c) voltage pulses 36 (Fig. 2) that the control electrode of the charge reversal thyristor 27 (Fig. 1) are supplied, d) voltage U29 Fig 2) on Commutation capacitor 29 (Fig. 1), e) Voltage U (Fig. 2) at the load, f) Current i are in the load.

In Fig. 3, there are timing charts for signals at various points the circuit shown in the second control level, where a) Pulses 77 of the voltage U2, which are applied to the control electrode of the main thyristor 25 (Fig. 1) are supplied, b) pulses 38 (Fig. 3) of the voltage U26, which are applied to the Control electrode of the quenching thyristor 26 (Fig. 1) are given, c) pulses 37 (Fig. 3) the voltage U27 'which is applied to the control electrode of the charge reversal thyristor 27 (Fig. 1) are supplied, d) voltage U29 (Fig. 3) at the Eom7nutierungskondensator 29 (Fig. 1), e) voltage U (Fig. 3) at the load, f) current i in the load.

The device for the digital control of the ghyristor pulse direct current converter operates according to the invention as follows.

Originally, the output 10 (Fig. 1) of the control unit 5 is a Potential signal supplied, which blocks the control generator 1 and the flip-flops of the Brings reversing counter 4 to the INITIAL STATE when the first pulse arrives from the summation output 11 of the control unit 5 at the summation input of the reversing counter 4 his flip-flops set themselves in the first state.

At the same time as the first pulse is fed in, the potential signal removed from output 10, what for Use of the control generator 1 leads from its output at the input of the clock counter 2 clock pulses with a repetition frequency f = f0. 2n begin to run in, where f0 is the operating frequency of the thyristors 25, 26, 27 and 28 of the converter 24, n the number of flip-flops in the clock counter 2 and reversing counter 4 denote.

Here, a pulse train begins from the separate output 9 of the clock counter 2 enter with a pulse repetition frequency f0.

The thyristors 26, 27 are controlled in the first control stage and 28 of the two-stage converter 24 is required, with the main thyristor 25 not involved in the work A signal occurs at output 7 of decipherer 3 only after finishing the scheme in the first stage, while it is in the beginning the regulation does not take place.

If there is no signal at the input of the device 21 appears at the output the latter a signal that arrives at the input of the AND circuit 19, on the other input pulses from the summation output 11 of the control unit 5 are given, which causes a signal at the output of the AND circuit 19.

If this signal is at the first separate input of the Signed flip-flops 22 arrives, it changes the latter into a state in which a signal is received at first separate output of the sign flip-flop 22 occurs, it being sent to the second inputs of the AND circuits 15 and 17 arrives, At. . Coincidence of one from the output 9 of the clock counter 2 incoming pulse with a signal that on the second input of the AND circuit is given, starts from the output of the latter a pulse train 34 at the control electrode of the quenching thyristor 26 of the converter 24 (Fig. 2, diagram a)) to run in with a repetition frequency f0.

From the separate output 6 (Fig. 1) of the deciphering device 3 comes a sequence of pulses given by the output 9 of the clock counter 2 by a time interval of shifted control pulses, where T is the switching time of the thyristors 25, 26, 27 and 28 of the converter 24.

When a pulse arrives from the output 6 of the decipherer 3 on first input of the AND circuit 17, at the second input of which a signal from the first Output of the sign flip-flop 22 is present, occurs at the output of the AND circuit 17-a pulse 35 (Fig. 2, diagram b)) which is applied to the control electrode of the auxiliary thyristor 28 (Fig. 1) is given.

At the same time, this impulse is applied to the entrance of the delayed stance 23 delivered, of their output after Expiration of one of the sum of the Release time of the thyristor 28 and the charge time of the capacitor 29 to the reverse Polarity of the same time interval a pulse 36 (Fig. 2, diagram c)) on the control electrode of the charge reversal thyristor 27 (FIG. 1).

When the next pulse arrives from the summation output 11 of the Control unit 5 at the Sumuiationseingang the reversing counter 4 is the time interval to the shift of the; Output 6 of the decipherer 3 coming pulses against the pulses supplied by the output 9 of the clock counter 2 increase.

When each pulse arrives at the summation input of the reversing counter 4 thus becomes the time interval between that at the control electrode of the erase thyristor 26 (Fig. 1) fed in pulse 34 (Fig. 2, diagram a)) and that at the control electrode of the auxiliary thyristor 28 (Fig. 1) of the converter 24 incoming pulse 35 (Fig. 2, Diagram b)).

The time interval between the arrival of pulse 35 and that of the Pulse 36 (Fig. 2, diagram b) and c)) at the control electrodes of the auxiliary thyristor 28 (Pig. 1) or.

of the charge reversal thyristor 27 is here in the course of the entire control process remain unchanged in the first stage.

When the quenching thyristor 26 is triggered, the load is a Voltage U (Fig. 2, diagram e)) of the capacitor 29 (Fig. 1) and the supply source, and a current i begins via the load (Fig. 2, diagram f)) to flow.

The commutation capacitor 29 (FIG. 1) starts here the reverse polarity over the load circuit (Fig. 2, diagram d)) to reload.

When the impulse -35 (Fig. 2, diagram b)) arrives at the control electrode of the auxiliary thyristor 28 (Fig. 1) the load circuit is shunted, and the other Charging of the capacitor 29 takes place via the auxiliary thyristor 28, whereby the current i (Fig. 2, diagram f)) in the load on the diode circuit thanks to the during the pulse period of the voltage U applied to the load (Fig. 2, diagram e)) stored electron'agnetic energy continues to flow.

When the pulse 36 Fig. 2, diagram c)) arrives at the control electrode of the charge reversal thyristor 27 (FIG. 1), the latter ignites, and a charge reversal takes place of the commutation capacitor 29 via one of the capacitor 29, the charge reversal thyristor 27 and the throttle 30 put together resonant circuit.

With an increase in the time interval between that on the control electrode of the quenching thyristor 26 (Fig. 1) given pulse 34 (Fig. 2, diagram a)) and the Pulse 35 arriving at the control electrode of auxiliary thyristor 28 (Fig. 1) (Fig. 2, diagram b)) there is an enlargement of the Pulse duration of the the load applied voltage U (Fig. 2, diagram e)), resulting in enlargement the rotational speed of the bunker 31 (Fig. 1) leads.

The maximum pulse duration of the load in the first control stage applied voltage U (Fig. 2, diagram e)) is equal to the time of a complete Reloading of the commutation capacitor 29 (FIG. 1) by the load current via the quenching thyristor 26th

After completion of the first control stage, the appears at output 7 Dechiffrator 3 a signal that a disappearance of the signal at the output of the NOT circuit 21 and causes the signal to appear at the input of AND circuit 20.

When the next pulse arrives from the summation output 11 of the Control unit 5 at the other input of AND circuit 20 appears at its output a signal that arrives at the second separate input of the sign flip-flop 22 and the latter is transferred to the other stable state at which a signal is on second separate output of the sign flip-flop 22 occurs, it being on the second inputs of the AND circuits 14 and 15 arrives.

When a pulse coming from output 9 of clock counter 2 coincides with a signal fed in at the second input of the U circuit 14 begins from Output of the latter at the control electrode of the main thyristor 25 of the converter 24 a pulse train 37 (Fig. 3, diagram a)) with a repetition rate to run in fo. At the same time, these pulses 37 (Fig. 3, diagram c)) on the Control electrode of the charge reversal thyristor 27 (Fig. 1) supplied.

From the separate output 6 of the decipherer 3 comes the sequence of control pulses shifted against the pulses given by the output 9 of the clock counter 2 to the first input of the AND circuit 16. Furthermore, these pulses 38 (Fig. 3, diagram b)) supplied to the control electrode of the quenching thyristor 26 (Fig. 1), After the arrival of each pulse at the summation input of the reversing counter 4 becomes the time interval between that on the control electrodes of the main thyristor 25 (Fig. 1) and the charge reversal thyristor 27 supplied pulse 37 (Fig. 3, diagram a) and c)) and the one arriving at the control electrode of the quenching thyristor 26 (FIG. 1) Pulse 38 (Fig. 3, diagram b)) increase. To reduce this time interval 4 pulses from the subtraction output are sent to the subtraction input of the reversing counter 12 given to the control unit 5.

When the pulse 37 (Fig. 3, diagram a)) is fed to the Control electrode of the main thyristor 25 (Fig. 1) ignites the latter, and to the A voltage U (Fig. 3, diagram e)) of the supply source is applied to the load. At the same time, the charge reversal thyristor 27 (FIG. 1) via which the commutation capacitor opens 29 to reverse polarity (Fig.

3, diagram d)) is reloaded.

The current i (Fig. 3, diagram f)) in the load begins from the specified minimum value to increase to the specified maximum value at which The pulse 38 reaches the control electrode of the quenching thyristor 26 (FIG. 1) (Fig.

3 diagram b)) is given.

When the extinguishing thyristor 26 (FIG. 1) is opened, the main thyristor is connected 25 a voltage U29 (Fig. 3, diagram d)) of the commutation capacitor 29 (Fig. 1) is applied, and the main thyristor 25 blocks. In the load circuit flows in the Break the current i (Fig. 3, diagram f)) further, taking its circuit over the diode 33 (Fig. 1) finds.

When increasing the time interval between the on the control electrodes the main thyristor 25 (Fig. 1) and the charge reversal thyristor 27 given pulse 37 (Fig. 3; diagram a) and c)) and that at the control electrode of the erase thyristor 26 (Fig. 1) incoming pulse 38 (Fig. 3, diagram b)) takes the pulse duration the voltage U applied to the load (Fig. 3, diagram e)) to what a further Increase in the speed of rotation of the armature 31 (Fig. 1) caused.

In order to avoid the rotational speed of the latter, the said is made Time interval reduced.

After completion of the second control stage, the appears at output 8 Dechiffrators 3 a fed in at the input of the AND circuit 18 signal to aren Other input pulses from the subtraction output 12 of the control unit 5 arrive.

The next pulse from output 12 of the last-mentioned one extends to the output the AND circuit 18 and passed the sign flip-flop 22 in the other stable State above, in which a signal appears at its first separate output, where it arrives at the second inputs of the AND circuits 15 and 17.

In the following, the device implements a control process in the first stage, in which the main thyristor 25 is excluded from work will. The sequence of regulation is analogous to that described above, only that the time interval between the on the control electrode of the quenching thyristor 26 (Fig 1) given pulse 34 (Fig. 2, diagram a)) and that at the control electrode of the auxiliary thyristor 28 (Fig. 1) incoming pulse 35 (Fig. 2, diagram b)) after the arrival of each pulse at the subtraction input of the reversing counter 4 decrease will.

The inventive device thus allows the work of a two-stage thyristor pulse direct current converter to control the one in the first Control stage feeds three pulse sequences to the control electrodes of the thyristors 26, 27 and 28 and in the second control stage the feed to the control electrodes of thyristors 25, 26 and 27 of two pulse patterns.

L e r s e i t e

Claims (1)

Device for digital control of a thyristor pulse DC converter Claim device for digital control of a thyristor pulse DC converter, in the case of the outputs of a clock counter at the inputs of a deciphering device Input the output of a control generator is connected, and the outputs of a Reversing counter are connected, its summation and subtraction input are connected to the respective outputs of a control unit, their separate Output with the control inputs for the initial status of the reversing counter and the Control generator is connected, while the outputs of the decipherer and the separate Output of the clock counter containing an AND circuit and a sign flip-flop Switching unit electrically with the control electrodes of the thyristors of the converter are connected, that is, that the switching unit (13) seven AND circuits (14, 15, lor, 17, 18, 19 and 20), one NOT circuit (21) and a delay circuit (23), with the first inputs of the first (14) and the time AND circuit (15) of the separate Output (9) of the clock counter (2), the output of the first AND circuit (14) to the Control electrodes of a main thyristor (25) and a charge reversal thyristor (27) of the Converter (24) and the output of the second AND circuit (15) to the control electrode a quenching thyristor (26) of the converter (24) is connected, with which the Output of the third AND circuit (16) is connected to the first input of the third (16) and fourth AND circuit (17) the separate output (6) for control pulses of the decipherer (3) connected and the output of the fourth AND circuit 17) connected to the control electrode of a auxiliary thyristor (28) of the converter (24) electrically via the delay circuit (23) to the control electrode of the charge reversal thyristor (27) of the converter (24) is connected to the first input of the fifth AND circuit (18) the subtraction output (12) of the control unit (5) to the first inputs the sixth (19) and the seventh AND circuit (20) the dumnation output (11) connected to the control unit (5), the first output (7) for pulses for switching the control stages of the decipherer (3) with the second input of the seventh AND circuit (20) and electrically via the NOT circuit (21) to the second input of the sixth AND circuit (19) is connected, while the second output of the fifth AND circuit (18) with the second output (8) for pulses to switch between the control stages of the Decipherers (3) connected, being disconnected with the first input of the sign flip-flop (22) the outputs of the fifth (18> and the sixth AND circuit (19), with the separate input of the sign flip-flop (22) the output of the seventh AND circuit (20) the first separate output of the Sign flip-flops (22) with the second inputs of the second (15) and the fourth AND circuit (17) and the second separate output of the sign flip-flop (22) connected to the second inputs of the first (14) and the third AND circuit (16) is.