DE2827745C2 - Dynamic address translation arrangement - Google Patents

Description

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The invention relates to a dynamic address translation arrangement for a channel or a Adapter of a sub-assembly according to the preamble of claim 1.

In one example of dynamic channel address translation in a known data processing system, the process of capturing a page carried out beforehand in the case of an access from the channels to the main memory. To enable access to this pinned page from the channels, the Channel invalidation bit turned OFF and then the SIO command is used to execute the access from output to the channels. This page capturing process and the channel invalidation bit operation will become controlled by the operating system However, the following difficulties arise with this system: The organization to search for the page to be recorded must also have some input-output devices that must be connected to the channels before executing the channel programs, and the number of pages held grows, while a number of input-output devices are in Operation is set, so the real memory is running out.

In addition, the known data processing systems provide access protection for the main memory carried out in that the storage key in each physical page within the main memory and the channel key to be transferred to the channels while the SIO command is issued, be compared. In the case of a virtual storage system, access protection should of course be implemented in a unit of logical data. However this owns The system has the following disadvantage: The logical access protection data should be recorded for the physical access protection mechanism there is such an architectural illogic that the canal is the logical addresses for address protection and the physical keys for access protection must know, and the organization for the recording is also fed.

A data processing system with dynamic address translation for re-addressing programs and channel addressing on a logical basis is also known (DE-OS 23 60 303). Do each channel associated devices for storing address translation parameters and devices for combining the address translation parameters with the logical ones Addresses provided in a channel program with translation of the logical addresses into real addresses.

The object of the invention is to provide a dynamic address translation arrangement according to the To create the preamble of claim 1, in which a memory page to be processed by the channel or the adapter of the sub-arrangement does not have to be retained in the main memory when the operation of the channel or adapter of the subassembly is interrupted.

For the input-output device or sub-assembly that does not necessarily require holding the page, the invention has the advantage that a channel or subsystem connection unit which operates at high speed and less hardware without encountering the following troubles:

(1) Due to the processing for searching a page to be pinned, an organization is applied before the channel programs are executed,

(2) when a number of input-output devices are put into operation, the number of them increases captured pages and the real memory is running out.

In addition, the invention has the additional advantages that holding the page solely within the Area of the software can be executed, not only for the input-output device, which is not a Holding the page requires, but also for a

such a device which requires the page to be held because the channel invalidation bit in the page table entry part as currently used is unnecessary and the organization for the software processing responsible for the operation of the channel invalidation bit is needed, becomes superfluous.

The application of the invention to the channel or the sub-arrangement adapter of the data processing system in which the logical access protection data, <Ue refer to the page corresponding to an entry point, are provided for such an entry point of the address translation table, allows such a data processing system to be implemented the problem that the channel recognizes the logical address as an address, as in the prior art, does not occur, but it must recognize the physical key for access protection.

In addition, according to the invention, high-speed access is possible and the dynamic address translation becomes less hardware added, since it is not necessary to do one every time Access the address translation table when accessing main memory from the channel or sub-array adapter.

The invention is explained in more detail below with reference to the drawings.

Fig. 1 is a system diagram of an embodiment according to the present invention. In Fig. 1 1 denotes the main memory MM, 2-1 and 2-2 denote the central processing unit CPU, 3-1 and 3-2 denote channels, 4 denotes the adapter of the subassembly, 5-1 and 5-2 denote input-output control units IOC, 6 denotes an input input-output device IO, and 7 denotes a sub-arrangement.

The channels 3-1,3-2 and the adapter of the subassembly 4, as shown in Fig. 1, have the Main memory 1 together with the central processor units 2-1 and 2-2, they also have the dynamic address translation arrangement.

Fig. 2 shows the function of dynamic address translation assigned part of the embodiment, this part is between the main memory 1, the central processor unit 2 and the Channel 3.

In FIG. 2, 1 denotes the main memory MM, 2 denotes the central processor unit CPU, 3 denotes the channel CH, 10 denotes a segment table, 11 denotes the page table, 12 denotes the page table entry position, 13 denotes the page invalidation bit PI, 14 denotes access protection data ACC , 15 denotes a physical page address PPA, 16 denotes a control register CR, Yl denotes a CCW (channel command word) address storage register CCAW, 18 denotes a storage register for main logical memory addresses CLAR, 19 denotes a CCW (channel command word) storage register CCCW, 20 denotes a Storage register for page table entry data CTLB, 21 denotes a control register within the channel CCR, 22 denotes a counter, 23 denotes a storage register for the main physical memory address CPAR, 24 denotes a valid bit I, 25 denotes a comparator circuit, and 26 denotes a unit control word UCW memory.

The main memory 1 has the segment table 16 and the page table 11, which are used for the dynamic address translation by the central processor unit (CPX1) 2, while the page tables entry point 12 within the page table has the page invalidation bit (PI) 13, which indicates the effectiveness the corresponding page table entry location, the access protection data (ACC) 14 of the logical page that corresponds to such a page table entry location and the physical page address (PPA) in which the corresponding page exists. In each central processing unit (CPU) 2 the control register (CR) is 14, which indicates the head address of the segment table 10, corresponding to that at that time space under execution. Each channel has the CCW address storage register (CCAW) 17 which stores the logical address and the channel access key of the channel control word (CCW) which is now is executed, the memory register for the logical main memory address (CLAR) 18, which is the main memory address (logical address) that is now being executed is, stores, the CCW storage register (CCCW) 19, which stores the CCW (channel control word or channel command word) under execution, the page table input data storage register (CTLB) 20, which is a copy of the page table entry point of the logical page to which access is carried out and corresponds to a validity bit (I-Bit) for this copy, and the control register (CCR) 21 in the channel, which is the head address of the segment table corresponding to the space to which an access is carried out, saves. The main logical memory address (CLAR) storage register 18 within each Channel (CH) 3 is composed of the logical page address part and the address part in the page, and contents of the addresses in the page can be changed by means of the counter 22. From any channel (CH) an access to the main memory is carried out by means of the memory register for the physical main memory address (CPAR) 23, whichever is always the value which holds the physical page address (PPA) in the storage register for the page table entry data (CTLB) 20 and the address on the page in the memory register for the main logical memory address (CLAR) 18 couples. A valid bit (I) 24 in the page table entry data storage register (CTLB) 20 is synchronously set to "1" when any central processing unit (CPU) 2 issues the ENABLE TLB command, which will be described later. In addition, each channel (CH) 3 has a comparison device 25, the access protection data (ACC) in the storage register for the page table entry data (CTLB) 20 and the Channel access key in CCW address storage register (CCAW) 17 compares. Besides, everyone owns Channel (CH) 3 different types of circles, for example the unit control word (UCW) storage area (subchannel) 26 which contains the executable condition of the channel programs, as in the case of the existing channel.

The dynamic address translation operation is performed in each channel as explained below. The central processing unit (CPU) 2 sets First the head address of the channel program and the channel access key for the channel address word (CAW) (not shown) when an input-output request is issued once and then it issues the SIO command off. The channel (CH) 3, which is determined in the operand of the 3IO command, sets the channel address word (CAW) and the content of the control register (CR) 16 into the CCW address storage register (CCAW) 17 and the control register (CCR) 21 within the channel, this provides access to the segment table entry

executed on the basis of the address which is taken from the head address of the segment table which is specified by the control register (CCR) 21 in the channel and the channel program head address in the storage register for the logical main storage address (CLAR) 18 is determined, can be obtained s. Then an access is made to the page table entry location executed, based on the address, which from the page address of the page table header address, which is contained in this entry position, and the channel program header address in the memory register ster for the main logical storage address (CLAR) 18 can be obtained, after which the content in the memory register for the page table (CTLB) 20 in channel (CH) 3 is copied, "0" becomes the Validity bit (I) 24 in the memory register for page table ι s entry data (CTLB) 2β. The above process is called dynamic address translation (DAT).

The channel couples the physical page address in the storage register for the page table entry data (CTLB) 20 and the address on the page in the memory register for the logical main memory address (CLAR) 18, the real address for the main memory (MM) 1 in the storage register door generates the physical one Main memory address (CPAR) 23, makes an access to the main memory (MM) 1 and then accesses the Channel control word (CCW) to. Channel (CH) 3 decodes this channel control word (CCW) and sets an input-output device (10) in operation. If the execution of this channel control word (CCW) is linked to an access to the main memory, the channel Jo (CH) 3 the logical address in the channel control word (CCW) in the memory register for the main memory address (CLAR) 18 for dynamic address translation (DAT), as in the above case, and then it sets the physical Address in the memory register for the physical main memory address (CPAR) 23.

If the execution of the channel control word (CCW) involves an access to the main memory area which is composed of several consecutive bytes. Once a value has been set in the memory register for the main physical memory address (CPAR) 23, the channel (CH) 3 accesses the main memory according to a physical address which is only available by the physical page address in the memory register for the page table entry data (CTLB) 2 · and has been generated by the address on the page in the memory register for the logical main memory address (CLAR) 18, and which has been added up by means of the counter 22.
Conditions:

1. The address in the page has overflowed as a result of the accumulation in the SS address part in the page in the storage register for Main Logical Storage Address (CLAR) 18 has been executed.

2. The valid bit (I) 24 in the page table entry data (CTLB) 20 storage register is "1".

If the above conditions are met, channel (CH) 3 carries out the dynamic address translation described above (DAT) and makes an access to the main memory (MM) 1 by having a physical Looks for address in memory register for physical main memory address (CPAR) 23.

Thereafter, the channel (CH) 3 sequentially executes the channel control word (CCW) in the channel programs, such as in the case of existing channels, and when the start of execution for a new channel control word with coincides with an access to the main memory, the channel repeats the above each time Operations.

In addition, when the contents of the page table entry data storage register (CTLB) 20 are checked by the dynamic address translation (DAT) is rewritten, the page valid bit is used in each case (PI) and the access protection data (ACC) checked. If the page valid bit (PI) is a "1", the generates Channel the page fault objection, or if the result of the comparison between each security data (ACC) and the channel access key in the memory register indicates an access prohibition for the CCW address (CCAW) 17, the comparison device generates 25 the defense.

When these objections are generated, the channel (CH) 3 generates an interrupt for the central Processor unit (CPU) 2 and generates and issues an instruction for setting operations to the input-output device (IO) to stop the execution of the channel programs.

An operation is then described below in order to set the valid bit (I) 24 in the storage register for the Set page table entry data (CTLB) to "1" using the command TLB RELEASE. Fig. 3 shows an embodiment of the circle, which directly the command TLB RELEASE in the central processing unit (CPU) and in the channel (CH). In Fig. 3, 1 denotes the main memory MM, 2 denotes the Central processing unit CPU, 3 denotes the channel CH, 20 denotes the storage register for the page table entry data CTLB, 24 denotes the validity bit 1.26 denotes the unit control word UCW memory, 30 denotes the command register, 31 denotes the decoder DEC, 32 denotes the control circuit for command TLB RELEASE, 33 denotes the table conversion index buffer TLB, 34 denotes the memory access control circuit, 35 denotes the TLB ENABLE LEVEL channel control circuit, 36 denotes the data transfer control circuit, 37 denotes the input-output interface control circuit. The command TLB RELEASE is a command that provides information about the update of the entry of the Address translation table or to change this entry. The operations due such a command are explained with reference to FIG.

The central processor unit (CPU) Z decodes the command code (OP) in the command register 3 · in the decoder (DEC) 31 and puts the control circuit 32 into operation for the command TLB ENABLE when the command TLB ENABLE is issued. The control circuit 32 for the command TLB ENABLE gives the information of the output of the command TLB ENABLE to the channel (CH) 3. (©)

When the information about the issue of the command TLB RELEASE is received, the TLB RELEASE-BEN control circuit sends 35 the interrupt command to the data transfer control circuit if the channel is now in State for the data transmission is to the data transmission to interrupt at the most desirable step. ((F))

Then the TLB ENABLE channel control circuit informs 35 the RELEASE TLB command control circuit 32 of the central processing unit (CPU) 2 from the sub-

interruption of data transmission. ((T))

The control circuit 32 thus rewrites the validity bit (I) as a "1" for the command TLB RELEASE into each entry of the table conversion index buffer (TLB) 33 in the central processing unit s (CPU) 2 and then outputs the information to the channel (CH) 3 to also set the validity bit (I) 24 of the memory register for the page table entry data (CTLB) 2 · to be changed to »1«. This information causes the channel control circuit for TLB ENABLE 35 again valid bit (I) 24 as a "1" in the storage register for the page table entry data (CTLB) 20 writes. (©)

The channel control circuit for TLB ENABLE 35 gives to the central processing unit (CPU) 2 the information that the invalidation of the memory register for the page table entry data (CTLB) 2t has been completed ((T))

This ends the execution of the RELEASE TLB command.

An operation for giving information of the page fault objection and the protection objection to the central processing unit (CPU) and the input-output device will now be explained. F i g. 4 shows an embodiment of the circle that directs the page fault objection and protection objection in the Channels. In Fig. 4, 2-1 and 2-2 denote them Central processing unit CPU, 3 denotes the channel CH, 18 denotes the storage register for the logical Main memory address CLAR, 2t denotes the memory register for the page table entry data CTLB, 25 denotes a comparison device, 26 denotes the unit control word UCW memory, 36 denotes the data transfer control circuit, 37 denotes the input-output interface control circuit, 40 denotes the selector circuit, 41 denotes a circuit for determining a CPU interrupt, 42 denotes a page fault address send gate, 43 denotes a page fault detector line, 44 denotes a protective object detector line, 45 denotes a draws a page fault break request line, 4 * denotes a guard break request line, 47 denotes a page fault address transmission designation signal line, 48 denotes an end of break information line, and 49 denotes a page fault address line.

The operation for informing the central processing unit (CPU) and the input-output device about the page fault objection is carried out in the manner described below. so

In Fig. 4 is made by means of the page fault detector line 43 the fact that the page invalid bit (PI) is in the storage register for the page table entry location (CTLB) 20 is a "1" is given to the data transfer control circuit 36. The data transfer control SS Circuit 36 gives the information that a page fault break request is present to the circuit via the page fault break request line 45 Determination of a CPU interrupt. The circuit 41 causes the determination of a CPU interruption, that the central processing unit is interrupted, as in the case of channel cross-call, and indicates the data path in selector circle 40. The data transfer control circuit 36 issues an interrupt request and opens the page address send determination signaling line 47 the page fault address send gate 42 and outputs from the memory register for the logical main memory address (CLAR) W sent error address on the page fault address line 49. This changes the page fault interrupt request and the page fault address for the designated central processing unit (CPU) from channel (CH) 3 through the page fault interrupt request line 45 and the page fault address line 49 the pages. The central processing unit (CPU) performs the Operation similar to those performed when there is a page fault in the central processing unit (CPU) is generated to generate conversion objections and at the same time stores the address in which an error has been generated in the channel for the pinned address of the previous area of the Central Processing Unit (CPU). Here the memory area can be the same as for the storage of the Conversion objection address in the central processing unit (CPU). The data transfer control circuit 36 in the channel (CH) 3 issues an interrupt request to the central processing unit side and inquires at the same time from the input-output interface control circuit 37 to the in the side of the channel to carry out a certain sequence of completion. The input-output interface control circuit 37 is such a completion sequence as in the case that an error is generated in memory access from the channel on the input-output interface. When the interruption end information comes back through the interruption end information line 48 from the central processing unit (CPU) 2 and when the interruption sequence end information is sent from the input-output interface control circuit 37, the data transfer control circuit 36 completes a series page fault handling.

An operation for transferring the information from a protective objection to the central processing unit (CPU) and the input-output device becomes like follows executed. According to Fig. 4, the information is from the generation of a protective appeal on the Protective objection detector line 44 coming out of the comparison device 25 is given to the data transfer control circuit 36. The data transfer control circuit 36 informs the CPU interruption determination circuit of the existence of the Protection object interrupt request, for this purpose the protection object interrupt start line 46 is used. The circle 41 to determine a CPU Interrupt determines the central processor unit to interrupt as in the case of the page miss interrupt, and then shows the data history in selector circuit 40. This is via the protection interruption interrogation line 46 the Protection barrier query to the central processing unit (CPU) determined by channel (CH) 3. In contrast to page fault interruption, no address is transmitted. The data transfer control circuit 36 issues the interrupt request to the central processing unit and at the same time interrogates the input-output interface control circuit 37 in order to execute the completion sequence determined by the channel.

The input-output interface control circuit 37 executes the completion sequence which is similar to that performed by the channel on the input-output interface when a memory access error is generated. Then, when the interruption end information comes back from the central processing unit (CPU) 2 via the interruption end information line 48, and when the completion

9 ίο

t | After information has been sent from the input-output interface control circuit 37, is completed the data transfer control circuit 36 performs a series of protection appeal processing.

In the above explanation, the channel was identified as a 5th Take the example of the unit which uses the main memory together with the central processing unit and carries out dynamic address translation. However, this invention is not related to the channel is limited, and it is clear that the present invention is applicable to such a unit as that shown in FIG Sub-assembly adapter can be used. In this case the sub-arrangement corresponds to the input-output device.

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Claims (2)

Patent claims: 1. Dynamic address translation arrangement for a channel (3) or an adapter (4) of a s Sub-arrangement (7) in a data processing system with a main memory (1) and a central processing unit (2), in which an interruption of the processing of a memory page allowing channel (CH 1, CH 2) or adapter (4) to the sub-assembly (7) a copy of at least one in an address translation table (page table U) contained entry position (12) which the physical address (PPA) of the memory page to be processed stores, is established, marked by a storage register (CTLB 2 *) in the channel or adapter of the sub-array with areas for storing the data (PI, ACC, PPA) of the copy of the entry point (12) in the address translation table (U) in the main memory (1) and for storing a validity bit (I) indicating the copy as valid, a counter (22) in the channel or the adapter for changing the respective addresses within the memory page containing the copy of the entry position (12) in the address translation table (11) is assigned, and one with the central processor unit (2) in operative connection device (35) in the Channel or the adapter for changing the state of the area (24) containing the valid bit (I) of the memory register (2) when the central processing unit has received an instruction to update the corresponding entry position (12) in the address Translation table (11) or a command indicating a change in this entry position (12) releases so that the validity bit (I) indicates the copy of the relevant entry point (12) as invalid. 2. Dynamic address translation arrangement according to claim 1, characterized in that a comparison device (25) for comparing access protection data (ACC), which are stored in the memory register (CTLB 20), and an access key (17) which is in the channel or sub- arrangement adapter is included, and that a device (44, 36, 46) is provided which outputs information to the central processing unit if the comparison result obtained by the comparison device indicates the inability to access the addressed memory page .