DE2802761A1 - STORAGE UNIT - Google Patents

Description

BLUMBACH · WESER · BERGEN. CHANDLER

PATENT LAWYERS IN MUNICH AND WIESBADEN

Patentconsult Radeckestraße 43 8000 Munich 60 Telephone (089) 883603/883604 Telex 05-212313 Telegrams Patentconsult Patentconsult Sonnenberger Straße 43 6200 Wiesbaden Telephone (06121) 562943/561998 Telex 04-186237 Telegrams Patentconsult

WESTERN ELECTRIC COMPANY INCORPORATED

NEW YORK, N.Y. 1oo38 / USA Lynes 14

Storage unit.

The invention relates to a memory unit with a multiplicity of word lines, a multiplicity of digit lines, which cross the word lines in a non-conductive manner and a multitude of storage locations at the respective Define crosspoints and with a memory cell that is associated with the associated one at each memory location Crosspoint defining word and digit line is connected, each memory cell having a transistor comprises three zones and a capacitor is connected to the transistor.

Considerable effort has been made in the development of storage arrangements in recent years which are manufactured as highly integrated (LSI) semiconductor wafers with the simplest possible processing can. This has resulted in a large number of proposals for relatively simple memory cell constructions result. A particularly simple memory cell is in the

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Munich: R. Kramer Dipl.-ing. ■ W. Weser Dipl.-Phys. Dr. rar. nat. ■ P. Hirsch Dipl.-Ing. · H. P. Brehm Dipl.-Chem. Dr. phil. nat. Wiesbaden: P.G. Blumbach Dipl.-Ing. · P.Bergen Dipl.-Ing. Doctor of Law · 6. Zwirner Dipl.-Ing. Dipl.-W.-Ing.

U.S. Patent 3,876,992. Every single memory cell according to the aforementioned patent has a single transistor and an associated capacitor.

Despite the simplicity of the cells shown in said US Pat. No. 3,876,992, the production of such cells leads to FIG highly integrated form in a memory array does not have as small an area as it does in certain important ones Applications in practice is desirable. In addition, the production of such a highly integrated Arrangement required processing relatively complicated. In addition, the complicated curve shape makes it difficult the voltage that must be applied to the word lines of the arrangement during write and read operations, the construction, the overall arrangement.

The application of the technique according to the aforementioned US-PS In particular, 3,876,992 does not appear to fit with common collector arrangements found in certain bipolar integrated circuits are used. For example, it would be complicated insulation structures required that separate the different collectors of the transistors. A desirable manufacturing process known as the GIMIC-O process, requires a common collector arrangement. and therefore does not fit the technique of the aforesaid US Pat. No. 3,876,992.

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There is therefore a need for a simple, small-area memory cell that can be more easily integrated into a large scale Can produce shape and by applying voltages with relatively simple curve shapes can be operated. Such a cell, if available, would improve manufacturing enable highly integrated memory arrangements.

The invention has set itself the task of creating a memory with the aforementioned properties » In order to achieve this object, the invention is based on a memory unit of the type mentioned at the outset and is characterized in that a first region of the transistor is connected to the word line, which is the Crosspoint defined at which the memory cell is coupled, that a second zone directly with a reference potential point and that the third zone is connected to the digit line via the capacitor, the defines the cross point at which the memory cell is coupled.

The invention is described in more detail below with reference to the drawings. Show it:

1 shows a simplified memory arrangement with special exemplary embodiments for bipolar cells,

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made in accordance with the principles of the invention;

FIG. 2 write and read signals which are applied to the arrangement according to FIG. 1; FIG.

Figures 3 to 7 are cross-sectional views of part of a highly integrated version of the memory arrangement according to Fig .;

8 shows a top view of part of the highly integrated arrangement according to FIGS. 3 to 7J

9 shows a simplified memory arrangement with special exemplary embodiments of MOS cells, made in accordance with the principles of the invention.

Fig. 1 shows a simplified circuit diagram of a read-write memory unit 1o with random access, which is a component of a matrix arrangement 11 as an embodiment according to the basic idea of the invention contains. The matrix 11, which lies within the dash-dotted line in FIG. 1, contains an arrangement of coordinates, which includes a plurality of horizontal and vertical lines, their crossing points define a plurality of storage locations. The horizon-

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Tal lines 12, 13 ... η should be used as word lines and the vertical lines 14, 15 ... m are referred to as digit lines.

A large number of standard memory configurations are known, each of which has at least one arrangement of the one shown in FIG shown type. In a special embodiment, two interconnected matrix arrangements, each containing 64 word lines and 128 digit lines, combined with conventional decoders, drivers and a timing control circuit to produce a memory signal 16,384 individual memory locations. Such a system is commonly referred to as i6K-bit memory.

According to FIG. 1, an exemplary embodiment for a memory cell which is produced in accordance with the basic concept of the invention is coupled to each memory location of the arrangement 11. In order not to overload the drawing too much, only four such cells 17 _f 18, 19 and 2o are particularly shown. The cells are expediently all identical.

Each cell has a single pnp transistor as well a capacitor connected in the manner shown. For example, cell 17 contains the Transistor 21, whose base is connected directly to word line 12, and whose emitter is connected to the digit line via capacitor 22 14 and its collector are directly connected to a reference potential point, for example earth.

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The selection of a particular word line in FIG. 11 is carried out in the usual way by applying a data word to Input lines 24 ... f of a unit 26 which contains word line decoders and drivers. On appropriate A specific digit line or a group of digit lines is selected by creating a Data word on input lines 28 ... ρ of a unit 3o containing the digit line decoder and driver. The order 1 also usually has read amplifiers that determine during read operations whether O or 1 representations are stored in selected cells of the arrangement.

The mode of operation of the unit 1o according to FIG With reference to the voltage waveforms according to FIG. 2 are described. It is assumed that initially, i. before the point in time denoted by t <j in FIG. 2,, each of the Word lines 12, 13 ... η is held at a rest potential of, for example, 5 volts. It is further assumed that an O representation in one of the cells, for example to be written into the cell 2o, which is connected to the through the word line 13 and the digit line 15 defined intersection is coupled. To perform such an O write operation, the word line 13 applied voltage to a negative voltage (for example -1 volt) during the interval between t .. and t ~ decreased while the voltage of the digit line 15 on

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O volts is held. No flow under these conditions Current through the emitter-collector path of the transistor 34 in the cell 2o. Accordingly, the one previously uncharged remains Capacitor 36 in cell 2o uncharged. This uncharged state represents, for example, the specification 0.

A memory cell is read in that those voltages are applied to the specified word and digit lines which are shown in FIG. 2 in the interval t 1 - t ^. These voltages are the same as the voltages shown in the interval tj - tp. Accordingly, if the capacitor in the interrogated cell is uncharged (representation of a 0 signal), no current flows on the digit line connected to the read cell. Then, the digit line of the associated sense amplifier indicates the absence of a current flow to the extent that one is stored in the retrieved cell 0th

The manner in which a 1 representation is produced in a selected memory cell is indicated by the curve shapes in the interval t, - - tg in FIG. Enroll a 1 in, for example, the cell 2o, a voltage is applied, for example, -1 volt to the word line 13 and a voltage of for example +5 volts to the digit line 15 °. This keeps the transistor 34 conductive and a current flows from the emitter to the collector. As a result, the capacitor

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36 charged to a voltage of about 5 volts (right side positive with respect to the left side).

The reading of the cell 2o, which contains the charged capacitor, is shown in FIG. 2 in the interval t "- t _Q. In this so-called 1-reading interval, the collector-base junction of transistor 34 is forward-biased. Accordingly, the transistor 34 can conduct a current in the reverse direction, ie from the collector to the emitter. As a result, the positive charge on the right side of capacitor 36 flows on the digit line to sense amplifiers 32 and then from ground across the collector-emitter path of transistor 34 to the left side of capacitor 36. This downward flow of current on digit line 15 is in 2 shown as pulse 38. The sense amplifiers interpret the occurrence of such a pulse to the effect that a signal 1 was stored in the memory cell 2o.

The 1 read operation described above discharges the capacitor in the scanned cell. Therefore, in a known manner, the 1 previously stored in the cell is rewritten during a 1-write operation after each such interrogation. In addition, a so-called refreshing of the stored representations can be carried out periodically in the usual manner in order to compensate for charge losses in the arrangement shown.

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Both the matrix arrangement 11 and the conventional units 26, 30 and 32 in FIG. 1 are expedient and other associated units, not shown in Fig. 1, in the form of a microminiature semiconductor die manufactured. A number of technolo-

gien, for example the IL method or the standard buried collector method, are available to manufacture such a large scale integrated (LSI) die. According to a special aspect of the invention The basic idea was found to be that the bipolar integrated technology known as GIMIC-O is known, is particularly advantageous for producing the memory unit 1o considered here. In order to explain of the GIMIC-O method, reference is made to an article by P.T. Panousis and R.L. Pritchett "GIMIC-O - A Low Cost Non-Epitaxial Bipolar LSI Technology Suitable for Application to TTL Circuits ", IEDM Digest of Technical Papers, December 1974, pp. 515-518. The circuits for the above-mentioned units 26, 3o and 32 and others associated standard units are expediently using, for example, transistor-transistor logic circuits (TTL) or TTL-compatible circuits.

In accordance with the features of the invention, the matrix arrangement 11 according to FIG. 1 is produced in GIMIC-O form in such a way that that they only have a single transistor and an associated

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Neten capacitor at each of the plurality of crossing points, which are arranged by the perpendicular to each other Word and digit lines are defined. A large number of semiconductor wafers can then each containing such an arrangement with their associated units, on a semiconductor wafer in one relatively simple manufacturing processes can be generated. Any semiconductor die produced in this way is characterized by ease of manufacture, high bit capacity, high speed, and low cost. It is important that each memory cell on such a semiconductor wafer has an area of less as o, 645. 10 mm (1 square mil) occupied.

A group of specific steps will now be described as an exemplary embodiment with reference to FIGS can be used to produce a matrix arrangement 11 of the type shown in FIG. These steps which is a manufacturing process for integrated circuits according to the above-mentioned bipolar GIMIC-O technology can also be shown in the production of a single semiconductor wafer with the associated Use units 26, 30 and 32 as well as further standard units (not shown), those of the matrix arrangement 11 assigned. These units are expediently used as TTL or TTL-compatible circuits in a manufacturing process simultaneously with the production of the matrix

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arrangement 11 generated. In the following, however, only the production of the arrangement 11 will be emphasized.

Fig. 3 shows a p-type semiconductor substrate 5o with a specific resistance between about 8 and 20 ohms. cm. A masking layer is created using conventional lithography processes 52 of silicon dioxide with a thickness of 0.8 micrometers on the surface of the substrate 5o with a selective pattern made. The word line areas of the arrangement 11 are in the unmasked sections of the substrate 5o by ion implantation of a superficial phosphor layer and diffusion of the layer generated to a depth d of about 8 microns. A large number of such n ~ -regions (for example the regions 54 and 56 in Fig. 3) are produced in the substrate 5o. With the special memory configuration assumed above Accordingly, 64 such regions or word lines that are at a distance from one another are simultaneously in the substrate 5o of each of the two arrays formed in each 16K-bit platelet area are included.

In a special embodiment of the invention, the word line regions have a spacing a (FIG. 3) of approximately 5 microns, and each area extends about 2 mm in the z-direction. These areas correspond to the horizontal ones Word lines 12, 13 ... η in FIG. 1.

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The next step in the manufacturing process considered here is shown in FIG. Another silicon dioxide layer 58 with a selective pattern is produced using conventional methods on the surface of the substrate 50 and serves as a mask for an ion implantation. Channel boundaries including p ⁺ regions, such as regions 6o and 62 in FIG. 4, are then formed on substrate 5o. These delimitation regions, which extend in the same direction as the word line regions 54 and 56, are produced, for example, by means of a conventional two-stage boron implantation process. The resulting boundaries 6o and 62 have a depth b of about 1.2 micrometers, with a peak value for the doping concentration occurring at a depth of about 0.7 micrometers.

A further silicon oxide masking layer 65 (FIG. 5) with a selective pattern is then produced on the surface of the substrate 5o. Then n ⁺ regions 66, and 7o are formed by diffusion into unmasked sections of word line regions 54 and 56. As an example, these areas 66, 68 and 70 are produced by diffusion of phosphorus into the substrate, resulting in a resistivity of less than about 30 ohms square. The regions 66, 68 and 7o, which are intended to increase the conductivity of the word line regions, have a depth of approximately 0.6 micrometers and a width e of approximately 5

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Micrometer.

Next, as shown in FIG. 6, a further masking layer is applied to the surface of the Substrate 5o formed. This layer consists, for example, of a silicon dioxide film 72 with a thickness of 5,000 Angstrom units. In a known manner, openings in the masking layer are spaced from one another along the Word line areas produced. For example, in FIG. 6 there is an opening in the masking layer 72 above the Word line area 54 shown. In a particular embodiment, each such opening is square Area of about 5 microns by 5 microns.

Thereafter, p-regions, for example region 74 in FIG. 6, are produced by ion implantation in the spaced-apart sections of the word line regions which are accessible through the above-mentioned openings in masking layer 72. These p-regions, which are formed, for example, in a conventional boron implantation process, each represent the emitter zone of one of the transistors in the matrix arrangement 11 in FIG. 1. Accordingly, the regions 50, 54 and 74 in FIG. 6 form the collector base - and emitter zone of such a transistor.

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A layer of dielectric material is created over the entire surface of the arrangement in FIG. This layer, for example made of a silicon dioxide film with a thickness of 2oo to 5oo Angstrom units is designated by 76 in FIG. 7. Next be spaced apart metallic strips, for example the element 78 in Fig. 7 »on the dielectric film 76 is generated. These bands are rectangular are arranged with reference to the word line areas described above and form the digit lines in FIG integrated circuit arrangement. Storage capacitors arranged at a distance from one another are used in the arrangement defined between the digit lines and the underlying p-zones (emitters), for example zone 74 in Fig. 7.

In a particular embodiment of the invention, each digit line tape comprises an aluminum strip, which extends about 5 micrometers in the z-direction (Fig. 7) and about 1 mm in the x-direction. Alternatively you can a number of other single metals or combinations of metals (for example, a triple layer of titanium, Platinum and gold) are deposited on the structure to form the aforementioned digit lines.

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A plan view of part of the matrix arrangement 11, the manufacture of which has been described above, is shown in FIG. 8. The spaced apart metal films 78 which form the digit line bands are shown in FIG. In addition, the openings 8o in the masking layer, in which capacitors are defined between the digit lines 78 and the underlying p-emitter zones in the substrate, are shown there in dashed lines. Dashed bands 82 in FIG. 8 represent n ⁺ regions corresponding to regions 66, 68 and 7o for increasing conductivity and shown and described in FIG. 7.

As an example, the digit lines 78 according to FIG. 8 have a distance j of about 10 micrometers. Furthermore is In a special embodiment, the vertical center-to-center distance k between two adjacent openings 8o is approximately 2o Micrometer.

During the above-described manufacturing method, a plurality of M _a is trixanordnungen 11 simultaneously formed on a single semiconductor wafer. At the same time, the ends of the digit and word lines of each such arrangement are connected to the units 26, 30 and 32 of FIG. 1 and other associated standard units in order to create a plurality of read / write memories on each semiconductor wafer. That way becomes a

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A multitude of small-area, fast and cheap low-power storage systems produced simultaneously. A special embodiment of such a memory, which is in LSI-GIMIC-O-form according to the basic idea of the invention has been made forms a semiconductor chip with dimensions of about 4 mm by 4 mm. The access and cycle times of this embodiment were determined to be less than 1oo or 2oo ns.

A special embodiment for a MOS version a memory unit according to the invention is shown in FIG. In this embodiment, each memory cell has in the memory matrix a single MOS transistor and an associated capacitor in the illustrated Circuit on. For example, the cell 84 in Figure 9 contains the field effect transistor 86, the gate of which is directly connected to the Word line 88 is connected. One of its source and drain electrodes is connected to the capacitor 9o Digit line 92 and the other directly to a reference potential point, for example earth.

The arrangement according to FIG. 9, which is similar to the arrangement described above in connection with FIGS. 1 and 2 is operated easily in a highly integrated manner Manufacture the mold according to the usual manufacturing processes

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It should be noted that the methods and arrangements described above are only examples. Numerous modifications and alternatives can be made by those skilled in the art without departing from the invention. For example, npn transistors can be used for the pnp transistors shown in FIG. 1 in a simple manner can be used when the polarity of the signals shown in Fig. 2 is changed accordingly. In addition, in the case of the transistors shown in FIG. 1, the emitters can be connected to ground instead of the collectors. In this case, each storage capacitor lies directly between a digit line and the collector of the assigned one Transistor.

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Claims (7)

BLUMBACH · WESER · BERGEN · KRAMER ZWIRNER - DEER. BREHM 280276 PATENT LAWYERS IN MUNICH AND WIESBADEN Patentconsult Radeckestrasse 43 8000 Munich 60 Telephone (089) 883603/883604 Telex 05-212313 Telegrams Patentconsull Patentconsult Sonnenberger Straße 43 6200 Wiesbaden Telephone (06121) 562943/561998 Telex 04-186237 Telegrams Patentconsult Claims Memory unit with a plurality of word lines, a plurality of digit lines that form the word lines non-conductive cross and a plurality of storage locations at the respective crossing points define, and with a memory cell that is assigned to each memory location, a cross point defining word and number line is connected, wherein each memory cell comprises a three-zone transistor and a capacitor connected to the transistor is, characterized in that a first zone of the transistor (21, 86) with the word line (12, 13 ... n) is connected, which defines the cross point at which the memory cell (17, 84) is coupled is, that a second zone is directly connected to a reference potential point , 809830/0921 originally inspected Munich: R. Kramer Dipl.-Ing. · W. Weser Dipl.-Phys. Dr. rer. nat. · P. Hirsch Dipl.-Ing. · H. P. Brehni Dipl.-Chem. Dr. phil. nat. Wiesbaden: PG Blumbach Dipl.-Ing. · P. Bergen Dipl.-Ing. Dr. jur. · G. Zwirner Dipl.-Ing. Dipl.-W.-Ing. - \ "'28Ü27b I and that the third zone is connected via the capacitor (22, 9o) to the digit line (14, 15, m) which defines the cross point at which the memory cell (17, 84) is coupled. 2) storage unit according to claim 1, characterized in that that the plurality of memory cells on a single semiconductor body (5o) of an integrated circuit are formed and that the semiconductor body is the second zone of each of the transistors of the integrated circuit represents. 3) memory unit according to claim 2, characterized in that the transistor is a bipolar transistor and that the first zone is the base, the second zone is the collector and the third zone is the emitter of the bipolar transistor are. 4) memory unit according to claim 2, characterized in that the transistor is a MOS transistor and that the Gate the first zone, the source electrode the second zone and the drain electrode the third zone of the MOS transistor are. 809830/0929 ORIGINAL INSPECTED 5) memory unit according to claim 2, characterized by durc'h a word line decoder and driver unit (26) connected to the word line rods, one to the digit lines connected digit line decoder and driver unit (3o) and one to the digit lines coupled sense amplifier unit (32). 6) memory unit according to claim 5, characterized in that the word lines have a plurality of parallel, spaced apart regions (54) of a specified conductivity type formed by ion implantation are made in the surface of a substrate of the opposite conductivity type to the plurality of To form word lines that at least one area (66, 68) of high conductivity with the specified conductivity type is diffused into said areas in order to Increase conductivity of the word lines, and that channel delimitation areas (6o, 62) of the opposite Conductivity type introduced into the spaces between the first-mentioned areas by ion implantation are. 809830/0929 7) Memory unit according to claim 6, characterized in that an insulating layer (72) provided with openings is applied to the surface of the substrate, that the openings in the layer lie over spaced apart memory cell positions and are arranged along each of the word lines,
that through the openings in the surface of the substrate by means of ion implantation, regions of the opposite conductivity type are formed in order to produce the emitter zones (74), that an insulating layer is deposited on the entire surface of the storage unit, that a multitude of parallel and spaced apart metallic digit lines on the second Place said insulating layer at right angles to the word lines at the indicated memory cell positions are deposited to form lines that are capacitively coupled to the emitter regions. 809830/0929