DE2758276A1 - METHOD AND DEVICE FOR ERROR REDUCTION IN THE PROCESSING OF MULTIBIT DIGITAL SIGNALS - Google Patents

Description

Dipl.-Ing. H. MITSCHERLICH Ü-8000 MUNICH 22 Dipl.-Ing. K. GUNSCHMANN Gteinsdorfstrasse 10 Dr.rrnot. W. KÖRBER ^ ⁽⁰⁸⁹⁾

Dipl.-Ing. J. SCHMIDT-EVERS PATENT LAWYERS

- Io -

SONY COiRPOKATION

7-35, Kitashinagav / a 6-chome

Shinagawa-ku

T old, ο / Japan

Method and device for reducing errors in the processing of multi-bit digital signals

The invention relates to the processing of digital signals in such a way that a high probability for the Identify and correct errors in certain stages of processing. In particular, the invention relates deriving primary pulse code modulated (PCM) multibit digital signals from an analog signal, deriving secondary ones PCM signals from the same values of the analog signal as in the primary PCM signals were recorded, the delaying of either the primary or the secondary signals and the Combining groups of the delayed signals in an interleaved sequence with groups of the relatively undelayed signals.

In the pending patent applications P 2? o5 4o6.4 of 9.2.1977 and P 27 o7 435-7 of 02.21.1977, which correspond to the Japanese patent applications 13397/76 of 02.2.1976 and 19198/76 of 02.24.1976, and both of which refer to the applicant of present application is proposed

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been putting analog audio frequency signals into a video tape recorder to process. These patent applications and a third one schv / ebende patent application dated December 22, 1977 »that of the Japanese Patent application 157235/76 of 2 * f.12.1976 corresponds to describe Method for coding the audio frequency signals by means of PCii-i'technology and for arranging the resulting pulse signals such that they conform to a video format and can be easily handled by a video tape recorder.

The analog signals are sampled at a frequency that is essentially at least twice as high as the highest in is the information frequency occurring in such signals. A suitable scanning speed is three times that horizontal line rate of the video signal, .Ta this converts the resulting sampled signal into the correct one Relation to horizontal video sync signals inserted into the pseudo-video format.

Video tape devices are capable of using audio frequency signals excellent fidelity, but there is still the problem of occasional loss of signal due to a failure or impulsive lumps. There the playback quality possible with equipment of the type described below is so high that it is compatible with Compatible with commercial standards, it is important even occasional To avoid errors in the processed signals.

One object of the invention is to minimize the error in the processing of digital signals by providing a time shift of groups of such signals in relation to groups of signals that contain essentially the same information contain.

Another object of the invention is to combine code signals with groups of primary and secondary hultibit digital signals,

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among other things enable the determination of whether both processed signals or one or neither of them are error-free, and to ensure that one of the signals is selected for further processing because of its smallest error.

According to the invention, a cultibit digital signal referred to as a primary signal and a secondary iiultibit digital signal which is encoded in the same PCM arrangement with the same information, apart from the fact that the lowest order bits of the primary signal are omitted from the secondary signal, are in corresponding or related groups comprising a digital word signal. Either the primary signal is delayed relative to the secondary signal, or the secondary signal is delayed relative to the primary signal and then groups are interleaved to form a sequential ilultibit signal. After processing this sequential signal, related groups are brought back into coincidence and one of the signals is selected for further processing. This number is based on which signal is error-free at this point. If both signals are error-free, a predetermined one of them is selected for further processing. V / hen none of the signals is error-free, a forward I reciprocating temporarily stored signal for a second time processed v / ground, instead of processing one of the failure signals.

To determine which signal is healthy, cyclic redundancy check code (GIiC) signals are obtained for both the primary and secondary PCIi signals prior to processing, and these CRC signals are interleaved with the primary and secondary signals, to form a complete sequential signal. In determining whether there is an error in any of the processed signals, the coincidence of the primary and secondary signals is measured, and if they do coincide , the invention provides that either of them, usually

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the primary signal, chosen for further processing.
At the same time, the CliC signals for the corresponding

primary and secondary signals are used to ground the j

sfeimman ^ Qb either the primary or the secondary signal ■

is error-free. If only one of these signals is error-free, j

v / as means that there is no coincidence j for the two signals

has been determined, the error-free signal is automatically I

chosen for further processing. Each for the other;

Processing selected signal is stored in a temporary memory j

circle pinned to be used again when!

neither the primary nor the secondary signal of the next pair S

are error-free. The continued repeated use of the-!

same signal is compatible with the fact that there is less!

bothers, if the output signal does not change at all in:

an additional time step when it changes significantly. j

About time for the insertion of the secondary oignalgru ^ pen and eggs

To provide CRC signals in the sequence of the primary signal groups;

so / ohl the primary as well as the secondary signals ' ^:

subject to time compression. This can be done by: these signals are fed to stores at a clock speed

and from the memories with a different clock speed!

read v / earth. For simple treatment in the following I.

Circuits, such as the coincidence circuit, \

it is preferable that the time compression of the primary sig-; nale is exactly the same as that of the secondary signals. This one

both signals contain essentially the same information, i

except possibly those in the least important '

3ita the primary signal encoding information, the i

Time compression should be about 2: 1. In fact, through:

Leave enough prudent 3its of the primary signal,;

the bits required to transmit the CRC signals

the sum of the truncated secondary signal groups j

plus the zv / ei sets of CRC signals exactly equal to the number:

Bits of the primary signal groups are made so that a j Time compression of exactly 2: 1 to an evenly dense

sequential full signal leads. ■

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-ο ¹

An embodiment of the invention is based on the following
of the drawings. Ss shows:

FIG. 1 shows a block diagram of a signal processing system according to the invention;

Figure 2 is a block diagram of a coding portion of the circuit in Figure 1;

FIGS. 3A to 3F symbolic representations of digital signals
to explain the mode of operation of the circuit in
Figure 1;

FIG. 1 shows a block diagram of a time compressor for use in the circuit in FIG. 2;

FIG. 5 shows a wave diagram of signals which, when operating the
Circuit in Figure k can be obtained;

Figure 6 is a block diagram of a CRC encoder and a
Gate circuit, which can be used:; endun ^ in the
Circuit of Figure 2 are suitable;

FIGS. 7a to 7a to explain the mode of operation of the two embodiments of the circuit in FIG. 6;

Figure 8 is a block diagram of a for use in
Circuit of Figure 1 suitable decoder;

A further time compression is necessary, u: .i Raun between I. certain pulses for the insertion of horizontal and vertical j

Allow synchronous and synchronous signals. Since it further wishes j

is worth seeing, an integer complete or together- j

set groups in each horizontal video interval under j

spend, it is also desirable .Vortsynchronpulse between !

to be provided for each pair of composite groups. The ;

Term "composite" is used to indicate ;

that such a group has a primary signal digital location, the CRC- j

Signal for this 7ort, a time- i from the primary digital word

borrowed spaced secondary digital word and the CPC signal: for the secondary signal.

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FIG. 9 is a schematic circuit diagram of a decoder as shown in FIG
; the circuit of Figure 8 is used;

Figure 1 oA to 1oC '. Waveforms that occur during operation of the circuit
'. are obtained in Figure 9;

FIG. 11 is a schematic circuit diagram of a logic circuit

in Figure 3; i

; FIG. 12 shows a symbolic representation of digital signals which j

• are fed to the coincidence detector in FIG. 8; I. FIG. 13 a tradition table which shows the logical states for!

; Figure 3 illustrates operation of the circuit of Figure 8; j

': Figure lif a schematic circuit diagram of a switch and memory 1

I j

j circuit for use in the circuit of Figure 8; ·

i and I.

. FIG. 15 shows a symbolic representation of the processed signals

• to explain the error reduction.

One of the coding concepts to be used in the following disclosure is known as the cyclic redundancy check code (CSC). The mathematical aspects of the CPC are first described in three terms that relate to the
. the following execution forms are applicable. ■

j Cyclic redundancy check code ;

'■■ I

The CRC code is generally represented by a polynomial F (x) with j; of the indeterminate (indeterminant) χ and coefficients of a | j n-bit code (a., ^a _n -2 '*** » ^a 1' ^a o ^ expressed as follows:

! ~ n-1 n-2 '** o *

Vienn for example the 5-bit code (Ι00ΙΙ) through the polynomial
F (x) is expressed, then:

F (x) = X ^ + x + 1. i

This polynomial becomes the polynomial over the Galois field of 2 \

called. ;

i 809827/0927

The coding and decoding of the CRC code is essentially characterized by a division algorithm such that the Ccdepolynomial F (: :) is divided by the generator polynomial G (x).

Assuming that the code polynon in front of degree (k-1) for a k-bit code as M (x) and the generator polynomial in front of degree (n-k) is expressed as G (x), the division algorithm is:

i; (: :) x ⁿ " ^k = G (: OQ (x) + R (x)

in the Q (x) the quotient polynomial and R (x) the remainder polynomial are of the highest degree (n-k-1). It should be noted that the

The n-k coded code polynomial V (x) consists of the code polyziora H (x) x and the remainder polynomial R (x) added to this. Therefore the coded polynomial V (x) has degree (n-1) and is given by V (x) = M (x) x ⁿ " ¹ + R (x) = G (x) Q (x).

That is, the coded polynomial V (x) by the generator polynomial G (x) is divisible.

If next a noise signal represented by the polynomial 3 (x) expressed in the code polynomial V (x) during transmission is introduced, the code polynomial V '(x) on the decoding side is expressed as

V ¹ U) = V (x) + E (x).

If no error is introduced therein, then E (x) = ο applies. Then V '(x) = V (x), and consequently the polynomial V' (x) is divisible by the polynomial T (x).

If, however, the polynomial V '(x) in the decoder cannot be divided by the generator polynon G (x) and causes the generation of a residual polynomial R' (x), the polynomial V '(x) is to be regarded as having an error bit . Then the polynomial V '(x) is given as follows:

V «(x) = G (x) Q '(x) + R' (x).

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The polynomial V (x) should be divisible by the generator or poly nora G (x) such that the remainder polynomial 3 · (: Ο the remainder in the division algorithm must be the division of the polynomial Ξ (χ) by the generator polynomial G (x). Accordingly, it can be seen that the remainder polynomial R '(x) is a factor showing whether the code polynomial V '(x) contains the error bits or not. Such a residue is called a syndrome.

An example is given with the state n = 7, k = 4 and the generator polynomial G (x) = x ^ + x + 1 given.

(1) M (x) = x ³ + 1 = (1oo1)

M (X) X ⁵ " 3X ^ X ³ + R (x) M (x) x ³ = G (x) Q (x) R (x) = χ ² + χ χ) = χ ⁶ ₊ V (x) = J-Kx) X ³ + R (

+ x ² + χ = (loollio) (3) E (x) = x ^ = (0I00000)
(if) V (x) = V (x) + E (x) = x ⁶ + x ⁵ + χ ³ + x ² + χ = (ΙΙ0ΙΙΙ0)

V '(x) = G (x) Q' (x) + R '(x)
(5) R '(x) = x ² + χ + 1 = (111)

of

The basic circuit / CRC code encoder and decoder comprises a dividing circuit with the divider G (x), the produces the remainder, not the quotient. The dividing circuit is essentially formed by one shift register, each Stage is preceded by a modulo-2 adder, which is on a modulo-2-3asis (i.e. counting on base 2 without carry-over), the output signal of the previous stage and the output signal of the shift register are added depending on whether the responsible Element of the polynomial g ^ =! or g. = o is in the divider

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Hun is the generator polynon given in the above example as j

■ ζ ' I

G (x) = sr + χ + 1 i

Accordingly, the dividing circuit of the polynomial G (x) is a three-stage shift register with feedback loops from output to rnod-2 adders at the input and between the first and second level. The clock states in each shift register stage and the sixes example are shown:

.6 . .3

(i) E (x) = ο

V (x) =

χ + 1

+ χ

X + X

X X

Table I.

States in shift registers

Tact

input

(Initial state)

£ 5

t ⁶

^t 7

1 ο

1 I 1 ο

O O O

O O

the rest

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(ii) E (x) = x ⁵ V '(x) = x ⁶ + x ⁵ + x ⁵ + x ² + χ

χ ⁶ +: χ ⁵ + y? η KX ² H ■ i χ ⁶ - χ Λ. · Λ. ' HX ² H X ⁵ + X ³ H HX ² ι- X H
HX ² H X ³ ^ HX ² h>;
r X X ³ ι- χ + 1

Table 2

input 1 conditions in shift registers D ₂ Tact (Initial state) 1 ^D o ^D 1 O t. O O O O 1 1 O O t? 1 1 O 1 1 O 1 1 O O 1 1 O 1 1 O 1 1 «<d 1 1

the rest

Accordingly, the content of the shift register shows whether the transmitted code contains error bits or not.

2!

the remainder χ + χ + 1 j

• oim / om

The circuit in Figure 1 comprises a video tape recorder 1, the For example, it can be of the type to those in the above pending patent applications. The video tape recorder is an input terminal 1. and a Vaginal clergy 1 on.

The system is designed for use with stereophonic audio frequency signals, although it can be used with other types of signals. When designed for stereophonic audio frequency signals, it comprises two input terminals 2L and 22, to which the left or respectively. the right i'on frequency channel can be fed. The input terminal 2L is connected to a low-pass filter 3 ^, which in turn is connected to a sample and hold circuit ^ L. The output of the sample and hold circuit is connected to an analog / digital (A / D) converter 5L, the output of which is connected to a parallel / serial converter 6. j

The input terminal 2H is connected to the parallel / series 7 / andler 6 j via an identical circuit, namely a low-pass filter 33, a sample and hold circuit ^ R and an A / DV / andler 3? ..

The output of the parallel / serial converter 6 is connected to an encoder 7, which is described in detail below in connection with FIGS. The encoder followed by a time compressor 8, which provides the encoder for an additional time compression of the output signal to enable the Ziriiagung of synchronous signals in a synchronizing signal adding circuit .9 that follows the time compressor. 8 The output of the synchronizing signal adding circuit 9 is connected to the Singangsklemme 1 of the video-3andgerätes 1.

Up to this point, the circuit comprises the elements used to record a signal in the video tape recorder 1 .

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To play back the previously recorded signals, the
Output terminal 1 of the video handheld device with a synchronous

signal-Sliminierschaltung 1o connected, which the synchronizing signals j

extracted and used in the normal way when controlling the j

Tape device used. The output of the Elininierschaltung 1o!

is connected to a time expander 11, the distance j

between successive pulse signals to an equal to j

returns the shaped amount and closes the gaps, [

which were provided for inserting the sync signals. j

The output of the time expander 11 is connected to a decoder 12 j

connected, the one of the function of the encoder 7 opposite;

Exercises a set function and is described in detail below j

v / ird, especially in connection with the circuits in the!

Figures 8 to IZf. j

The output of the decoder 12 is connected to a series / parallel converter 13 which has two output signals
the output terminal is equipped with a digital / analog (D / A) - .. 'aiidler
1 / fL and the other with a D / AV / andler Τ4Ι-Ϊ for the left,
or right audio frequency channel connected. The outcome of the

D / A - '. 7andlers 1Z | L is via a low-pass filter 15L with a _; Output terminals 16L connected, and the output of the D / A converter

IZfR is similar via a low pass filter 15H with a. Output terminal 16Π connected.

The conventional reference oscillator circuits and the clock,!

Synchronizing and gate signal circuits which are connected in connection '

with the sample and hold circuits, the A / D and D / AV / and _: learners, the parallel / series and series / parallel -. / a.idlern, the

Time compressor and the time expander as well as the synchronizing signal!

Adding and eliminating circuits are used, and the '

Video tape recorders are all normal devices and need '

not to be described in detail. j

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In the operation of the circuit in FIG. 1, the tone frequency signals to be processed are sampled at a suitably high speed in the sampling and Ilalte circuits if L and if R. 3s is acceptable and satisfactory when the speed is three times the repetition speed of a horizontal video sync signal or et v / a if 7.25 kHz. With each scan, the corresponding A / DY / andler% and 3R 1S-Bic-PCM signals to the V / andler 6 Read information bits supplied by the Α / ΰ - '. Converters 5 ^ and 5 ^. The resulting multibit digital signal is shown in Figure 3A and contains a left channel signal with sixteen bits, which range from a most important bit Ii to a least important bit L, and a right channel signal, which also includes sixteen bits and a most important bit 7 . to a least important bit L is enough. Dio initially:. '- :: tränieren of in Figure 3A aargestellten üigitalsignals from the converter 6 is equal to the sampling period of time required and, therefore, is in this embodiment II / 3, where the horizontal line interval II is a video signal. The entire multibit digital signal shown in Figure 3A can be viewed as a digital word signal or a digital word group.

Digital word signals like that in Figure 3Λ v / ground with a constant Speed generated so that three such digital words essentially complete a horizontal line interval to complete. Un to get time for a forgetful signal The constant signal flow, which is similar to that in FIG. 3A from the converter 6 to the encoder 7, must have a time compression be subjected. That is; in the circuit shown in FIG.

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The 3 bits of the signal shown in Figure 3A are assigned to the switch
32 continuously fed in and one word alternating with the
Shift registers 33 and 34 connected. To achieve this,
the switch 32 is at the end of every 32 incoming 3its of
switched from one contact to the other. The information
is pulsed into the shift register with which the arm of the
Switch 32 is connected in a moment, through the

Figure 2 v / eist an input terminal 21, which is connected to a first
Time compression circuit 22 is connected. The outcome of the
Time correction circuit 22 is provided with a CI? C encoder 23 and

connected to a gate circuit 2h , with which the output!

output of the CRC encoder 23 is connected. j

The input terminal 21 is also connected to a gate circuit 25, the output of which is connected to a second time compression circuit 26. Its output is connected to a second CRC encoder 27 and to a further gate circuit j 28. The output of the encoder 27 is also connected to the |

Gate circuit 23 connected. The output of the gate circuit!

23 is via a delay circuit 29 with a gate J

circuit 3o connected, with which the output of the gate J

circuit 2h is connected. The gate circuit 3 ° v / eist one!

Output terminal 31 on. !

j The time compression circuit 22 reduces the time required for transmission

the time required for the digital word signal shown in FIG. 3A. A circuit shown in Figure h which achieves this; has a Zv / eipol- ^ transition switch 32, which is connected to the! Inputs of two 32-bit shift registers 33 and 3h is connected. The outputs of the shift registers 33 and 3h are with the
Terminals of a further switch 36 connected. The shift register 33 has a write clock terminal 33 · »and a read clock terminal 33R, and the shift register 34 has corresponding write clock and read clock terminals 34W and 34R.

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Write clock signal with a frequency equal to the frequency with which the 3its are generated in the converter 6 in FIG. 1, but they are activated by the read clock signal with a Read at a rate that is twice the rate at which they are written to. The arm of the Switch 36 is the same as that of the two shift registers 33 and 34 connected, which at a given point in time in its "read" -3operating position is operated. Figure 5 shows that the era of switch 3 <- supplied 32-3it PCM signal, because it is read at twice the writing speed, it is compressed in a ratio of 2: 1. Instead of the 32 3its occupy the full time interval from one scan to the next, the bits are therefore bundled, as in FIG. 5 and leave unused time intervals, each of which is half of the total interval that of the signal shown in Figure 3A is occupied. The second or!

i Comparison signal and two sets of CRC signals can be stored in \

the resulting unused intervals are inserted. '■

Figure 6 shows the CRC - encoder which can be used either as the encoder \ 23 or the encoder 27th The formwork j processing is the same for both and according to the CRC equation. "■ j G (x) = χ + χ + connected. 1 The encoder includes a signal i eingangsklerame 37 that have been obtained a Eingangskiemine an exclusive ODEE Gate 38. The output of gate 38 is connected to the D input terminal of a D flip-flop 39. The output of this flip-flop is connected to an input klerrse of a further exclusive 0D3R gate 41, the output terminal of which is connected to the D input terminal of a D flip- flop 42. The latter is connected to a sequence of two further D flip-flops 43 and 44. A clock input small 46 is connected to the clock terminals CL of all four flip-flops 39, 42, 43 and 44. The output terminal of the flip-flop 44 is connected back via a UIID gate 47 to the second input terminals of each of the exclusive -0DE2 gates 38 and 41. The

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The output ski enirie of the flip-flop Uk is connected via another ^: Ji7D gate Jf3 also to an output circuit-ie k9 . Two
Entrance gills 5oa. And 5o b are gate signal singing gills
to control the AND gates Zf 7 and ZfS, the gate circuit ZU connected to the encoder i 23 or the one with the encoder 1

27 connected gate circuit 28 form. J

The operation of the circuit in Figure 5 will be discussed in connection I.

ER- with the results shown in Figures 7A to 73 gate signals <

locates. The signals in Figures 7A and 7B are those corresponding to j

the gate circuit 2Zf supplied to v / ground while the signals;

in Figs. 7C and 7D are those associated with the gate circuit j

28 are fed.

The bundles of 32-bit PCM signals are fed to the input signal 37 of the encoder 23. V / hile the time in which this \ 32-bit signal is supplied, is the "lingangsklemne 5oA
the signal of Figure 7Λ supplied to the U.:D gate U 7 -u
open so that it is a direct connection from »output of the
Flip-flop Uh, back to the second singangsmallrae of everyone
the exclusive ODSR gates 33 and 4I act. That offsets the
Encoder 23 capable of acting as a shift register with feedback
to work according to the equation G (x) = X ^ + χ + 1, as before
in connection with the CRC code. ! laugh at the 32-3it-: interval which can be viewed as a digital word! ist.das AND gate 1 + 7 blocked to prevent further signal feedback from the output of the flip-flop ZfZf to the exclusive ODSH gates 38 and i + 1. At the same time, no further alarm signals are heard at the terminal 57
of the next four bit intervals, the gate signal of the j Figure 73 is applied to open the AND gate Jf8, and during j

this interval the flip-flops 39 and / + 2 to UU over =

discharge the output terminal l ± 9. As shown, the input

Terminal 37 is connected directly to the output k9 , so that i

during the 32-3it interval in which the UMD gate ifS!

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is locked, the one from ^ -2. Bits existing PCÜ input signal
is transmitted through the short circuit to the output ski emrr.e k9 , j The CRC pulses v / ground are sequentially added in the immediately following four sitting intervals. These 3its are in the same '. Clock read in v / ie the input signal fed to terminal 37. \, Which is also the same clock as the terminals 33 and 34R ^ i zujeführte in time compression circuit in Figure l \ read clock. 'Thus, all pulses have i at the Ausgangsklcmme + 9 -er circuit in \ Figure 6 is the same V.iederholgeschwindigkeit, and using a i 36-3it interval instead that the Sumse the two 7A and intervals shown in the figures 73 ί is. The complete ί signal is shown in Figure 33 and comprises a time-corrected ί primed 32-3it section, which corresponds to the signal in Figure 3A, and a ^ -bit section which contains the CriC signal. 'Since the signal j is designated in Figure 3A as a digital word, the signal in Figure 33 can be used as extended digital ^word designated v / ground.

The total time difference between the signal in Figure 3A
and that in Figure yz is the time required for 28 bits. V / ie
previously proposed, this interval can be filled uniformly with a 28-3it signal, which consists of 2 £ f information bits and a further ^ -Sit-CSC signal. The 2ii.-bit signal corresponds ^Cl most significant bits of the Fingangsklemne
ι 21 in Figure 2 supplied original information signal, · j and this signal is shown symbolically in Figure 3C and
comprises 12 bits for the left channel and 12 bits for the right; Channel. This is a truncation of the original signal shown in Figure 3A, but that means, in physical terms,
^: a relatively small reduction in the dynamic \ operating range of the system. Since the operating area represented by a 12-3it signal is still very good, the loss of the additional area is almost imperceptible.

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The derivation of the clipped signal from the original \

The input signal at the Singangs cycleme 21 is through the gate j

circuit 25 accomplished. This truncated signal will!

then compressed by a time compression circuit 26 identical to circuit 22 , and is actual in FIG. 3C

the compressed signal is shown. The CRC signal for the j

compressed truncated signal is in the encoder 27 and the i

Gate circuit 28 by supplying the circuit shown in FIGS. 7Z and j

7D generated gate signals to the circuit in Figure 6, j

, While the signal is below 3its with a reduced number! completely satisfactory as a comparison signal in almost all circumstances; for comparison with the primary signal, which is the signal; is at the output terminal of the gate circuit 2 / f, it is also possible to use an untrimmed or total area comparison! signal to use. That just means a compression '. in another way. For example, the time compression circuit 26 could be operated to receive a whole 32-3it signal
compressed in a ratio of 8: 3 instead of 2: 1. The bits would then have
but no longer the same repetition speed. It is
preferable to stick to the same repetition speed
and to truncate the signal passing through the gate circuit 25.

The output from the gate circuit 28, as shown in Figure, 3B is shown with the output from the gate; circuit 2if, as it is the most important bits of this ί

ι I

Represents or duplicates the signal. It can therefore be used as a comparison j signal to determine errors that occur in the 'further processing of the primary signal A., the _t

'emerges from the gate circuit 28. To better use! of the error reducing potential of the secondary signal! make, on which now as signal B. at the output terminal: the gate circuit 28 can be referred to, this j signal B. is delayed by a sufficiently large time interval that! it makes it unlikely that a signal will be transmitted

809827/092?

A. interfering signal would also affect the secondary signal B. This delay is obtained in the delay circuit 29, and a delay period of about six horizontal line intervals has been determined to be sufficient to separate the signals A. and B. resulting from the same scan information. Since the signals represent essentially the same information and thus begin essentially at the same time, it is of course necessary that the system have a sufficient delay of the secondary signals B. to place them in sequence with the primary signals A. This delay is equal to the duration of signals A. as shown in Figure 3E. Consequently, the delay for offsetting the related signals by six horizontal line intervals, which is equivalent to 18 digital locations with three digital words per line interval, should be 6h + A. If a shorter delay is sufficient, the integer 6H can be replaced by IT, where N is a composite digital location shown in Figure 3E comprising Gh bits. Indeed, Figure 3S has been marked to indicate that signal A. is part of a composite digital word with signal B...g which is related to the primary signal which occurred 18 digital words earlier. FIG. 3F shows a horizontal line interval consisting of three composite digital words, which explains the fixed delay of 18 words. Figure J> ¥ also shows the sync signal at three times the horizontal repetition frequency, which is used as word sync signals HD in the further processing of the signals.

It should be noted that, instead of the signals B ^ , the signals A. could also be delayed. It is only important that there is a separation of related signal groups, that is to say groups that originate from the same sampling interval.

809827/0927

"■■" "I.

The advantage of selecting a predetermined group of each digital word group of primary multibit digital signals A. the the secondary multibit signals B. comprises the delay of one of the signal groups relative to the other and the Combination of the delayed signal groups in nested Result with subsequent relatively undelayed signals only received when the signals modified in this way have been processed further. In this embodiment, this includes further processing is the recording of the signals as shown in Figure 3F on magnetic tape in the video tape recorder 1. As described in detail in the copending patent applications cited above, this requires additional time compression for the insertion of sync signals before the recording, furthermore the elimination of the sync signals and the Restoring the original timing of the pulses.

The decoder 12 in FIG. 1 is shown in detail in FIG. 8 and is the circuit in which the discrepancy between the signals A. and B. is used to effect an error correction. The decoder has an input terminal 51 which is connected to a decoder gate circuit 52 which separates the A. section of each compound word from the B-sig section. The A. section is fed to a delay circuit 53 which effects the same delay as the delay circuit 29 in FIG. 2 in order to bring the A, o signal into coincidence with the B. η signal. The A. "-. V signal of the Verzogerungsschaltung 53 / ill be the input of a CRC decoder 3k supplied, and the B _i _ ₁ g signal of gate circuit 52 is a similar CRC decoder 55 is supplied. The output signal from the delay circuit 53 is also fed to a gate circuit% , and the output thereof is connected to a time expansion circuit 57. Similarly, the B ^ o signal from the gate circuit

809827/092?

52 fed to a Ciat terse hai tu ng 58, and its output is i connected to a time expansion circuit 59. The exit

of the time expansion circuit 57 is via a gate circuit |

60, which truncates the signal to the same extent as the j

3rd signal was previously trimmed. The outcome of the;

Circuit 57 is also provided with an output gate circuit 61 j

tied together. In a similar way is the output of the time expan

sion circuit 59 with another input terminal of the output i

output gate circuit 61 and with a coincidence detector, or j

a comparison circuit 62, which also includes the truncated j

Signal from gate circuit 60 received. The output signals!

from the CRC decoders 54 and 55 and from the coincidence detector j

62 are fed to a logic circuit 63 to generate an output;

gate control signal which the output gate circuit 61 trains j

and generate a hold signal. !

The CRC decoders 54 and 55 are in the circuit in FIG
shown in detail in FIG. Each of these circuits is
very similar to the CRC encoder 23 shown in FIG. Of the

Decoder 54 has an input terminal 66 which receives the A. signals; supplied v / earth. This terminal is connected to one of the input terminals an exclusive OR gate 67, the output of which

is connected to the D input terminal of a D flip-flop 68. i

The output of the D flip-flop is connected to one of the input terminals j

connected to a further exclusive-OR gate 69, and its j

The output is with the D input terminal of the first of three!

successive D flip-flops 71 to 73 connected. The I.

The output of the last flip-flop 73 is directly connected to the second i input terminals of the exclusive QDäU gates 67 and 69 ^ back-

tied together. The decoder 54 also has a gate signal input i

terminal 74, which is connected to an AND gate 76,;

whose output connects to the clock signal input terminals CL of each of the!

Flip-flops 68 and 71-73 is connected. The clock signal r itself is via a clock signal input terminal 77 of the other
Input sclerame of AND gate 76 supplied. The exits

809827/0927

of the four flip-flops 68 and 71 to 73 have one thing in common sanen OR gate 79 connected, the output terminal of which is denoted by 81 i. ,

The CRC decoder 55 has an input terminal 82 which is connected to;

connected to an input terminal of an exclusive OR gate 83 '

whose output is connected to the D terminal of a D flip-flop 84 j

connected is. The output of the flip-flop Qk is with a |

An input terminal of an exclusive OR gate 86 connected, and j the output of the exclusive OR gate 86 is connected to the D input j terminal of the first of three D flip-flops 87 to 89, the j

connected in series. The output of the flip-flop 89 is |

the second input terminals of the exclusive ODSR gates 83 and '

86 connected back. A gate signal input terminal 91 is connected to a second input terminal of an AND gate 92, the other input terminal of which is connected to the clock signal input terminal 77 . The output of the AND gate 92 \ is connected to the clock terminals of each of the flip-flops 8 * t and 87 to 89
tied together. The output terminals of all four flip-flops 8 * t and

87 to 89 are connected to input terminals of an OR gate 93 ' which has an output terminal 9k.

The input signal A. applied to input terminal 66 should, j

if it does not contain an error, exactly the same as the A. signal

of the composite digital word j shown in FIG. 3E

be. This section of the digital word is 36 bits long, |

and so the gate signal shown in FIG. 10A becomes the J

Gate signal input terminal 7k supplied to open the AND gate 76 'and to allow the clock signals supplied to the input terminal 77, 36 information bits in the decoder 3k
to pulse, immediately after each word sync pulse HD, shown
in Figure 10C, beginning. If there are no errors in signal A.
are, the signal tX at the output terminal 81 is "o", if
but there is some error, the signal is "1". j

809827/0927

In a similar manner, the gate signal shown in FIG. 10B is fed to the gate signal input terminal 91 in order to enable 28 information bits to be read into the decoder 55, which begins one bit after the word sync pulse HD. If there are no errors in the B ^ signal applied to the input terminal 82, the output signal β> at the output terminal 9 * f is "o", but if errors are present, the signal R is "1". .

The signals A _1-1 Q and B ^^, which may be referred to as extended word signals since they contain CRC components, are applied to the gate circuits 56 and 58, respectively. These gating circuits only pass the basic information signals and clear the corresponding CRC signals appended to them. The signal at the output of the gate circuit

56 should therefore be exactly the first 32 bits of the symbol in FIG. 3B signal shown, and the signal at the output of the gate circuit 58 should be the one shown symbolically in Figure 3C Signals, it being assumed in each case that no error has been received in one of the information signals is·-.

The corresponding information signals freed from the CRC pulses are grounded by corresponding time expansion circuits

57 and 59 expanded again. Thus, the signal at the output of the time expansion circuit 57 should be exactly the same as the signal shown symbolically in FIG. 3A if there is no error in the processed signal. The signal at the output of the time expansion circuit 59 should be similar to the signal in Figure 3A, except that it contains a total of Zk bits instead of 32 bits.

The output signals of the time expansion circuits 57 and 59 are compared in the coincidence detector 62 for coincidence. However, since the output of the time expansion circuit 59 only contains the Zh, most important bits of the 32-bit output of

809827/0927

of the tent expansion circuit 57, this signal In the gate circuit or pruner 6o can be trimmed to clear its eight least important bits so that the two signals applied to the coincidence detector 62 contain the same number of highest order bits. These two signals must contain the same number of bits if they contain information for two stereophonic signals, since such signals contain two MSB signals, and each of these MSB signals in the primary signal must be compared with the corresponding two MSB signals in the secondary signal.

The two signals to be compared in the coincidence detector are shown in Figures 12A and 12B. The signal in Figure 12A is the secondary signal which was originally generated truncated to include only the highest order bits from M through L ^{1 of} the primary signal. Since this signal, as shown symbolically in FIG. 12A, contains only information bits and no CRC bits, it is simply referred to as signal B. The trimmed primary signal, which now has the same number of bits as the secondary signal B, is referred to as signal A ^f to distinguish it from the untrimmed or full area primary signal A. When the two signals B and A ^{coincide 1} bit by bit, the coincidence detector 62 generates an output signal jf of "1". However, if the two signals B and A ¹ do not coincide, the value of the output signal JT I ^{1 is} O ".

The entire primary signal A at the output of the time expansion circuit 57 and the truncated secondary or comparison signal B at the output of the time expansion circuit 59 are fed to separate terminals of the output gate circuit 61, which selects one of these two signals for forwarding to the output terminal 6k for further processing. The gate circuit 61 is essentially the same as a switch circuit which connects either the time expansion circuit 57 or the time expansion circuit 59 to the output terminal 6k.

«09827/0927

ORIGINAL INSPECTED

The output signals o (and β from the CRC decoders 54 and β, respectively, and the output signal f from the coincidence detector 62 are all supplied to the logic circuit 63 to generate therein signals for controlling the operation of the gate circuit 61. The logic circuit is shown in detail in FIG It has four input terminals 96 to 99 in order to receive the signals 0 (, β , IP or the 7 / locally synchronous signal HD

96 and 99 are connected to an AND gate 1o1, the output of which is connected to an inverter 1o2 and each with an input terminal connected by UIID gates 103 and 1oif. The input terminals

97 and 99 have two input terminals of a further AND gate 106 connected, the output terminal of which is connected to the other input terminal of the AND gate 1olf and the input of a Inverter 1o7 is connected.

The output terminal of the inverter 1o2 is connected to one of the input; terminals of a NAND gate I08 and one of the input terminals a second NAND gate 1o9 connected. The output terminal of AND gate I06 is with the other small input of the NAND gate 1o9 connected. The output terminals of the two NAND gates I08 and I09 are one with two input terminals third NAND gate ΙΙ0 connected.

The output parameters of the NAND gate Ho and the input terminal 98 are connected to the two input terminals of an OR gate 111 and the input terminal 98 is also connected to the input terminal of an inverter 112. The output terminal of the OR gate 111 and the input cycle 99 are with the zv / ei Input terminals of a further NAND gate 113 connected, the output terminal of which is connected to the set input of a flip-flop Π Zf connected is. The input terminal 99 connects to the reset input of this flip-flop and the reset inputs of two further flip-flops 115 and 116 as well as one of the input terminals an AND gate 117 connected.

809827/0927

The other input terminal of the AND gate 117 is connected to the output terminal of the inverter 112, and the output terminal of the AND gate 117 is connected to one of the input terminals of each of two NAND gates 118 and 119. The ·.-. >, _i output terminals of AND gates 1o3 and loif are connected to the second input terminals of NAND gates 118 and 119, respectively, and the output terminals of these NAND gates are connected to the set input of flip-flop 115 and flip-flop 116, respectively . The three flip-flops have respective output terminals 121 to 123.

The output gate circuit 61 controlled by the logic circuit 63 is shown in somewhat greater detail in FIG. 1if. She knows two input terminals 126 and 127 connected to the output terminals of the time expansion circuits 57 and 59, respectively are. In series with the leads from the input terminals 126 and 127 are electronic switches 128 and 129, respectively controlled by the flip-flops 11Zf and 115, respectively, as by the reference numerals given at the arrows near the switches.

The switches 128 and 129 are commonly connected to the input terminal of a memory 131 which has sufficient capacity to store as many signal bits as there are contained in a full primary signal A. For example, memory 131 can be a 32-bit ^L shift register. The output of the memory is connected to one pole of a pole reversal switch 132, the arm of which is connected to the output terminal 64. The other pole of switch 132 is directly connected to the output terminals of switches 128 and 129. Y / ie indicated by the arrow near the switch 132, the switching state of this switch is controlled by the flip-flop 116.

The logical relationship between the signals Oi , / ft and V- and the state of the signals transmitted from the gate circuit 61 to the output terminal 6k is in the truth table

809827/0927

compiled in FIG. '.Vhen the signal γ after comparison of a digital ^{word of the truncated primary signal A 1} with i a corresponding digital word of the secondary signal B has the value "1", the table indicates that the signal A via the switch 132 to the output terminal Eq \ is transmitted regardless of whether the signals (λ and / 2>"o" (which is likely when the, Vert of the signal V "is " 1 ") or" 1 ".

l'ienn & = ο and V * = ο, indicating that there are no errors in the primary signal A, the switch 128 is also closed and the switch 132 connects the primary signal A directly to the output terminal. This state exists regardless of whether the signal ß also has the value "o".

If, on the other hand, d = 1, which indicates that there are errors in the primary signal A, but ρ - ο, which indicates that there are no errors in the secondary signal, then switch 128 opens and switch 129 v / is closed. The switch 132 continues to route the signal directly to the output terminal 6if. The fact that this signal is the somewhat truncated secondary signal B instead of the full signal A only means that the smallest changes in amplitude represented by the least important bits are not present in the signal at J of the output terminal Gk are, but the omission of these lowest order bits in one or even more digital words is practically imperceptible.

'. If there are errors in both signals A and B, it is

0 ^ = p = 1. In such rare cases, both switches 128 and 129 are opened until the next digital word has been measured . However, instead of suddenly reducing the digital signal at the output terminal 6 * t to a zero state over a digital word interval, which could cause a negative signal with a large amplitude to be generated by the D / AV / converters 1 ^ L and 11 + R , the switch 132 is actuated to the output terminal !

809827/0927

of the memory 131 to connect to the output terminal 6k .
The memory 131 has received the V / location signal, dat; just
was passed through the switch 132, and has each .Yortsignal
replaced by the next local signal as long as one of the switches
128 or 129 was closed. When none is closed
If the memory 131 still contains the last used signal j and can discharge this signal via the switch 132 to the output j terminal Gh. That just means that for a very! the output signal remains constant for a short period of time. Against it
is less objectionable than against allowing a strong one
Change of the output signal. j

As an alternative to providing the memory 131, the switching!

i device can be designed in such a way that the supply of clock pulses to the D / A converters in FIG. 2 is interrupted for a digital input interval I when o (= β = 1 , whereby the output signal level is kept relatively constant for a short time. \

The operation of the circuit in Fig. 11 will now be described,! from which the signals for controlling the switches 128, 129 and
132 in Figure IJf.

Various points in the circuit in FIG. 11f are labeled alphabetically in order to simplify the description of the mode of operation. The three signals o <, β and r determine the operating states of the logic circuit 63 while the word sync pulses fed to the terminal 99 initiate each operation. That is, only if a word sync signal pulse of the 'input terminals 99 and from there the reset terminals of the flip-flops 11 / ». to 116 is supplied, the output terminals
121 to 123 are forced to assume the values determined by the logical "o" or "1" values of the signals c ( , A and r.

809827/0927

If the truncated primary signal Λ 'in the coincidence detector 62 exactly corresponds to the secondary signal B and the signal ψ becomes - 1 as a result, the signal point g at the output of the OR gate 111 has the value "]", regardless of what the output value of the NAND gate 11 o is. Consequently, the node h at the output of the NAND gate 113 and at the set input of the flip-flop 11Zf is also at "1" until the Y / ortsynchronsignale fed to the other input terminal of the NAND gate 113 this Singangsklemme to V / ert "1 "raise, whereby the output signal at the node h for the duration of the» pre-sync pulse drops to "o". That causes! the output terminal 121 assumes the value "1". As before- \

is set, this closes the switch 12o in Figure Hf and causes the switch 132 to conduct the full signal A to the output terminal Gh . >

In the mentioned state, in which VT = 1, the inverter 112 inverts this to the value “o”, thus disables the AND gate 117 and holds the node m at “o”. This prevents both NAND gates 118 and 119 from responding to a word sync pulse for setting flip-floos 11p and 116. As a result, both output terminals 122 and 123 have "ο". _;

Jenn Ϋ = ο, this indicates that there ^{is an error in either the truncated primary signal A 1} or in the secondary signal B which is compared with it. If it is assumed that the error is in the secondary signal B, the signal P>'has the value ¹¹ I "and the signal tX has the value" o ". Consequently, the node a has the * 7ert" o ". and the potential at deta circuit point b at the output of AND gate Io6 corresponds to: the V / local synchronous signal fed to input terminal 99. Inverter 1 o2 inverts the value "o" at circuit point a to the value "1" at the circuit point c. The inverter Io7 inverts the V / ortsynchronpuLssignal at the circuit point b and feeds this inverted synchronous pulse to the NAND gate

809827/0927

1o3 to. The states of the circuit points c and d have the effect that the output of the KAND gate 1o3 at the circuit point e follows the V / local synchronous pulse. At the same time, the states of the switching points b and c at the input circuits of the iAND gate 109 have the effect that the output of this NMD gate (f) is the inverse of the Yv'ortsynchronpulssignal and therefore opposite to the signal at the point e at all times. Therefore one or the other input terminal of the HAND gate I1o is always on the V.'ert "o", and consequently the output terminal of this liAND gate is always on "1" as a result of these input states. This causes the output of the ODSR gate 111 to follow the NAND gate 11o and to assume the value "1" at the node g. This represents the same state that prevailed when the value of the signal γ was "1", and the output ^{terminal 1} Zl of the flip-flop 11 if is therefore at the value "1" and causes the switch 123 in FIG. 1 to close / f so that the signal A is transmitted to the output terminal 6k.

Since the signal of the AND gate at point a is "ο", both AND gates 1o3 and ^ ok have the value "o" at their output terminals, and consequently also nodes i and j. These states hold the output values of the NAND gates 118 and 119 at points k and 1 at ¹¹ I ", so that the output terminals 122 and 123 of the flip-flops 115 and 116 remain at" 0 "and the switches 129 and hold 132 in Figure 1if in the states shown.

The condition just described in detail, in the o (= ^ο: ο Ϋ = and / 3 = 1, state II is W3 / mean in the following table, in which WS the V / ortsynchronpuls and the inverted V ortsynchronpuls the previous one. State with P "= 1 is! State V in the table. '

If there is an error in the primary signal A, but none in |

the secondary signal B, the value is 0 ("1" and the value:

from f> "o". The value of y is "o". This is state III in '

of the table and does not need to be described in words. j

809827/0927

; Switching points

Tabel

States II III IV

96 (input) 0 0 1 1 1 97 (input) 0 1 0 1 99 (input) O O O O a 0 0 WS WS b 0 WS O WS C. 1 1 Ws Ws d 1 WS 1 WS e 0 WS WS WS 1 f 1 Ws 1 1 G 1 1 WS Ws H Ws Ws 1 1 i 0 O WS O 1 C-J. 0 O 0 WS 1 k 1 1 WS 1 O 1 1 1 1 Ws 1 m WS WS WS WS α 121 1 1 0 α 0 122 0 0 1 O 123 O Q 0 1

If the primary signal A and the secondary signal B have errors , so that <x = β = 1 and f = ο, the logic circuit operates according to state IV in the table and, as previously described, causes switch 132, in FIG. Ii +, fetch a replacement from memory 131. As a result, three signals are available at the output terminal Gk without delay: signal A as the first choice, signal B as the second choice and the signal stored in the memory 131 as the third choice.

809827/0927

- / fl -

State I represents a state in which the analysis
of the CRC code in each of the decoders 5 * f and 55 indicates that
there is no error in either signal A or signal B,
so that OC = / 5 = ο. The statement / = ο means, however,
that the most important bits of the two signals do not coincide, J so that at least one of them must have an error. j This requires that the error be of such a nature that it causes a! exact shift of the information signal or the CRC signal and the information signal to a new Y / ert ' , which is considered to be a permissible and therefore correct value
is decoded. The occurrence of such a situation is; possible, but has a very low probability.
The logic circuit 63 is designed so that in this
State the primary signal A to pass through the output; gate circuit 61 to output terminal 6if selects. I.

Figure 15A shows the effect of the invention in overcoming
an impulsive noise that extends over three composite digital words that make up the primary signals
A. to A. ₊ 2 and the secondary signals B. .. g to B. .. r grouped in this interval. As indicated in FIG. 3F, this is a horizontal line interval.

As shown in Figure 153, the logic circuit 63 can »after:

the compound word signals separated and the error-free '

primary signals A ^ jο to A ^ _ ^ c with the faulty second!

The signals B _1- ^ g to B ^^ c have been brought together in the same time interval, select the error-free primary signals for further processing with ease,

for example in the serial / parallel converter 13 and above j

out. I.

809827/0927

In the same way, if the erroneous signals A.

to A. -z with the related error-free secondary signals

B. to B. ₊ , have been brought into the same time interval, the logic circuit 63 easily select the error-free secondary signals for further processing. In this way J the advantage of the invention is obtained.

na / old

809827/0927

Claims (1)

7-351: Citashinagav / a 6-chome Shi nagav / a- ku Cokio / Japan Expectations: N. ) Method for error reduction in the processing of first multibit digital signals, which are grouped into Digitalv / ort groups, characterized in that from each> r Digitalv / ortgruppe (A) in the first multibit digital signals a secondary group (3) of second Mulcibit digital signals are selected, whereby each digital / location group (Λ) and its secondary group (ß; consist of related signal groups that one of the groups (A or B) is delayed relative to the other group (3 or A) and that the delayed signal groups are combined in an interleaved sequence (FIGS. 3S and 3F) with subsequent undelayed signal groups to form combined sequential signals. 2. The method according to claim 1, characterized in that when selecting a secondary group (B) only a part (bits M to L, Figure 3C) of the digital signals of each digital word group (A) is selected. 3. The method according to claim 1, characterized in that the secondary group (ΰ) relative to the digitaiv / ortgruppe (A) is delayed in each of the signal groups used. 809827/0927 . '■ _r . Ancestors according to. \ Nspruch 1, with don the Ai.jital signals' from pulscodeuoclulier ten OCA-J I! All iblt-oigna.Ler. t.; it is a series (M to L) from .jits of higher to ^ its lower order: between an .important tone bit O) and an a; .i at least important 3i'c (L) exist, characterized that a large number of Aits of higher purity (Γ. to L ') from the PCIi signals are selected as the second I-'ultibit-Sign-xle J. 5. Procedure according to. '. Nspruch l \, ci by ^ el: o.; P ^ oichne t that all l -'. Ultibit-5Lf; nale temporal Uonpri;: iiort v / earth. 6. Procedure according to. Claim h, characterized. ;; oke: Tn ^ yichnei '., That the first (M to L) and the second (■.'. To L ¹ ) multibit signals separately in time l: omjrxr .-. Ior. before the delayed signal groups (ß) r.i with the relatively unchanged signal groups (Λ) are conjugated. 7. The method according to claim 6, characterized jekenuzoichnet that a group of first cyclical iiedundanzjrüi'code- (üAG) -. 'Ji _; 'jnalo (CRC in Figure 3 ^) Clen time L I kor.iprinierten deferrers ^ jarten Signalgruppsn O) and a group of second C ^ C-Si / jnale ((JICC in Figure 3B) the seitkonprinierten relatively unverzö _(Erten Sifsnalgruppen (A ) must be added before the time-corrprimiercon delayed signal groups and the zeitkonprinierteu relatively undelayed signal groups are combined. 8. The method according to claim 7 »characterized by that ^! the delay of one of the signal groups the delay of this '' iruportn by the ^{time span occupied by one of} the time co.r.priuiorten relatively u.i7e · "- delayed signal groups (; V) and the time span occupied by the j first CRC signals for these ( A) occupied additional time span, plus an integer multiple (Ii) of a full interval consisting of a complete set of the time-coded delayed signals O) and the time-coded relatively undelayed signals (A. ) so / le of the first and the ■ second UAC-3igna.Le be laid, where II - ο.; / 09 ?? ^e *> or, _GiNa 9. The method according to claim 3, characterized in that _: all time-configured signals in the ratio 2: 1 compressed v / ground. 10. The method according to claim 7, characterized in that each of the first CKC signals has P bits that are each time co-ordinated immediately follow the delayed signal group, and that each group of the second CSC signals includes P Bibs, that of each time-compressed, relatively undelayed signal group follow immediately. 11. The method according to claim lo, characterized in that the total number of bits in each secondary group (3) is 2P less than the total number of bits in each digital location group (λ). 12. The method according to claim 11, characterized in that the number of bits in each digital word group (λ)} Z is 3 bits, the number is 3 bits in each secondary group Zk and the total number of CBC signals is c. 13. The method according to claim 1, characterized in that the first multibit signals (A) and the zv / eicen ΐ IuI iibit signals (B) are compressed in time before they are combined, and that the combined signals (for example in one Video tape recorder) and the processed signals are expanded back to their original duration. \ 1 ^. Method according to Claim 13, characterized in that the processed signals G-.) Are selectively delayed in order to restore the original time relationship between the extended first and second multibit signals (A and 2) place. i ßO98? 7 / O9 ?? 1 5 · Ancestors .uv error minimization into a:.: Composite 'signal comprising groups of first multi-bit digit word signals I which are nested with groups consisting of two multi-bit digital input signals, each of which one predetermined secondary group is one of the first digital / location signals, each signal being one of the groups versus the signals
nor other. Group is delayed, and where the aggregate-; ootzce signal has a large number of first, very large number of criC binary signals, each of which relates to one of the digital / location signals and follows a group of first digital signals and the next group of second digital signals
precedes, and also has a multiplicity of two-digit j CRC binary signals, each of which relates to one of the! Groups of second Digi'.aloi. ^ Nalen relates and a group
of second Uigita signals follows and the next group
first Digi'.alsi -.-- ialo precedes, characterized in that
(iie delayed and relatively undelayed signals (Λ, Β)
be compared and for ./ more diligent processing that
(Λ or; 5) of the compared signals selected v / ird that a
MininuM of errors υ. 16. The method according to claim 1 ^, characterized in that
the selected signal until the time of the next comparison
is saved and the saved signal is sent again
further processing is selected if said _to: time, none of the compared signals (A or B) is error-free '. · 17. The method according to claim 15 _f, characterized in that ι when selecting that signal that has a minimum of errors! has, in the case of the accuracy of both compared
Signals (A ₁ B) the first digital word (A) is selected. 8098 27/092? 18. Device for processing a primary Kultibit digital signal, characterized by a first device (21) for receiving the primary signal in the device, by a second device (25) for generating a secondary multibit digital signal (B), the v / at least the higher order MIs of the primary signal by a delay circuit (29) connected to the first (21) or the two (25) devices for delaying the signal relative to the: n signal in the other of the two devices ( ^;: 1, 25) by a predetermined Zv / itspanne, and by using the deferrers _o erungsschaltung (29) and the other of the two devices (21,25) gate circuit connected (3 °) ^ ^for alternating passage of the delayed signal and the signal in the other of the two bodies (21.25). 19 · device according to claim 1 ^; '>, characterized by Zeitk_ompressionsschaltungen (22,26), which are connected to the eraten (21) or the second (25) device, /. to reduce the duration of each primary (Λ.) and sekiuidaron (_'>) Signals. 20. Apparatus according to claim 19, characterized in that that the time compression circuit (22,2G) is a Lünrxchtuni; (32,33,3 ^) to receive the multibit signals at an input bit repetition rate and to save the received Bits and means (33,3'f, 36) for extracting the Includes bits with a higher bit repetition rate, dividing the multibit signals into spaced apart groups of signals be separated with higher repetition speed. 21. The device according to claim 2o, characterized in that each time compression circuit (22,26) the duration of the corresponding primary and secondary signals compressed in a ratio of 2: 1. 809827/0927 22. Execution according to claim 1 3, rekennze backrest '.. by a first .'inriehtung (21) connected to the first compression circuit (22) zuu 2npfan ;; en and storage of a vrinärtm signal (A) with a speed and zu.i Extracting the primary signal from the storage in first time-spaced groups at a higher rate by one with the second device; ¹ , (25) connected second time pressure circuit /; (26) ζιιπ: i.ipfangen and storing the secondary signal (3) i tit the one speed and ζkm extracting the secondary signal from the storage in second time-spaced groups with the higher speed and through with the first (22) or the second (Za) time compression circuit connected gate circuit ^ :! (2 / ' _Γ , 2ό) to extract the groups of the primary signal alternately r; it the groups of the secondary signal. first 23. Device nael ·. Claim 22, characterized by a V Li it the first rliurichLun ;; (21) for Auf nehrxM: the pr signal (A) connected CRG-i-loilieror (Zj) for generating a first check code signal (CRC in Λ ..) based on each of the first signal groups by one with the second . ^; ; inrichtung (25) second CRC coder (27) connected for receiving the secondary signal (G) for T] rzeugun _t ^f ·; a second check code signal (CRC in B.) based on the secondary signal groups, and through gate circuits (2 ^, 23) associated with the corresponding time compression circuit ^{; i} ; (22,26) and the corresponding C; C encoder (23,2?) Are connected, ura one after the other according to an interval of predetermined noise, one interval before the primary signal (A). i; j ujj jrston Jrüicoaasignals (CRC), an interval of predetermined i ", length ac ^ secondary signal (3) and an interval vorgo ::: office i, än ;; o eoi; second test code signals (CRC) as ei. : i Z! is: i: ".:. u; 'ir-; üivj tztes Dl'; italv / ortsignal to be transmitted. 809Ö27 / 092? Ph. Device according to claim 2 ^ _1, characterized by a Jekooier gate circuit (52) for separating each interval de :; primary signal (A.) and each interval of the first test code signal (CRC in A.) of each interval of the secondary signal (3 ^ _, _ο ) and each interval of the second test code signal (CRC in 3., π), by one with the Dekodierga .terschaltung 1 IO (52) connected first CRC decoder (3k) for λ decoding of the primary and the first test code signal (A-) and for the generation of a first logic signal (A) , the value of which indicates the presence of an error in the primary signal section (A) of the digital word signal is based by a second CRC decoder (55) connected to the decoding gate circuit (52) for decoding the secondary and the second test code signal (13. _. ^ and for generating a second logic signal (fi) whose!. Vert on your presence of an error in your 'secondary signal abscimitt (3) of the digital word signal glazed, and through a switching device (123,129,132) that nxl the first (54) and the z.veicen (55) decoder and with an output sticker ..'. 2 (6-Ί-) and is controlled by the first ( (X) and the second ( β) logic signal to either -las primary (Λ) or the secondary (3) signal to the output terminals (6 '+) to switch through. 25 · Device for processing a digital signal (Figure 3 ^), which is divided into composite digital word sections (A- and 3 ._ .. q), the first digital word section (A.) ^: a primary digital word (A) and a first 1 -check code signal (CRC in A.) for the first digital location (A), and the. second digital word section (3 .., <-,) a secondary digi; alv / jr; (3), das i .-. I information inalt. ^. It ii.;: «;.] p ^ i ^ aror. üigitciwort (A in A ._, p) imengesetzten in one occurring at a different time in the "Digital Signal different zusa, digital word portion is used, and a second Prüfcodesigna L (CWC in 3., o) for RIAS secondary DigitalV / ort, : gokc-üiizeichnet by a source (51) of the Digi alsignals, ;; ine walilvioise nit >} ■ ;? inolle (51) connected 809827/092? BATH ORIGINAL Delay circuit (53) ι which is used to each secondary; Digital word (3 in 3., o) and the primary digital word (A in Α._, _ο ), which is essentially used in the information content, in temporal coincidence, and by means of a delay circuit (53) and the source (51 ) connected comparison circuit (S2) for comparing each secondary digital word (3 in B ^, n) with the primary digital location (A in A .., <■,) and for the production J- IO generation of a logic signal (y) having a predetermined value when at least predetermined portions of the compared digital signals are identical. 26. The device according to claim 25, characterized in that the secondary digital word (B) only has higher order bits (K-L ') of the primary digital word (A) related to this in the information content, and that the device has a trimming device (6o) for trimming each primary digital word (A) in order ^{to bring it into agreement with the bit orders (ML 1} ) in the secondary digital word (B), the corresponding bit orders comprising the predetermined section. 27. The device according to claim 2. ^ ₁ characterized by ^: a switch connected to the comparison circuit (62) ; direction (128,129,132) to select the primary digital j signals (A) if the compared signals (A 'and B) are identical j are. 28. The device according to claim 27, characterized by a , decoder (54) connected to the source (51) for generating a second logic signal (D () which has a predetermined Y / ert (o) when the primary digital word (A) is error-free , and by a logic circuit (63 ), which is connected to the decoder (5k) and to the switching device (128,129,132) which is to be actuated by the second logic signal ( o () in order to select the primary digital word (A) if it is error-free. 6Ö9 8 2 7/09 2? 29. The device according to claim 28, characterized in that the delay circuit (53) between the source (51) and the decoder (5A-) is connected in series. 30. The device according to claim 28, characterized by a second decoder (55) connected to the source (51) for generating a third logic signal ( B ) which has a predetermined value (o) when the secondary digital word (B) is error-free, wherein the logic circuit (63) is connected to the second decoder (55) in order to cause the actuation of a switch (129) of the switching device (128,129,132) by the third logic signal (yö) and to select the second digital word (B) if the primary digital word (A) has an error and the secondary digital word (B) is error-free. 31. The device according to claim 3o, characterized by a memory (131) for storing and repeating a previously selected digital word, v / obei the logic circuit is responsive to the first-mentioned, the second and the third logic signal in order to activate a switch (132) of the switching device ( 128, 129, 132) to select the previously selected digital word when errors occur in the primary and secondary digital words that control the generation of the second () and third (ß) logic signals. 80§827 / 092?