DE2752742A1 - Cascade circuit for UHF amplifier - has N-channel MISFET connected by drain to emitter of series bipolar NPN transistor - Google Patents

Abstract

The cascade circuit, for UHF amplifiers, has an FET connected by its drain to the emitter of a series bipolar transistor. The FET is an N-channel MIS type and the bipolar transistor an npn type. The two transistors are integrated onto one s-c chip or into a hybrid circuit. The advantage lies in the circuit's being controllable over a wide range, in having low output capacitance, high reverse voltage, high operating frequency and high input impedance.

Description

Cascade connection of two transistors connected in series

The invention relates to a cascade circuit comprising two series-connected Transistors for preferably UHP1 amplifiers.

There is already a cascade circuit in the form of a MOS-FET tetrode, in which two MOS field effect transistors are connected in series.

Such a conventional MOS-FET tetrode is shown in FIG. On a p-conductive substrate 1, for example, there is a p-conductive epitaxial Layer 2, in which n-conductive zones 3, 4, 5, 6 and 7 are provided. Zones 3 and 4 serve as the source of the first field effect transistor. Zone 5 serves as a drain of the first field effect transistor and at the same time as the source of the second field effect transistor. The zones 6 and 7 serve as the drain of the second field effect transistor. On the zone 3, a source electrode S is provided, which on the one hand via a line 12 with the substrate 1 and on the other hand to a terminal 8 is connected. Over a canal 13 between the zone 4 and the zone 5 is a gate electrode G1, the with one connection 9 is veztunden. There is also a channel 14 between the zone 5 and the zone 6 have a gate electrode G2, which is connected to a terminal 10 is. Finally, a Draln-Zloktrodo D is provided above zone 7, which is connected to a terminal 11.

When this MOS-FET tetrode is operated, a space charge zone is formed 16 leading to capacities 17, 18 between zone 5 and layer 2 respectively between the zone 6, 7 and the layer 2 leads.

The current controlled by the gate electrode G1 flows across the zone 5, the drain for transistor I and source for transistor II at the same time represents, via the channel 14 into the drain zone 6, 7.

This MOS-FET tetrode works because of the considerably high input impedance of the transistor II with increasing frequency a considerable current share as parallel leakage current lost from zone 5 to substrate 1. Because of the low steepness of the characteristic of transistor II is at multiplicative / mixing (as a "multiplicative" mixing circuit a circuit with an oscillator at the gate electrode G2 is called what in principle means a circuit with drain modulation for the transistor I) or in the case of regulation via the gate electrode G2, a high control voltage swing is required; in addition, control potentials are outside the operating potentials in normal operation at the drain electrode D and at the source electrode S required.

The output capacitance of the MOS-FET tetrode is due to the large area required for the drain zone 7 and for the contact surface of the drain electrode D for practical Applications in the UHF area too large and about a factor of 2 larger than with bipolar transistors. Finally, the channel length of the channel 14 under the gate electrode G2 can also be selected Blocking voltage reasons cannot be shortened arbitrarily.

It is therefore an object of the invention to provide a cascade circuit of the initially mentioned named type with high gain, large control range and high control steepness specify which is fully controllable within the operating potential for the circuit, which have a low output capacitance, a high reverse voltage, a high working frequency and has a high input resistance for AC voltage, and in particular For VHF and UHF amplifiers with a high mixer slope and low oscillator voltage requirement suitable is.

This object is achieved in that the drain of a Field effect transistor interconnected with the emitter of a bipolar transistor is.

The low-resistance input impedance of the bipolar transistor is almost compelling the entire current flow from the channel of the field effect transistor into the emitter of the Bipolar transistor. This is the capacitive shunt of zone 5 to the substrate 1 and to layer 2 practically ineffective.

The steepness of the regulation is due to the steepness of the bipolar transistor about a factor of 3 improved, which means that the 'requirements for a local oscillator reduced in terms of voltage amplitude and thus among other things the interference radiation problems be defused.

The regulation is carried out with an extremely small spread of the base voltage; full curtailment is already within the operating voltage range with collector voltage / source voltage achieved.

With the smaller-area bipolar transistor, the output capacitance reduced, which is especially true for multichip integration.

The HF and IF output impedance is much higher than for for UlIF behavior specially optimized field transistor cascades.

With the bipolar transistor, the reverse voltage problems are separated, which is otherwise closely related to the RF properties of an XOS field effect transistor the short canal lengths are linked.

Finally, in the cascade circuit according to the invention, the Maintain favorable distortion and noise properties of the field effect transistor.

The invention is explained in more detail below with reference to the drawing. The figures show: FIG. 1 a section through a conventional MOS-FET tetrode, FIG. 2 a circuit diagram of the cascade circuit according to the invention, FIG. 3 a section through an embodiment of the invention, Fig. 4 is a circuit diagram of the invention Cascade circuit with input phase reversal, Fig. 5 characteristic curves to explain the 4 and FIG. 6 signals for explaining the operation of the embodiment of FIG. 4.

In Fig. 2 is an N-channel MIS field effect transistor 20 with its drain electrode D is connected to the emitter E of an NPN bipolar transistor 21. The entrance this circuit forms the gate electrode D of the field effect transistor 20, while the output at the collector K of the bipolar transistor 21 is provided.

Control signals are applied to the base B of the bipolar transistor 21 and at the gate electrode G of the field effect transistor 20.

With this cascade circuit according to the invention from the field effect transistor 20 and the bipolar transistor 21 are while maintaining the favorable distortion properties of the field effect transistor 20, the high-frequency properties, the mixing slope and gain as well as the output capacitance and the dielectric strength compared to the conventional MOS-FET tetrode improved.

In the case of the invention, a field effect transistor is used in a source circuit and a bipolar transistor connected together in a basic connection to form a cascade. This interconnection can take the form of a hybrid module or monolithic integration take place.

3 now shows an example of an integrated cascade circuit according to the teaching of the invention. Corresponding parts are shown in FIG. 3 the same reference numerals are used as in FIG. 1.

In the left part of Fig. 3, the field effect transistor 20 is shown, while the right part of FIG. 3 shows the bipolar transistor 21. The field effect transistor 20 consists of the n + -conducting source zone 3, the n -conducting zone 4, the n + -conducting Source zone 7 and the n-conductive zone 6 in the p-conductive layer 2. Between the zones 4 and 6 is formed under the gate electrode G with the gate terminal 25 the channel 13. On the zone 3 is the source electrode S with the source connection 26 provided. On the drain zone 7 is the drain electrode D with the drain connection 27 provided.

The bipolar transistor 21 consists of an n + -type buried Layer (buried layer) 30 with an n + -conductive contact connection zone 31, from a n-conductive zone 32, from a p-conductive zone 33 and from an n + -conductive zone 34. The zones 30, 31 and 32 form the collector zone of the bipolar transistor 21.

The zone 33 forms the base zone of the bipolar transistor 21. The zone 34 forms the emitter zone of the bipolar transistor 21. On the zone 34 is an emitter electrode E with an emitter terminal 35 is provided. On the zone 33 is a base electrode B with the base connection 36 is provided. The collector electrode is on zone 31 K is provided with the collector connection 37.

The terminals 27 and 35 of the drain electrode D and the Emitter electrodes E are connected by a line 38.

This line 38 can optionally also directly on the insulation layer over the surface of the layer 2 or the zones embedded in it be led as a conductor track.

The individual zones in layer 2 or in the semiconductor substrate 1 for the field effect transistor 20 and the bipolar transistor 21 can by diffusion or made by ion implantation.

Fig. 4 shows a modification of the embodiment of FIG Input phase reversal. A bias current I, for example through an integrated Current source 40 or a resistor is generated, controls the drain potential of the Field effect transistor 20 via the potential at the base electrode B of the bipolar transistor 21 so that the field effect transistor working as an input transistor 20 inversely is operated. This means that the input signal can be used during the entire control period, for example an oscillator. It will be such an increase the mixer gain by 3 dB.

5 shows the dependence of the drain current ID on the collector voltage UK with the gate voltage UG as a parameter. The difference UM'TUBE (UBE = base-emitter voltage of the bipolar transistor 21) is shown in FIG. 5 by lines 51, 52. At the bottom The signal curve UB-UBE is plotted in part of FIG. 5.

Fig. 6 a shows the course of the control voltage Ust or the base voltage U3 at the base electrode of the bipolar transistor 21.

Fig. 6 b shows the profile of the input voltage UE or the gate voltage UG at the gate electrode G of the field effect transistor 20. Fig. 6c finally shows the profile of the output current IA at the collector K of the bipolar transistor 21.

The disturbing influence of the substrate potential of the semiconductor substrate 1 on the steepness of field effect transistors, in particular MIS field effect transistors, which occurs particularly in the embodiment of FIG. 4, but also in MIS tetrodes can be effective by using a high-resistance carrier material for the substrate 1, such as sapphire or semi-insulating semiconductor material.

9 claims 6 figures

Claims (9)

Cascade circuit consisting of two series-connected transistors for preferably UHF amplifiers, d a Bu r c h g e k e n n -z e i c h n o t that Drain (D) of a field effect transistor (20) with the emitter (E) of a bipolar transistor (21) is interconnected (Fig. 2). 2. Cascade circuit according to claim 1, characterized in that the Feldeffekttransi stor is an N-channel MlS field effect transistor, and that the bipolar transistor (21) is an NPN bipolar transistor. 3. Cascade circuit according to claim 1 or 2, characterized in that that drain (D) of the field effect transistor (20) with emitter (E) of the bipolar transistor (21) are interconnected (Fig. 2). 4. Cascade circuit according to one of claims 1 to 3, characterized in that that the field effect transistor (20) and the bipolar transistor (21) are integrated in one Circuit are summarized (Fig. 3). 5. Cascade circuit according to one of claims 1 to 3, characterized in that that the interconnection of the field transistor (20) with the bipolar transistor (21) takes place in a hybrid module. 6. Cascade circuit according to one of Claims 1 to 4, characterized in that that the interconnection of the field effect transistor (20) with the bipolar transistor (21) by a conductor track guided directly on the surface of the integrated circuit (compare 38) takes place (Fig. 3). 7. Cascade circuit according to one of claims 1 to 6, characterized in that that as the connection point of the field effect transistor (20) with the Bipolar transistor (21) has a bias current (I), so that the drain potential of the field effect transistor (20) reversible and the field effect transistor (20) can be operated inversely. 8. Cascade circuit according to one of claims 1 to 7, characterized in that that the field effect transistor (20) and the bipolar transistor (21) on a high resistance Carrier material are arranged as a substrate (1). 9. cascade circuit according to claim 8, characterized in that the The carrier material is sapphire or semi-insulating semiconductor material.