DE2746642C2 - Television pulse generator - Google Patents

Description

45

State of the art

The invention is based on a television pulse generator according to the preamble of the main claim. Such a Television pulse generator is for example from October 1973 from the company National Semiconductor Corp. published publication for an integrated module with the type designation MM 4320 / MM 5320 known and in IEEE Transactions on Broadcast and Television Receivers BTR-18,1972, issue 4, pages 128 to 133.

In the known television pulse generator, each pulse signal is in its own logic combination unit derived. However, since logical linking units are very circuit-intensive and also fixed are wired, such television pulse generators are usually only for very specific television standards designed and deployable.

The object of the present invention is to provide a television pulse generator of the type mentioned at the beginning indicate which less circuit-intensive and with little modification measures also in television systems other television standard can be used

Advantages of the invention

The television pulse generator according to the invention with the characterizing features of the main claim the advantage that the circuit complexity can be considerably reduced by using a memory can. By simply programming the memory, all required in a television system can be found Generate television pulses in any desired frequency and temporal coupling with one another.

The measures listed in the subclaims are advantageous developments and Improvements to the television pulse generator specified in the main claim are possible. It is particularly advantageous that by using two counters the television pulse generator according to the invention not only external synchronization can be made, but through the associated division of storage capacity can be saved.

drawing

Further advantages and details of the invention are given below with an exemplary embodiment in FIG the drawing described with figures. From the figures shows

F i g. 1 tin block diagram according to the invention,
F i g. 2 and 3 voltage timing diagrams to explain the block diagram.

Description of the embodiment

In the block diagram of FIG. 1, a clock signal is fed to the clock input C of a counter 2 via a terminal 1. The counter 2 can be reset by an externally supplied horizontal-frequency pulse signal at a terminal 3.

The binary values obtained depending on the count at the output of counter 2 are fed in parallel as addresses to the address inputs of a read-only memory 4. At the output of the read-only memory 4, according to its programming , _{a horizontal pulse signal H can be} picked up at a terminal 5, a horizontal-frequency blanking signal A H at a terminal 6, a burst identification pulse signal Kh at a terminal 7 and a pulse signal of double horizontal frequency at a terminal 8. An auxiliary pulse signal Z, described in more detail below, is passed on from a further output of the read-only memory 4 to the clock input C of a second counter 9. The counter 9 can be reset by a vertical-frequency pulse signal V applied to a terminal 10. As, in the first counter 2 also in the second counter 9, the binary values resulting depending on the counter status at the output in parallel form to the address inputs of another read-only memory 11 is supplied as addresses when suitably programmed, is connected to an output terminal 12, a vertical synchronizing signal V, on a terminal 13 a vertical rate blanking signal Av, and at a terminal 14, a synchronizing signal S removable. The address at the address inputs of the further read-only memory 11 can be extended by a pulse signal at a terminal 15 of half the vertical frequency.

The mode of operation of the block diagram in FIG. 1 and the time assignment of the in this block diagram mentioned pulse signals is based on the following

of the voltage timing diagrams shown in FIGS explained.

It is assumed that the pulse generator is externally synchronized according to the present embodiment will. For a horizontal synchronization, the counter 2 via the terminal 3 is a pulse signal according to the 2a. This pulse signal has a pulse repetition frequency for a television standard of 625 lines of 15.625 kHz. The pulse width of the reset signal is one cycle duration of the one at terminal 1 lying clock signal. This clock signal (FIG. 2b) should be a whole-line multiple of that at terminal 3 lying horizontal pulse signal be frequency-coupled. In FIG. 2g to 21 are some of the parallel to the Binary signals lying at the counter outputs are shown. The binary signals of FIG. 2g to 21 are regarding their Ordered weighting. In the present exemplary embodiment, FIG. 2g a binary signal with the lowest value (LSB) and Fig. 21 a binary signal with the highest value (MSB), in The dependency of the binary value currently present in the counter status is shown at the output of the Read-only memory 4 either ei, i Sgral according to FIG. 2c (Horizontal synchronizing signal), a signal according to FIG. 2d (horizontal blanking signal), a signal according to FIG. 2e (Burst identification pulse signal) and / or a signal according to FIG. 2f (pulse signal with double horizontal frequency) tapped. A read-only memory (ROM) or a programmable one can be used as read-only memory Use read-only memory (PROM). Depending on the address at the address inputs Depending on the programming, either a logical H or a logical L is output. The width the pulses contained in the output pulse signals are therefore different from those present in each case Addresses set. The accuracy of the time allocation depends solely on the level of the frequency of the clock signal applied to terminal 1.

While the read-only memory 4 is used to derive essentially horizontal-frequency pulse signals and pulse signals with multiples of the horizontal frequency, the read-only memory 11 generates vertical-frequency pulse signals or pulse signals with vertical-frequency signal components. To save storage capacity in the read-only memory 11, a special address sequence is generated from the auxiliary pulse signal Z in the counter 9. The auxiliary pulse signal Z is generated simultaneously with the other pulse signals derived in the read-only memory 4. 3d shows two horizontal periods H of the auxiliary pulse signal Z. The timing of the pulses per horizontal period in the auxiliary pulse signal Z depends on the respective position of positive and negative edges of the pulses in the vertical blanking gaps of a standard synchronous signal. F i g. 3a shows the vertical blanking interval of a first partial image and FIG. 3b shows the vertical blanking interval of a second field in a standard synchronous signal. For every possible pulse edge change in the synchronizing signal, a pulse is set in the auxiliary pulse signal Z of FIG. 3c. The auxiliary pulse signal Z shown in FIG. 3d with a smaller time scale contains pulses everywhere at the times of which the edges of the vertical component of the synchronizing pulse are in the first and in the second field. An address change takes place when using such an auxiliary pulse signal as a clock signal for the counter 9 ηιτ in the moments in which, according to the television standard, a level change from H to L or from L to H in the synchronous signal could take place. External synchronization is carried out by applying an externally supplied vertical synchronous signal to terminal 10. For field-correct external synchronization, terminal 15 is supplied with a pulse signal of half the vertical frequency.

By changing the program in the read-only memories 4 and 11, you can also easily Generate television pulse signals of a different television standard.

For this purpose 2 sheets of drawings

Claims (5)

Patent claims: 1. TV pulse generator, in which a first counter for counting the horizontal frequency coupled clock signal and a first code converter are provided, and the first code converter generates the horizontal frequency pulse signals necessary for the operation of the television system depending on the addresses generated by the first counter a second counter and a second code converter are also provided, the second code converter generating the vertical-frequency pulse signals necessary for the operation of the television systems as a function of the addresses generated by the second counter, characterized in that one of the first code converter ( 4) generated auxiliary pulse signal (Z) is fed to the second counter (9j) 2. television pulse generator according to claim 1, characterized in that read-only memory as a code converter ([P] ROM) can be used. 3. television pulse generator according to claim 1, characterized in that for external synchronization of the Television system the first counter (2) horizontal frequency and the second counter (9) vertical frequency is synchronizable. 4. television pulse generator according to claim 1, characterized in that the second counter (9) address obtained by binary values of an externally supplied pulse signal of half the vertical frequency is expandable. 5. television pulse generator according to claim 2, characterized in that the auxiliary pulse signal (Z) is coupled to an integer multiple of the horizontal frequency (H) that the number and the timing of the pulses in the auxiliary pulse signal (Z) during a horizontal period (H) by programming of the first read-only memory (4) is determined so that each pulse edge of the pulses in a television sync signal during each horizontal period can be assigned a pulse in the auxiliary pulse signal.