DE2743492C2 - - Google Patents

Description

The invention relates to a Control processor that works both as a numerical controller for a controlled machine tool workpiece programs executes as well as a programmable control unit ar that works the condition of individual, controlled works witness machine associated digital scanning devices senses and individual, the controlled machine tool actuated assigned digital work devices, according to the preamble of claim 1.

Such a control processor is off the US-PS 38 10 104 known. This well-known Control processor can be used both as a numerical controller a machine tool as well as a programmable control device for controlling on / off functions on the ge controlled machine work. It contains for this purpose a first processor assigned to the numerical control device that is used for numerical control Workpiece program data blocks processed and in the course of this Processing also decodes workpiece program data blocks, which the setting of a selected storage space in a system flag table memory on a logi cause that indicates that at work an auxiliary function. Further the known control processor contains one the second pro assigned to the programmable control device processor device for carrying out this auxiliary function NEN is provided and periodically control unit commands that performs the operation of digital work devices serve, which exist on the machine tool are. The operation of these devices is done depending on the logical state of the Machine tool provided digital scanning device as well as depending on the logical state  the memory set by the first processor device System memory table memory locations.

From US-PS 39 42 158 is a tax processor known as a programmable controller works that the state of individual, a controlled Digital scanning device associated with the machine tool and individual, controlled machine tools ne assigned digital scanning devices actuated. This known control processor contains one Means to execute the in a routine memory stored control unit commands machine tool-specific routine. There is also an I / O image table memory provided that assigned to each of the machine tool digital scanner and for each of the tool ma digital working device associated with the machine Has storage space. The logical states of the memory locations allocated to digital scanning devices are continuously on the current machine tools stood firm. The logical states of the digital Storage devices are assigned to storage devices depending on the logical state of selected Ab tracer memory locations set, and after that the machine tool status is set accordingly. The I / O picture table memory has the advantage that the Expiration speed of a sequence of control unit command existing control program regardless of the Data transfer speed between the tax pro processor and the connected scanning and work device machine tool.

The object of the invention is a Control processor of the generic type continue to do so form that performed by the numerical control te control process and that of the programmable Control device performed control process at a time Lich optimally coordinated way executed can be.  

This task is with a tax processor according to the preamble of claim 1 solved by its characteristic features. After that ar works in the generic tax processor required system identifier table - Memory in a special way with an I / O image Table storage together. This collaboration is so hit that there is between the two control operations to a mutual influencing these processes Message exchange is coming. This exchange of messages happens relatively quickly. This is especially true of of great importance if the two control processes with Using a single processor in time-division multiplexing be performed. The only processor has to in this case within certain time limits perform many functions that control numerical tion and the programmable control unit. Each Action by the processor is therefore time-critical. The Processor designed according to the invention therefore provides an optimally interlocking result Association of a numerical control and a program mable control unit to a complete uniform machine tool control.

A training course for the tax processor according to claim 2 has the advantage that from the factory Machine tool manufacturers or users very easy to edit functions can be performed, such as se are described in US-PS 38 13 649.

A training course for the tax processor according to claim 3, it allows in conjunction with Memory registers of the processor, control unit commands and to carry out indirectly and efficiently.

The invention and its developments are as follows with reference to the drawings described before represent drawn embodiment. It shows

Disposed Fig. 1 is a perspective view of a cabinet in a numerical controller, which is connected to a machine tool,

Fig. 2 is a perspective view of the numerical Steue tion of FIG. 1 with the cabinet door is open,

Fig. 3 is a block diagram of the numerical control of FIG. 1, the

FIGS. 4A and 4B is a block diagram of a control processor, which forms part of the controller of FIG. 3,

Fig. 5 is a block diagram of an arithmetic and logic processor that forms a part of the control processor of FIG. 4B,

Fig. 6 is a block diagram of an input / output circuit which forms part of the control processor of Figure 4B.,

Fig. 7 is a schematic diagram of a circuit Prioritätscodier, the processor part of the control of FIG. 4A forms,

Fig. 8 is a block diagram of a real time clock circuit forming part of the control processor of FIG. 4B,

Fig. 9 is a flowchart of the software system,

Fig. 10 is a schematic representation of the relationship of the ex ternal I / O devices to places in the main working memory of the processor of FIG. 4A,

Fig. 11 is a schematic representation of a portion of the clock timer counter and word memory of Fig. 10,

FIG. 12A is a schematic drawing for explaining the Pro programming of the processor of FIG. 4A,

FIG. 12B is a ladder diagram illustrating the programming of the Pro processor of Fig. 4A,

Fig. 13 is a flow chart of the main controller routine which forms a part of the software system of FIG. 9,

FIG. 14A and 14B a flow chart of Blockausführungs- routine which forms a part of the software system of FIG. 9,

FIG. 15A and 15B are a flowchart of the ten-millisecond clock interrupt routine which forms a part of the soft ware system of FIG. 9,

Fig. 16 is an illustration of a single keyboard, the location of two can be used in Fig. 1 shown keyboards,

FIGS. 17 and 18 are flow charts of the Programmredigier routine which forms a part of the software system of FIG. 9,

FIG. 19A-19C are flow charts of the subroutines which are called by the Programmredigier routine of Fig. 18, and

FIG. 20A and 20B a flow chart of a XIC button subroutine that is called by the Programmredigierroutine of FIG. 18.

According to Fig. 1, a numerical control unit is housed in a cabinet 1 and connected via a cable 2 with a multi-function machine tool with automatic tool changer. 3 The numerical control controls the movement of a cutting tool 4 along two or more loading axes (coordinates) depending on a part program that is read by a tape reader 5 . In addition, the numerical control controls auxiliary functions of the machine tool 3 as a function of commands that were read by the tape reader 5 , such as automatic tool selection and replacement from a tool magazine 6 , pallet selection and change, spindle speed and coolant actuation. The implementation of these auxiliary functions involves the sampling of 1-bit signals generated by several input devices, e.g. B. of limit switches, selector switches and photocells, which are attached to the machine tool 3 , and the actuation of a variety of output devices such as solenoids, lamps, relays and motor starters. The number and type of these input and output devices and the way in which they are operated differ from machine to machine.

The numerical control described can be easily adapted to all machine tool brands. This is done by programming the numerical control by means of an auxiliary keyboard 7 in such a way that the state of the respective input devices of the machine tool to be controlled is selectively scanned and its output devices are selectively controlled so that they perform the desired type of operation.

A manual data entry keyboard 8 (MDE keyboard) and an associated cathode ray tube viewing device 9 are arranged on the door of the cabinet 1 directly above the auxiliary keyboard 7 . To the right of the MDE keyboard 8 and the display device 9 there is a main control panel 10 which has a large number of pushbuttons and selector switches for conventional operating tasks, such as mode selection, feed rate override, spindle speed override, touch mode selection, axis selection and the like. One of the pushbuttons releases the keyboards 7 and 8 for data entry.

To particular Figures 2 and 3. The elements of the numerical controller are arranged in the cabinet 1 so that they are easily accessible for inspection, testing and maintenance. The keyboards 7 and 8 are together with tape reader 5 , view device 9 and main control panel 10 on the cabinet door 11 is introduced . A secondary control panel 12 is located immediately above the tape reader 5 , and all of these control I / O devices are connected to an industrial control processor 13 located at the bottom of the cabinet 1 . In detail, the connection of the tape reader 5 via a cable 14 , that of the secondary control panel 12 via a cable 15 , the auxiliary keyboard 7 via a cable 16 , the view device 9 via a cable 17 and that of the main control panel 10 via a cable 18th to a collecting cable 19 , which leads to the industrial control processor 13 len. A processor front panel 26 has a plurality of manually operable pushbuttons and visual displays which relate to the actuation of the processor 13 and are connected to it via a multiple line 27 (or a channel 27 ).

Two input / output (I / O) interface frames 20 and 21 are arranged in the cabinet 1 above the processor 13 and connected to it via a collecting cable 22 which runs upwards to the left of them. A main power supply device 23 is arranged above the I / O interface frame 21 , while a memory power supply device 24 is arranged on the left side wall of the cabinet 1 .

The I / O interface frames 20 and 21 carry a variety of input and output circuits on closely adjacent vertical printed circuit boards (not shown in the drawings). These input and output circuits are used to couple the control processor 13 to the cable 2 , which leads to the machine tool 3 , and can be input circuits for scanning the state of limit, selection and push-button switches, such as those used for. B. are specified in US Patent 36 43 115, and have output circuits for driving solenoids and motors, such as are specified in US Patent 37 45 546. The input circuits also have actual position value accumulators, to which actual value data from position measuring transducers on the machine tool 3 are supplied, and the output circuits have registers for transmitting setpoint axis movement values to the machine tool control devices (servo devices). Further details regarding the mechanical structure of the I / O interface frames 20 and 21 can be found in US Pat. No. 3,992,654. The cabinet 1 with the two I / O interface frames 20 and 21 is sufficient to control a typical three-axis machine tool. However, if a larger system is required, up to five additional I / O interface racks can be accommodated in neighboring cabinets to increase the input / output capacity.

FIGS. 4A and 4B, the control processor is arranged to provide a 16-bit bidirectional data channel processor 30 around. 13 The data is transmitted via this channel 30 from one processor element to the other when a microinstruction is executed, which is stored in a 24-bit microinstruction register 31 . Each microinstruction determines the source of the data to be supplied to data channel 30 , the destination of the data, and all operations to be performed on the data. The microinstructions are stored in a microprogram read-only memory 32 , and one is read out via a channel 33 every 200 nanoseconds and transferred to the microinstruction register 31 . Read-only memory 32 stores a large number of separately addressable or selectable micro routines, each of which consists of a set of micro instructions. When the processor 13 is to perform a desired function, the corresponding micro routine is stored in the read-only memory 32 and selected by a 16-bit macro instruction stored in a read-write main memory 34 .

Main memory 34 consists of dynamic 4K by 1 MOS random access memories that have a storage capacity of up to 32,000 16-bit words. Macro commands and data are read or written from or into the main memory 34 via a 16-bit main memory data register 35 which is connected to the processor data channel 30 . The memory words are selected or addressed via a 15-bit memory address register 36 , which is also connected to the processor data channel 30 . In order to write information into the main working memory 34 , an address is first loaded into the working memory address register 36 by supplying its clock line 29 with a 1 signal (in the form of a high voltage). The data to be stored appear in the processor data channel 30 and are switched through by the main memory data register by applying a 1 signal to its data input clock line 27 . Then a read / write control line 34 ' at the working memory 34 is supplied with a 1 signal to complete the loading operation. Data or a macro instruction is read out over an addressed line of main memory 34 when a READ micro instruction is executed. The read / write control line 34 ' is a 0 signal (a never drige voltage) and a data output enable line 28 is supplied to the memory data register 35, a 1 signal. The data word is temporarily stored in the register 35 and then transmitted via the processor data channel 30 to the desired location.

Depending on the execution of a CALL RETURN micro-routine that contains the READ microinstruction, a macro error is read out of the main working memory 34 and transferred via the data channel 30 into a 16-bit macro instruction register 37 . The macro instruction is stored in the register 37 by a 1 signal, which is supplied to a macro instruction register clock line 37 ' . Certain macro commands include Operations codes, the 39 a macro, via a command register channel decoding circuit are fed to 38, and other commands also include a bit indication code, which is a bit-indication circuit supplies 40 fed over the same command register channel. 39 Bit pointer circuit 40 is a binary decoder that has four inputs connected to the lowest digit digit outputs of macro instruction register 37 and a group of 16 outputs, each with one line in the processor data channel 30 are connected. Depending on the execution of a predetermined macro command (MASK), a 1 signal is supplied to a terminal 41 , so that the bit indication circuit 40 supplies a selected line of the 16 lines in the processor data channel 30 with a 0 signal. The bit pointer circuit 40 allows certain macro commands from a programmable controller to be executed, as will be described.

Depending on an operation code of a macro instruction stored in register 37 , one of the micro routines stored in read-only memory 32 is selected. The opcode is applied to the macro decoder circuit 38 which gates one of four map proms (PROM = programmable read only memory) 42 through 45 and addresses a selected line in the map prom gated. Each line of the image proms 42 through 45 stores a 12-bit micro-routine start address which, after being read out, is fed to a micro-program address channel 46 to preset a 12-bit micro-program sequencer 47 . The sequential control unit 47 is a presettable counter, which has a charging connection 52 , an indexing connection 53 and a clock connection 54 . The clock connection 54 is acted upon by a five-megahertz clock signal, which is generated by a processor clock circuit 45 , which is connected to the sequencer 47 via an AND gate 46 . Every time the connection 54 of the microprogram sequence controller 47 is supplied with a 1-stroke pulse, it is either preset to an address which appears in the channel 46 , or switched on by a counting step or increased by one. At the same time, the micro instruction register 31 receives via a line 88 and an AND gate 88 ' a clock signal for reading and storing the microinstruction, which is addressed by the microprogram sequence controller 47 . The AND gates 86 and 88 can be locked in response to predetermined codes in a microinstruction to disable the five megahertz clock signal. This separation of the clock 85 from the sequential control unit 47 takes place, for example, during input and output operations in order to grant the data a runtime of one microsecond.

Each microinstruction misregistration from the ROM 32 into the microbe is transmitted is 31, 48 passes through a microbe ge failed channel 31 A in a microinstruction decoder circuit, which is also connected to the clock line 88th The microinstructions are decoded and executed before the next clock pulse is supplied to the connection 54 of the microprogram sequence control unit 47 . As will be explained in more detail, each microinstruction consists of several separate codes, which are referred to as microorders and are decoded separately in order to probe or release one of the processor elements.

Each microroutine stored in the microprogram read-only memory 32 ends with a special microinstruction which contains a code or micro order, which is referred to below with the short name EOX or EOXS. When supplied to the microinstruction decoding circuit 48 , this code causes a priority mapping prom 50 to be supplied with a 1 signal via an EOX line 49 . When the industrial control processor 13 is in the CONTINUOUS mode, the start address of the FET micro-routine is read from the priority mapping prom 50 and supplied to the sequencer 47 via the channel 46 . The microinstruction decoding TIC 48 further comprising a 1 signal to a preset line 51 to which is connected 47 to the load terminal 52 of the microprogram sequence controller factory, to adjust the flow control unit 47 to the starting address of the fetch micro routine.

As already mentioned, the FET micro routine is used to read the next macro command to be executed from the main working memory 34 , to transfer it to the macro command register 37 and to trigger the execution of this macro command. The last microinstruction in the ACCESS micro-routine contains a code which is referred to below with the short name MAP. This microinstruction code causes the microinstruction decoding circuit 48 to supply a 1 signal to the macrodecoding circuit 3 through a MAP line 52 to initiate decoding of the macroinstruction stored in the macroinstruction register 37 . Furthermore, the preset line 51 is supplied with a 1 signal in order to load the microprogram sequence controller 47 with the start address of the micro routine called by the decoded macro instruction. The list of the retrieval microroutine is contained in the microroutine appendix.

As, Fig. 4B, mathematical from the control processor 13 and logical operations are carried out in an arithmetic and logic processor 55 which is connected via the channel 56 to the processor data channel 30 and the microinstruction decode circuit 48. According to FIG. 5, the arithmetic and logic processor 55 contains a "L" register 57 for 16 bits, which has on the lines in the processor data channel 30 is closed folio inputs and a corresponding group of outputs via a channel 58 with the "B " Inputs of a 16-bit arithmetic and logic unit (RLE) 59 are connected. The data in channel 30 is clocked into the L register 57 when a line 60 is supplied with a 1 signal, and the L register 57 is cleared when a line 61 is supplied with a 1 signal. Lines 60 and 61 lead via channel 56 to microinstruction decoding circuit 48 and are therefore controlled by predetermined microinstructions.

The RLE 59 consists of four commercially available computing logic units, which are combined with a commercially available full transfer look-ahead circuit for performing high-speed operations such as additions, subtractions, reductions by one and straight-line transmissions. The RLE 59 has sixteen A inputs that are connected directly to the lines in processor data channel 30 and four function select lines 62 that are connected to microinstruction decoding circuit 48 via channel 56 . Depending on preselected microinstructions, the RLE 59 executes operations with its inputs A and B and transfers the 16-bit results via a channel 64 to a shift circuit 63 .

The RLE 59 also generates signals which are fed to an RLE decoder 114 which provides an indication when the result of a logical or arithmetic operation is zero, is all 1's, is odd, is negative, or when an overflow occurs when it is performed or a carryover occurs.

The occurrence of such a condition is checked separately from micro-orders or codes in micro-instructions which activate or switch on the RLE decoder 114 via the channel 56 . The occurrence of the monitored conditions results in the generation of a 1 signal on a jump line 115 connected to decoder 48 .

The occurrence of an overflow in the RLE 59 can also be stored in an overflow flip-flop 116 if its clock connection from the decoding circuit 48 is supplied with a 1 signal via a line 117 . The Q output of flip-flop 116 is connected to RLE decoder 114 and its state can be checked by an appropriate micro order. A system flag flip-flop 118 is connected to the RLE decoder 114 and can be switched over by the microinstruction decoder 48 depending on a suitable micro order via a line 119 . The flag flip-flop 118 can be set depending on one of the checked or monitored RLE states, and its state can in turn be checked by a suitable micro job that is effective via the RLE decoder 114 .

The shift circuit 63 consists of eight commercially available double four-line to one-line data selectors, the inputs of which are connected to predetermined lines in channel 64 . The sixteen outputs of the shift circuit 63 are connected to a sixteen line RLE data channel 65 and two control lines 66 connect them to the microinstruction decoding circuit 48 . Depending on the selected microinstructions, the shift circuit 63 directs the 16-bit data word from the RLE 59 directly into the RLE data channel 65 , or shifts or rotates this data by one or four bits.

The 16-bit data word in RLE channel 65 is fed to a 16-bit "A" register 67 , a 16-bit "B" register 68, or a direct access memory bank 69 . The data is keyed into the A register 67 by applying a 1 signal to line 70 which connects the A register 67 to the microinstruction decoder circuit 48 , or the data is keyed into the B register 68 by a 1 signal is supplied to a line 71 which connects the B register 68 to the microinstruction decoding circuit 48 . The six ten outputs of the A register 67 are connected to the "A" inputs of a 16-bit multiplexer 62 , and the sixteen outputs of the B register 68 are connected to the "B" inputs of the multiplexer 72 . Sixteen outputs of the multiplexer 72 are connected to the lines in the processor data channel 30 , and if a release line 73 is supplied with a 1 signal, either the content of the A register 67 or the content of the B register 68 is routed to the processor data channel 30 . The selection is made via a dial line 74 which, together with the enable line 73, leads to the microinstruction decoding circuit 48 . When selected microbes are executed, the A register 67 or the B register 68 can therefore form a data source for the processor data channel 30 via the multiplexer 72 , or they can be predetermined by selected micro commands as the destination of the data on the processor channel 30 , which is connected via the RLE 59 and the sliding circuit 63 .

The random access memory 69 consists of four commercially available 64-bit random access memories which form sixteen 16-bit registers, namely the "P" register and the R1-R15 registers. When a 1 signal is supplied to a read-write line 75 , a 16-bit data word from the RLE data channel 65 is written into the random access memory 69 . On the other hand, the content of one of the sixteen registers of the memory 69 is supplied to a 16-bit data buffer 77 via a channel 76 when line 75 is supplied with a 1 signal, and data buffer 77 stores this word when its clock line 78 is a 1 Signal is received. The lines 75 and 78 lead to the microinstruction decoding circuit 48 , so that both the direct access memory 69 and the data buffer 77 are controlled in dependence on selected microinstructions.

The respective register in the direct access memory 69 that is to be selected is determined by a 4-bit address code that is supplied to a group of connections 79 . The address connections 79 are connected to the outputs of a 4-bit multiplexer 80 , the "A" inputs for receiving bits 4-7 of the microinstruction (original field) and four "B" inputs for receiving bits 9-12 of the Microinstruction (receiving or destination field) via the microinstruction channel 31 A has. The multiplexer 80 is gated on a line 81 which leads to the microinstruction decoding circuit 48 and the 4-bit address on the A or B inputs is selected by the logic signal which is fed to a line 82 which leads to the clock circuit 85 leads to receive a five megahertz destination signal. If the direct access memory 69 is selected as the data source, the address of the relevant register of the memory 69 , from which the data are to be read, appears at the A inputs of the multiplexer 80 , and if the direct access memory 69 is used as the data destination (or destination) ) is selected, the address of the relevant register into which the data are to be written appears at the B inputs.

Data read from the direct access memory 69 and stored in the data buffer 77 are coupled into the processor data channel 30 via sixteen gates 83 . The gates 83 are gated on a line 84 which leads to the microbe error decoding circuit 48 and is controlled by this. For example, the P-register in the memory 69 serves as a macro program counter, and when the FET micro-routine is executed, the content of the P-register is read out and transmitted via the data buffer 77 and the gates 83 to the processor data channel 30 , via which it is sent to Main memory address register 36 is passed.

The arithmetic and logic processor 55 also contains a binary 8-bit repeat counter 141 , the inputs of which are connected to the eight least significant lines in the processor data channel 30 . The retry counter 141 can be loaded with a constant by a micro job that identifies it as the destination of the data and probes it over an enable line 142 . The same micro order leads a preset signal to a 1 signal via line 143 . The repetition counter 141 can be incremented over a line 144 , and if up to fifteen or two hundred and fifty-five has been counted, an output signal appears on line 156 or line 157 . The lines 142-144, 156 and 157 are connected to the micro instruction decoder 48th

FIGS. 3 and 4B, to which reference is again made, the reciprocating Herübertragung takes place of the data between the I / O interface racks 20 and 21 on the one hand, and the system I / O devices 5, 7, 8, 9 and 10 via an input / output interface circuit 87 which is connected to the processor data channel 30 . I / O interface circuit 87 includes sixteen data output ports 90 ( FIG. 6) having inputs connected to the lines of processor data channel 30 and having 16-bit input / output data channel 91 having closed outputs. A strobe line 92 connects a second input of each data output port 90 to the microinstruction decoding circuit 48 , and when this strobe line is supplied with a 1 signal, a 16-bit data word from the processor data channel 30 becomes the input / output data channel 91 transmitted. The input / output data channel 91 leads to the collecting channels 19 and 22 , which connect the industrial control processor 13 to the interface frames 20 and 21 and the respective system I / O devices, such as the cathode ray viewer 9 .

The input / output interface circuit 87 also includes a 16-bit input / output address register 93 which is connected to the six least significant lines in the processor data channel 30 . The I / O address register 93 is connected to the microinstruction decoding circuit 48 via a clock line 94 , and when the clock line 94 is supplied with a 1 signal, the processor data channel 30 becomes a 6-bit I / O Address keyed into register 93 . Six output ports of register 93 are connected to lines in a 6-bit I / O address channel 95 . The I / O address channel 95 leads to the collective channel 22 , so that the I / O address stored in the register 93 is transmitted via the channel 95 to the I / O interface frames 20 and 21 . An erase line 96 connects the address register 93 to the microinstruction decoder circuit 48 , and when a 1 signal is applied to this erase line, the register 93 is reset to zero. As described in more detail below, when an OTA macro instruction is executed, the I / O address (rack number and column number) is loaded into the output address register 93 and fed to the I / O address channel 95 . The addressed device acknowledges receipt of its address, and then a 16-bit data word can be supplied to the processor data channel 30 and switched through the input / output data channel 91 to the addressed device. In this regard, reference is made to the programmed data output microroutine in the microroutine appendix.

The data is transferred to the industrial control processor 13 via a 16-bit multiplexer 97 which forms part of the input / output interface circuit shown in FIG. 6. Sixteen "B" input ports on multiplexer 97 are connected to input / output data channel 91 and sixteen output ports are connected to corresponding lines in processor data channel 30 . The six lowest inputs of sixteen "A" inputs of the multiplexer 97 are connected to ei nem interrupt address channel 95 A. A gating line 98 and a selection line 99 on the multiplexer 97 are connected to the microinstruction decoding circuit 48 . When the strobe line 98 is supplied with a 1 signal, data is transferred from the I / O data channel 91 or the interrupt address channel 95 A to the processor data channel 30 . The selection is made by the signal state on the selection line 99 , which is also controlled by selection microinstructions via the decoding circuit 48 .

The decoding of the I / O address for the system I / O devices 5 , 7 , 8 , 9 and 10 takes place in the input / output interface circuit according to FIG. 6. The three highest-order lines of the input / output address channel 95 are connected to the corresponding inputs of three exclusive NOR gates 102 to 104 , and its three lowest-order lines are connected to the inputs of a BCD decoder 105 . The second input of each of the exclusive NOR gates 102 to 104 is via respective switches 106 to 108 with a 0 signal feeding terminal 109 and an output terminal of each of the gates 102 to 104 is connected to respective inputs of an AND gate 110th An output of the AND gate 110 is connected to a gating terminal 112 on the BCD decoder 105 , and if a 1 signal is supplied to this terminal, the binary decimal-coded 3-bit number which is present at the inputs of the decoder 105 , decoded. In this case, a 0 signal is generated at one of the eight connections 113 , of which the five lowest digits are connected to corresponding system I / O devices 5 , 7 , 8 , 9 and 10 via the collecting channel 19 . The three switches 106 to 108 are set so that they indicate the frame number (which in the preferred off operation example, the number is 1), and if this number appears the I / O address channel 95 to the most significant three lines, one of the system I / O devices addressed.

The input / output interface circuit 87 of FIG. 6 further includes a clock controlled interrupt circuit 162 . The circuit 162 includes an RS flip-flop 163 with a set terminal 165 which is connected via a line 164 to the processor clock circuit 85 ( FIG. 4B). Every 10.25 milliseconds, a 1 pulse is applied to the flip-flop 163 as a set pulse, so that a 1 signal appears at its Q output terminal and an interrupt request line 160 is supplied. The interrupt request line is connected to a priority coding circuit 127 ( FIG. 4A), as will be described in more detail, and when the interrupt is granted, a 1 signal is generated on an interrupt confirmation line 161 . The interruption confirmation signal is switched through by an AND gate 166 and keyed into a dc flip-flop 167 . The Q output of the dc flip-flop 167 is connected via a line 168 to an input at each of six AND gates 169 and via a line 170 to an AND gate 171 . The outputs of the AND gate 169 are each connected to a line in the interrupt address channel 95 A and their respective second input connections to 1- and 0-signal sources in such a way that the octal address 17 is generated in the channel 95 A , if that dc -Flipflop 167 is set. The circuit 162 performs the priority encoder 127 every 10.24 milli-seconds to an interrupt request, and if it receives a Be stätigungssignal, it forms the I / O address 17 in the interrupt address channel 95 from A.

Circuits similar to the clock controlled interrupt circuit162 are in the keyboards7 and8th and the tape reader5 arranged. All of these are system I / O devices with the interrupt request line160 and "geese flower chain-like "with the interruption confirmation line tung161 connected. HowFig. 6 shows the interrupt confirmation line161 through an AND gate172 about the Un break circuit162 led by the -Output connection of the RS flip-flop163 is controlled. So if the circuit 162 requesting the interruption does not just speak up the resulting interrupt confirmation signal on, son they also prevent this signal from being sent to subsequent ones System I / O devices continued in the daisy chain  is leading. This way, only one interruption I / O device operated at once. If so, as below an interruption of the priority coding circuit127 is confirmed, it resolves also the execution of an interruption control micro routine, which is the I / O address of the interrupt device device in the register R4 of the memory69 loads. This I / O Address is then used to locate the start address in the main read / write memory34 a macro routine used that system I / O device concerned serves. So the clock-controlled interrupt circuit calls162  for example a 10 millisecond clock controlled sub break routine on (Fig. 15A and 15B). The interruption operating microroutine is in the microroutine appendix listed.

As the above description shows, the various elements of the control processor 13 are actuated in turn depending on microinstructions which are read from the microprogram memory 32 into the microinstruction register 31 and are then decoded by the decoding circuit 48 . The address of the first microinstruction of each micro routine to be executed is loaded into the microprogram sequencer 47 from one of the mapping proms 42 through 45 or 50 , and while the microinstructions are being executed, the microprogram sequencer 47 is incremented by one to that Read out the next microinstruction of the micro routine until an EOX or EOXS code is determined, which indicates the end of the micro routine.

To enable the use of JUMP microinstructions and thus only one level of a microsubroutine, a 12-bit save register 120 is connected to the outputs of the microprogram sequencer 47 via a channel 121 and a 12-bit multiplexer 122 with the inputs of the sequencer 47 connected via the address channel 46 . The save register contains a clock line 123 which is connected to the microinstruction decoding circuit 48 , and when selected JUMP microinstructions are executed, the address stored in the microprogram sequencer 47 is transferred to the save register 120 . The outputs of the fuse register 120 are connected to twelve "A" inputs of the multiplexer 122 , and when a recall micro command is subsequently executed, the address stored in the fuse register is switched through the multiplexer 122 and reloaded into the microprogram sequencer 47 . The multiplexer 122 further includes "B" inputs, which are connected to the microinstruction channel 31 A, and if a branch micro-instruction is executed, the target address contained in the command from the micro instruction register 31 is in the microprogram sequence controller 47 via the multi- plexer 122 switched through. The multiplexer 122 is controlled by the data selection line 124 and a strobe line 125 , both of which are connected to the microinstruction decoding circuit 48 .

According to FIG. 4B, the microinstruction channel 31 is also connected via A sixteen AND gates 158 with the processor data channel 30. One input of each gate 158 is connected to a line 31 A in the channel, while the second inputs are connected in common via a line 159 to the microinstruction decode circuit 48th Their outputs are each connected to a line in the processor data channel 30 .

According to FIG. 4A is a control panel interface connects sound processing 126, the switches, lights and other control and display devices on the processor front panel 26 and secondary control panel 12 to the processor data channel 30. The control panel interface circuit 126 is also connected to inputs of a priority encoder 127 via a 17-line channel 128 , and five outputs of the priority encoder 127 are connected via a channel 129 to the priority mapping prom 50 . Control panel interface circuit 126 receives signals from panels 12 and 26 over cables 15 and 27 and over processor data channel 30 . In response, it generates a 0 signal on one or more of the lines in cable 128 that determine the desired operating mode of control processor 13 .

As shown in FIG. 7, priority encoder 127 includes a first 3-bit binary encoder 130 that has eight inputs, seven of which are connected to channel 128 . The eighth input is connected to the interrupt request line 160 from the I / O interface circuit 87 . An 8-bit data buffer 131 has eight inputs connected to lines in channel 128 and eight output connections, each connected to an input of a second 3-bit binary coding circuit 132 . Three output connections 133 of the first binary encoder 130 are each connected to a first input of three NAND gates 134 to 136 . Similarly, three output ports 137 of the second encoder 132 are each connected to a second input of the NAND gates 134 to 136 and a fourth output port 138 of the second encoder 132 to a gating port 139 of the first binary encoder 130 . The fourth output 138 , the outputs of the respective NAND gates 134 to 136 and a seventh line 140 in channel 128 are each connected to a line in channel 129 , which in turn is connected to the priority mapping prom 50 . Line 140 is connected to input number 4 of the first binary encoder 130 .

The priority encoder 127 generates a 5-bit binary code which is supplied to the priority mapping prom 50 . This responds to a 0 signal on one of the seven lines in channel 128 and effects the addressing of a line of the mapping prom 50 . The mapping prom 50 is gated on when a 1 signal is supplied to its EOX connection 49 at the end of the micro routine which is then being executed, so that a 12-bit start address is derived from the addressed line of the gated mapping Proms 50 read out and the microprogram sequence controller 47 is supplied. Although more than one of the lines in channel 128 may carry a 0 signal at any time, encoding circuit 127 generates the code or mapping prom line address only for the line that has the highest priority. The signals that appear in the list below on the channels 128 numbered sequentially in order of priority result in the execution of the following functions or operations:

The priority encoder 127 further includes a binary / octal decoder 165 with three inputs of the NAND gates 134 are connected to 136 in each case to one. The second of eight output terminals of the decoder 165 is connected to the lower refraction acknowledge line 161, and when the interrupt-service microroutine by a 1 signal is required on the interrupt request line 160, is generated on the interrupt acknowledge line 161 is a 1 signal if the request is granted.

FIGS. 4B and Figure 8 is a real time clock circuit 145 connected to the processor data channel 30 and controlled decoding circuit microinstruction 48 from the. The real-time clock circuit 145 contains a D flip-flop 146 , the clock connection of which is supplied with a 5-megahertz clock signal via a line 147 from the processor clock circuit 45 . The D input of flip-flop 146 is controlled by two NAND gates 148 and 149 via an AND gate 149 A. A first input of the NAND gate 148 is connected via a line 150 to a five-Hertz clock signal output of the processor clock circuit 85 and a second input via a line 151 to the macro instruction register 37 . The line 151 indicates the logic state of the least significant bit of the macro instruction stored in the macro instruction register 37 and is connected via a reversing gate 152 to a first input of the NAND gate 149 . A second input of NAND gate 149 receives a 0.5 Hertz clock signal from processor clock circuit 85 via line 153 . The Q output of flip-flop 146 is connected to one input of a NAND gate 154 . The second input of the NAND gate 154 is connected to the microinstruction decoder circuit 48 via a TIM line 155 , while the output of the NAND gate is connected to the least significant line in the processor data channel 30 . Depending on a selected microinstruction (TIM), the state, one or zero, of either the 5-Hertz or the 0.5-Hertz clock signal of the lowest-order line in the processor data channel 30 can be fed and checked.

The hardware described above is controlled by microinstructions, one of which is executed every 200 nanoseconds. These microinstructions contain codes that are decoded by the circuit 48 to supply strobe signals to the corresponding system elements. Operation of the hardware will become clearer after the description of the microinstruction set executed by that hardware.

The microinstruction set consists of three types of instructions. The first type of microinstruction has the following format and is used to transfer data between processor elements connected to processor data channel 30 to perform logic and arithmetic functions (operations) on data supplied to RLE 59 and to perform data checks and microinstruction jump operations.

The microinstruction decoding circuit 48 simultaneously decodes all five "micro orders" for this first type of microinstruction and turns on the appropriate processor elements to perform one or more functions (operations). However, the processor element required by the destination or receive code is only turned on in the last 50 nanosecond section of the 200 nanosecond execution timing. The codes that can be used in the five micro orders of a "Type 1" microinstruction are as follows:

Micro order codes of processor functions

Micro order codes of the RLE functions

Receive field micro order codes

Origin field micro order codes

Crack micro order codes

License plate micro order codes

The LABEL micro orders are only released if if the processor function micro order FLG or FLGS in same micro command appears. In the absence of the micro order FLG or FLGS the SPRUNG micro orders are released.  

Picture Micro Order Codes

The second type of microinstruction has the following format:  

The processor function micro order codes and the destination micro order codes are the same as those given above Microinstruction type. There are only two RLE function micro order codes in place, and in addition to these functions, these prescribe both codes, they serve, as described above, to mark the microinstruction as one of the format of the second type.

RLE function micro order codes

Modifier micro order codes

The operand microorder code is a whole eight digit Binary number that is a decimal number from 0 to 255 or an octal number from 0 to 377.

The third type of microinstruction has the following format:

The processor function micro job codes are the same like the microinstructions of the first type, and besides the functions, that prescribe these two codes below, they are used to identify the macro command as one of the Format of the third type.

RLE function micro order codes

Modifier micro order codes

The operand micro-job code of a type three instruction is a 12-bit address which is supplied to the microprogram control unit 47 via the multiplexer 122 .

The microinstructions defined above are put together to form micro routines which are stored in the microprogram read-only memory 32 . These micro routines are in turn used to execute macro instructions that are stored in main memory 34 . The macro instructions are put together to form programs or routines, the various numerical control functions are carried out and the individual digital devices of the machine tool are actuated when they are executed. Before describing in detail how the macro instructions are carried out by selected micro routines, the software system of the industrial control processor 13 is to be described broadly in order to familiarize the reader with the tasks to be solved and the basic mode of operation of the device for solving these tasks do.

Furthermore, regarding commercial numerical control devices, to which the invention can be applied, to the essay "The Technical Ins and Outs of Computerized Numerical Control "by P. G. Mesniaeff in" Control Engineering ", March 1971.  

The operation of the control processor 13 is determined by the software routines which are stored in its main working memory 34 and which together form the software system. The software system consists of four main parts: basic routines; 10 millisecond clock interrupt control routines; Tape reader routines and keyboard routines.

According to FIG. 9, the basic routines 175 consisting of such numerical control effecting the basic routines such as build-up, decoding, non-interrupted part of the keyboard and tape reader routines, display update subroutine, ASCII / octal and octal / ASCII converter, rakes - and support routines, touch operation, keyboard operation, tool and holder relocation, cutting tool correction and part program reduction. The basic routines also include those that are required by the facility's programmable controller, such as a machine-dependent software loader and editor (text manipulator), hard copy output, hole punch output, and I / O monitor. Most of these basic routines are optionally called by a main control or execution routine 176 , which consists of three program loops 177 to 179 . These three loops 177 to 179 are selected by mode switches on the main control panel 10 . The first loop 177 is responsive to the selection of automatic or block-by-block modes, the second loop 178 to the keyboard mode, and the third loop 179 to the manual mode. A detailed flow chart of the main control routine 176 is shown in FIG .

The automatic and block-by-block modes of operation are performed by a common loop 177 that calls selected basic routines 175 . These routines trigger the tape reader 5 , read the partial program data block, decode it and set it up. Routine 177 then calls a block execution routine which actually executes the program part data block.

As shown in the detailed flow chart of FIGS . 14A and 14B, the block execution routine is divided into a header or header, an interpolation portion, and a post-block or header. During the preload portion (or prelude portion), selected system flags are set to indicate that certain functions, such as turning on the spindle, coolant, and the like, are to be performed. These identifiers are stored in a selected working memory part in a system identifier table 182 in the main working memory 34 . Similarly, during the trailer portion of the block execution routine, flags from table 182 are set to indicate that certain functions, such as tool change, reciprocation, coolant and spindle shutdown, and the like, should be performed by the machine-specific devices. As will be described in more detail below, it is the tag table 182 that couples the numerical control functions of the device to the functions of the programmable controller of the device.

The second loop 178 of the main control routine 176 is initiated when the keyboard release push button on the main control panel 10 is operated. This operating mode is used, for example, to carry out functions such as the partial program reduction of the machine-specific software routine, which is described in more detail below with reference to the flowcharts according to FIGS . 17 to 20. The third loop 179 of the main control routine 176 is initiated when the front panel selector is set to "manual". The manual routine contains all operating functions, such as touch mode, belt control and zeroing, which are each carried out by optionally called routines.

The main control routine 176 therefore directs all of the basic functions of the device which serve to prepare the control processor 13 for the formation of the data which are fed to the servo devices (control devices) on the machine tool and indicate the auxiliary functions to be carried out to the associated specific digital devices.

The remaining parts of the software system interrupt the main control routine 176 to operate the I / O interface frames 20 and 21 and the I / O devices of the device. A 10 millisecond clock interrupt routine 183 causes the instantaneous transfers of data from the control processor 13 to the control devices and specific digital devices of the controlled machine tool. This routine is shown essentially in FIG. 9 and is then executed for finishing every 10.24 milliseconds after an interrupt requested by the clock controlled interrupt circuit 162 . As previously mentioned, an interrupt servicing micro routine loads the memory start address of the 10 millisecond clock interrupt routine 183 into the P register (program counter) of memory 69 , and then it is executed for finishing.

After various organizational operations have been performed, see FIG. 9 and FIGS. 15A and 15B, actual position data and desired position data are transmitted between the I / O interface frame 20 and the control computer 13 by a controller operating routine 184 . In a three-coordinate machine, for example, the x , y and z coordinate position actual value accumulators are connected to columns 0-2 of the first I / O interface frame 20 and control device setpoint registers are connected to columns 3 to 5 . The routine 184 sequentially executes the three 16-bit actual value words in corresponding lines in the read / write main memory 34 and the three 16-bit setpoint words, which were previously calculated and stored in three main memory locations in the main main memory 34 , columns 3 to 5 of the I / O interface rack 20 too.

The states of all the scanners connected to the I / O interface frames 20 and 21 are then fed to the main memory 34 through an input state routine 186 .

Routine 186 sequentially feeds the sixteen bits of state data from the columns of I / O interface frames 20 and 21 to an associated row in main memory 34 . A part of the main working memory 34 , hereinafter referred to as I / O image table 185 , serves to store these status data and the data which are to be output to the I / O interface frames 20 and 21 . A more detailed description of the connection between the I / O columns in interfaces 20 and 21 with the rows in I / O image table 185 is given below, and the input sampling micro-routine that extracts the data from the eight columns of an I / O A interface rack to the I / O image table 185 is listed in the microroutine appendix.

Next, a machine-specific software routine 187 is executed to determine the state in which all working devices attached to the I / O interface frames 20 and 21 are to be placed. As will be described in more detail below, the machine-specific or machine-dependent software routine 187 contains programmable controller instructions that are executed in order to perform Boolean or switch algebraic operations and thereby determine the state of working devices. In making these determinations, the status of selected bits in the I / O image table are determined to determine an image of the current status of both the numerical control process and the machine-dependent devices connected to the control device. The determined states are stored in the I / O image table 185 , and after the routine 187 has been executed, these states are supplied by an output state routine 194 to the output circuits in the I / O interface frames that drive the connected working devices. Routine 194 transfers 16-bit status words from main memory 34 to their associated I / O interface racks and columns. The output sample micro-routine for transferring the I / O image table status words into the eight columns of an I / O interface rack is listed in the micro-routine appendix.

When a block of program part data has been set up and the leader functions have been performed, an interpolation subroutine 188 is executed to calculate position set point data for the machine control devices. These calculated position setpoint words control the controllers for a period of 10.24 milliseconds and are output by controller operator routine 184 during the subsequent 10 millisecond interruption. The timed interrupt routine 183 is returned to the main control routine 176 .

The machine-specific software program is thus executed once during each 10.24 millisecond interruption to check the states of the scanners that appear in the I / O image table 185 during the 10 millisecond interval and the states of the bits in the I / O image table 185 that correspond to the working devices. Equally often, I / O image table 185 is updated by transferring data between it and interfaces 20 and 21 to ensure that its state is an accurate picture of the state of the machine being controlled.

A third type of routine of the software system of Fig. 9 is the tape reader routine, which is divided into two parts: the interrupt part 190 and the base part. The tape reader routine is called by the main control routine 176 , which uses the main part of the tape reader routine to perform trigger functions. After the triggering or initiation of the basic part, a tape reader interruption occurs whenever a new tape character is arranged under the reading head of the tape reader 5 , the interruption part of the tape reader routine 190 being executed. In this routine, the tape character is read and transferred to a selected data buffer in main memory 34 . It also sets flags in system table 182 when the end of block character has been read and the block boundary has been exceeded.

A fourth type of software system routine is the keyboard and display routine. This contains an interruption part 191 , which is initiated each time a key on the MDE keyboard 8 or the auxiliary keyboard 7 is pressed. Basic parts of the keyboard and display device routine interpret the received ASCII characters as data stored in the main working memory 34 or as codes which call the execution of special subroutines. The two keyboards 7 and 8 are connected in parallel, and their only difference is that different symbols are printed on their keys. The keyboard 8 has keys with symbols that are typical of a numerical control device, while the keyboard has 7 keys that are typical of a program loader of programmable control devices. For example, a group of keys on the auxiliary keyboard 7 contains symbols of elements of a ladder diagram, and when these keys are actuated, a ladder diagram is displayed on the display 9 . In this way, control unit commands that are to be loaded into the machine-specific software part 187 of the main working memory 34 are generated on the auxiliary keyboard 7 , while a circuit diagram corresponding to the control program developed is simultaneously built on the display unit 9 . Other keys of the auxiliary keyboard 7 call up editing functions which are to be carried out by the control program formed. These include the SEARCH, MONITOR, GAP, and UNGAP functions described in US Pat. No. 3,813,649.

However, only a single keyboard can be used to operate both the numerical control functions and the functions of the programmable control device. In this case, it is expedient to mark the keys with symbols that are assigned to their two functions, as shown in FIG. 16. Regardless of whether only one keyboard or two keyboards are used, control is effected by means of the keyboard 8 if the device is set to keyboard operation. By entering the command "AL, PE" on the keyboard 8 , however, a basic program editing routine is called, so that all subsequent ASCII characters are interpreted according to the symbols on the keyboard keys of the programmable control unit. A flowchart of the program editing routine is shown in Fig. 17 and will be described in more detail below.

As already mentioned, an image of the state of the machine controlled by the control computer 13 is stored in the I / O image table 185 of the main working memory 34 and the state of the numerical control possibilities of the device in the system identification table 182 . According to FIG. 10, the E / A is-image table 185 from up to twenty-four lines of the main memory 34, not all of which are used in the preferred embodiment. Columns 6 and 7 of the interface frame 20 are connected to corresponding lines 6 and 7 of the I / O image table 185 , and all eight columns in the I / O interface frame 21 are with corresponding lines 20 to 27 (octal) in the I / O -Table 185 connected. All columns in the interface frame 20 and 21 , which are connected to the I / O image table 185 , each contain sixteen separate input or output circuits, each of which is connected to a digital device of the machine tool 3 , e.g. B. a limit switch or an engine starter. Each of these input or output circuits is assigned one of the sixteen bits on a memory line in the I / O image table 185 , so that there is a status bit in the I / O image table 185 that is associated with each particular digital device that is connected to the E / A interface frames 20 and 21 is connected. For example, a switch S on the machine tool 3 closes when the maximum value of the feed movement in the direction of the X axis has been reached, and it is connected to an input circuit which is arranged in column 3 of the interface frame 21 . Bit 14 on memory line 023 (octal) corresponds to this limit switch S , and when the limit switch S is closed, this bit is set to the 1 state during the next 10.24 millisecond interruption. The status of bit 14 on line 023 can then be checked by a command from machine-specific software routine 187 to determine the status of its corresponding scanner.

The machine-specific software routine 187 consists of controller commands that check the status of selected bits in the I / O image table 185 and controller commands that set the status of selected bits in the table 185 . The control device's check command consists of two memory words, the first of which represents the operation code and a four-bit bit indication and the second word the memory address of the status bit. For example, to check whether limit switch S is closed, the following 2-word check macro instruction is executed by industrial control processor 13 :

As will be described in more detail below, the XIC operation code indicates a selected micro-routine, the execution of which reads the content of the I / O image table line 023 (octal) onto the processor data channel 30 . The bit indication circuit 40 is released and the 4-bit indication (1110) is fed to it in order to mask or hide all but one status bit 14. The logic state of bit 14 is therefore fed to RLE 59 where it is checked.

The system similarly operates to set the status of the selected status bits in the I / O image table 185 . For example, a solenoid (SOL) connected to an output circuit number 12 in column 2 of the third I / O interface rack 21 is to be controlled by the machine-specific software routine 187 . In this example, the status bit number 12 in the I / O image table row 022 (octal) corresponds to the solenoid SOL, and the state of the solenoid SOL can be controlled to the appropriate state by setting this status bit. The following macro command sets the state of the solenoid status bit in I / O image table line 022 (octal) to the 1 state:

The first word is the opcode that selects the appropriate micro route 32627 00070 552 001000280000000200012000285913251600040 0002002743492 00004 32508ne and prepares the bit flag 40 while the second word selects the memory line. After being set by the control device command, the state of the status bit is fed to the output circuit, which actuates the solenoid SOL by the data output routine 189 . However, it should be appreciated that the I / O image table 185 can be placed anywhere in the main memory 34 . As a result, the second word in each controller command typically contains a number that is significantly larger than that contained in the above examples and identifies the absolute memory address of the desired status bit.

As already mentioned, the system identifier table 182 serves to adapt the aspects of the programmable control device of the device to the aspects of the numerical control. As shown in Fig. 10, the tag table 182 is stored alongside the I / O image table 185 in the relative memory rows 200 through 377 (octal). The content of the system identification table for a three-coordinate milling machine is listed in the system identification table annex to this description. As can be seen, considerable space is left free, so that the system can be adapted by the user to the machine tool make used in each case. The state of the tag table 182 is primarily determined by the basic routines 175 that are called by the main control routine 176 , although the machine-specific software routine 187 controls some of them.

The machine-specific software routine 187 may check the status of any system identifier during execution with an XIC instruction, as described above, or other programmable controller test instructions, which are described in more detail below. In short, system tag table 182 is essentially treated as an extension or addition to I / O image table 185 , which is an image of the state of the controller as it executes a program unit. The system identifier table 182 is used to coordinate the operation of the machine-specific work devices with the execution of the partial program.

The machine-specific software program 187 , which is stored in the main working memory 34 , consists of sets of macro instructions of the programmable control device type, which are executed in succession during a 10.24 millisecond interruption. As with conventional programmable controllers, these macro commands perform Boolean equations or switching functions to decide whether a particular work device needs to be turned on or off. U.S. Patent No. 39 42 158 describes a programmable controller in which the controller commands include those that check the states of the selected state bits in the I / O image table 185 and those that check the selected state bits therein for a logic state that depends on the result of a Boolean equation or combination. The described control processor directly executes a complete set of instructions as used in a programmable controller so that the user can use the machine-specific software program 187 using conventional instructions from a programmable controller and using programming techniques as described in the US patent 38 13 649 are described, can develop.

The programmable controller type macro instruction set contains 33 operation instructions and nine edit instructions. The operation commands can be divided into the following five types: basic commands, timer commands, counter commands, arithmetic commands and special commands. The basic instructions are those that are required to execute or solve Boolean equations. In the following list of such commands, the "display and keyboard symbol" provided for each appears on a key of the auxiliary keyboard 7 and on the screen of the cathode ray tube display device 9 when this key is pressed.

Basic commands

Clock commands

Counter commands

Arithmetic commands

Special commands

The editing commands are used to develop machine-specific software, using the keyboard 7 and the display device 9 . These commands call subroutines that do the following:

A sample program is described below to give an idea of the functions to be performed. The program example applies to a three-axis (x, y and z) machine tool, which is shown schematically in FIG. 12A and in which a cutting tool 200 is displaced in the direction of each axis as a function of position setpoint words that are generated by a partial or The workpiece program tape is read by means of the tape reader 5 . The machine tool has an index table 201 which carries the workpiece and can be rotated about a vertical axis b in order to bring the workpiece into the working position relative to the cutting tool 200 . The motor provided for the feed in the direction of the X axis is used to rotate the index table 201 . The index table 201 is lashed and lifted, and then drive power is mechanically transmitted to the index table gear train when a solenoid (SOL A) is turned on. A first limit switch (LS1) determines when the index table reaches the upper end position UP, a second limit switch (LS2) determines when the gear train is engaged, and a third limit switch (LS3) determines when the index table reaches the lower end position Has reached DOWN. The following sequence of operations should take place:

• 1. A "b" setpoint word for rotating index table 201 is read by tape reader 5 and transferred to an active buffer in main working memory 34 . Lock header (foreplay) and trailer (foreplay) requirement flags in the system flag table 182 .
• 2. When all axes are in position and the control device in the opening credits, start lashing of the index table and its displacement in Direction to the upper end position by switching on SOL A.
• 3. Make sure that the index table is in the upper end position by checking LS1 and whether Gear train is engaged by inspection from LS2.  
• 4. Release of the opening credits. The control device then executes the b setpoint word by rotating the index table 201 .
• 5. Compliance with a waiting time of one second after the b axis is in the target position in order to allow an overshoot to subside.
• 6. Wait for the credits, then turn off the SOL A.
• 7. Check the gearbox intervention (LS2), make sure that index table 201 is in the lower end position (LS3) and then release the trailer.

The assignment of the connections on the I / O interface frames 20 and 21 to the external I / O devices (LS1, LS2, LS3 and SOL A) is arbitrary. As shown in FIG. 11, they are connected to the first three connections in column 5 and the first connection in column 7 of the third I / O interface frame 21 . The following table summarizes these assignments.

The one to coordinate this sequence of events with the execution of the workpiece program tape required internal system characteristics are the following:

A program for executing the sequence of events described above is entered into the machine-specific software section 187 of the main working memory 34 by successively pressing the corresponding keys on the auxiliary keyboard 7 . Each time a key is pressed, the character is displayed on the display 9 in ladder diagram format as shown in Fig. 12B. The resulting program is as follows:

The machine-dependent software (MDS) is entered by calling the program editor or program editor. In accordance with the flow chart of this macro routine of Fig. 17, the programmer labels parameters such as the rung position indicator symbol and also clears the display. The edit flags (edit flags) set by the previous edit commands (edit commands) are cleared, and then the word "start" is displayed on the display device, or a rung display subroutine is called and that of the rung Position indicator icon displayed ladder diagram rung displayed on the display device. The conditioner then remains in a loop until a character is received by the auxiliary keyboard 7 .

When an ASCII character is received, its code is used to look up or map the start address of a subroutine associated with it. According to FIG. 18, this search or mapping is carried out by a character table 210 which occupies fifty lines of the main main memory 34 , one for each keyboard key. Depending on the receipt of a numeric character (0-9), the content of one of the first ten lines of the character table 210 is read out and executed. Since a numeric character alone is meaningless, the content of each line 0-9 is a jump command back to the starting point "B" in Fig. 17 to await the reception of another character from the keyboard 7 .

The edit or edit keys that are used to form the MDS routine and the rung element keys that are used to form the control unit commands each generate a special ASCII character that addresses an associated line in the character table 210 . The contents of these addressed lines are jump instructions which point to the start of a special subroutine which carries out the function or task required by the key assigned to it. At the end of the subroutines assigned to the edit keys, the program editor is started again at point "B" in Fig. 17 to wait for the next keyboard character to be received. On the other hand, at the end of the rung element subroutines, the program editor is started again at point "A" in order to update the display of the display device by executing the rung display subroutine. Therefore, each time a rung element is entered in the MDS routine, this element is added to the ladder diagram displayed by the display device 9 .

The subroutines for performing the tasks desired by the edit keys are illustrated by the flowcharts in Figs. 19A through C for the insert, delete and transfer keys. The insert key subroutine only sets an insert flag to "1" and sets an existing remove flag to "0" and returns to entry point "B" of the program editing routine in Fig. 7. Similarly, the remove button subroutine sets the removal flag to "1" and an insertion flag to "0". If the transfer key is pressed twice in succession, the program editor must be triggered and the control must be transferred back to the MDE keyboard 8 . The transfer key subroutine of Fig. 19C therefore waits for the next key character to be received, and if it is another transfer, the subroutine and the program editing subroutine are triggered. Otherwise, the subroutine returns to the entry or start point "C" of the program processing routine according to FIG. 17.

The rung element key subroutines are much more complicated than the XIC key subroutine flowchart shown in FIGS . 20A and B. This subroutine first checks whether the XIC key has been operated as part of a remove or insert edit function. If the removal flag has been set and the element position indicator symbol indicates an XIC instruction currently stored in MDS portion 187 of main memory 34 , that instruction is removed and the routine returns to entry point "A "of the program editor. If, on the other hand, the insertion flag is set or the element position indicator element indicates the last element (control unit command) of an incomplete rung (Boolean expression), a 2-word XIC instruction is loaded into the main working memory 34 and the element position indicator symbol is increased so that it indicates the memory locations in which the command is to be saved. If no insertion is to be made and the position indicator symbol does not indicate an output element (e.g. an OTE command), the command indicated by the element position indicator symbol must be replaced by an XIC instruction. In any event, after the XIC opcode has been loaded into main memory 34, a digit counter is set to minus three in preparation for receiving three octal digits which form the second word of the XIC instruction.

In particular, Fig. 20B, in the XIC-key subroutine, a loop is formed waiting for the receipt of three octal digits or a command for deleting the command. Each time an octal number is received, it is loaded into main memory 34 to form the second word of the XIC instruction. After receiving the three octal digits, a second loop is formed, waiting for the first bit (1 or 0) of the 4-bit hint code to be received and loading it into the first word of the XIC instruction, together with the XIC- Operation code. The third loop is then formed, waiting to receive the last three bits of the bit flag (in the form of an octal digit) and loading it into the first word of the XIC instruction to complete its formation. The XIC key subroutine then returns to the program editor entry point "A" to wait for the next keyboard character to be received. During the formation of the XIC command, the rung displayed by the display device 9 is updated after each character has been entered, so that the operator can visually convince himself of the input of the correct character when the keyboard 7 is actuated. The rung element thus formed is also caused to flash by the XIC key subroutine so that the operator is clearly informed of the formation of the rung element and that additional characters must be entered to complete the formation of the control device command.

The control unit program in the example described above is entered into the MDS routine 187 in the main working memory 34 by means of the auxiliary keyboard 7 , the display unit 9 and the program preparation routine, and the ladder diagram belonging to this program is built up on the display unit 9 . Although the device is designed for a large number of rungs or Boolean expressions and each rung can have innumerable branches and elements, the display device 9 is nevertheless limited to the display of five lines at a time, with up to ten elements in one line. The display can be moved up or down to show other rungs of the ladder diagram.

As you can see, the control unit commands are bit-oriented and not word-oriented. That is, the state of individual bits is checked or the bits are changed to a desired state set. Furthermore, the condition must be a Boolean Expression or a ladder rung as long as an expression command is executed. If the boolean expression is met (i.e. the rung is conductive), then the programmed event, which is carried out by due to the elements of this expression. Even though it is not shown in the example above, occur on the Field of controls also on boolean expressions by more than one group of conditions can be met. These expressions have one or more OR functions, which are considered to be parallel branches in the rung diagram can. In this case, those prescribed in the main rung Conditions are met if any of  several parallel branches in the rung is fulfilled.

In particular, according to FIGS. 4A, 4B and 5, a command is recognized by the type of programmable controller, when a charged into the macroinstruction register 37 macro instruction comprises an operation code of 105, 1014, 1015, 1016 or 1017 starts (octal). The macro decoder 38 detects these codes and reads the start address of the corresponding micro routine from one of the mapping proms 42 to 45 (also called lookup prom). These micro-routines are listed below, but the following is a general description of how this facility solves Boolean expressions (equations). Register R12 in random access memory 69 is reserved for storing the "rung condition flag", register R13 for storing the "branch condition flag" and register R14 for storing the "multiple branch condition flag". In the case of a rung without branches, the register R12 stores the state or the condition of the rung. Register R12 is set to the 1 state upon suspend, and when an XIC instruction is executed, register R12 is set to zero if the checked condition is not met (false). If the checked condition is true, the register remains unaffected so that when all conditions have been checked by a sequence of XIC instructions are true, register R12 remains in the 1 state to indicate that the rung is conductive or true. When an OTE or other similar instruction is then executed, the state of register R12 is checked and used to decide or solve the Boolean expression or equation.

When a BST instruction is executed, the rung occurs a branch on, so that the content of register R12 is transferred to register R13 to the main branch condition to ensure (keep). Register R12  is set to one and the condition of register R14 is set to zero. If another BST command is executed will complete before the previous branch is, the content of the register is ORed R12 with the contents of register R14, and the result is stored in register R14. When a BND command is executed the branch or branches are terminated by that an OR operation of the content of register R12 with that of register R14 and an AND operation of the result with the contents of register R13. The result is stored back in register R12 in order to Continue checking the main branch.

As already mentioned, most macro commands from programmable control units consist of two words. The first word is the opcode and the second is the address of the operand in main memory 34 . For example, in the case of an XIC or OTE instruction, the second word identifies a line in the I / O image table 185 , while the four least significant bits in the first word serve as a bit indicator which identifies the relevant bit in this line or identified. The micro routine executed in the case of an XIC or OTE instruction enables the bit flag circuit 40 to receive this 4 bit flag and to generate a 16 bit mask in the processor channel 30 which is loaded into the L register 57 . The mask consists only of ones, with the exception of the bit which is indicated by the pointer, and when the operand is subsequently read out of the main working memory 34 , it is logically linked in RLE 59 with the mask in order to carry out the desired function. For example, to execute an XIC instruction, an exclusive OR operation of the operand with the mask is carried out, and if the RLE output has all ones, the identified or marked status bit in the I / O image table 185 is "true" or a 1-bit, so that the content of the register R12 remains unchanged. To execute an OTE instruction, the mask is stored again in the L register 57 . If the register R12 is a zero, which indicates that the conditions are not fulfilled, the operand identified in the second word of the OTE instruction is linked in RLE 59 with the mask after an AND function and the result is returned to the I / O A-picture table 185 stored. If the conditions were met or the register R12 is a one, the mask is complemented, reloaded into the L register 57 and linked to the operand after an OR function. The result is saved back to the I / O image table 185 at the same operand address. The micro routines for some more representative commands of the programmable control unit type have the following structure:

The clock commands (TON 0.1, TON 1.0, TOF 0.1 and TOF 1.0) require much more complicated micro routines and use the real-time clock 145 . Like the others, the clock commands also have two memory words. The first word in a clock instruction is the opcode and the second word is the memory address of an accumulated time in a clock counter portion 192 of the main memory 34 . As shown in FIG. 10, this portion of memory between I / O image table 185 and system tag table 182 is stored in relative memory rows 030 through 177 (octal). In addition to an accumulated clock value or time value associated with each clock command, a preset time value or clock is stored in the adjacent working memory space of the memory part 192 , so that a total of four working memory lines are required for each clock command.

According to FIGS. 8 and 11 in particular, the least significant bit of the operation code word indicates the selected time range. When the clock instruction op code has been read into the macro instruction register 37 , this bit is transferred over line 151 to the real time clock circuit 145 , where a one feeds the 5 Hertz clock signal to flip-flop 146 (0.1 Seconds per period) and a zero enables the 0.5 Hertz cycle (1.0 seconds per period). The TIM origin micro-job code causes a 1 signal to be generated on the TIM line 155 , so that the state of the selected real-time clock is switched through to the lowest-digit line of the processor data channel 30 . As can be seen from the description of the micro routine below, the state of the real-time clock is compared with the least significant bit in the accumulated time value. This comparison is made at least once every 10.24 milliseconds, and if the states are different, it means that the real time clock has been incremented or advanced, and the accumulated time value for this clock should also be incremented by one. The micro-routine also checks whether the running time of the clock has expired. This is done by comparing the accumulated time value with the preset time value. A first status bit (number 15) in the preset time value indicates whether the clock is running or not, and a second status bit (number 13) in the same word or value indicates whether the clock has expired. Therefore, if the accumulated time value is equal to or greater than the preset time value, status bit number 13 is set to one so that it can be checked by the commands following in machine-specific software routine 187 . Whether or not a clock must be triggered is determined by the state of the "rung" or the Boolean expression of which it is a part. This state is indicated by the register R12 of the direct access memory 69 and stored as the first status bit in the preset time value. The micro routine for executing the macro commands TON (1.0) and TON (0.1) has the following structure:

The other clock macro instructions are similar executed, although the status bits are in the word of the preset Fair values are used differently. The registers R12 and R13 are used as a buffer in the clock micro routines used, and the rung condition register R12 is set to one at the end of the micro routine so that it can again serve as sprout condition storage means.  

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In summary, it has been shown that a Control processor in a numerical control Control of the control devices of a machine tool in Dependency on a partial or Workpiece program is controlled. The control processor has special hardware and software properties on, which also make it a programmable control unit to control the individual digital devices, connected to the machine tool. The control processor becomes more conventional with one group Computer commands for performing numerical control functions and with a group of commands, like a programmable one Control unit used to carry out machine-specific or machine-dependent logical functions programmed. The resulting facility retains the Capabilities of known numerical computer controlled controls, but also makes them just as flexible and easily programmable like a programmable control unit.

Claims (3)

1.Control processor which both executes workpiece programs as a numerical control for a controlled machine tool and works as a programmable control device which senses the state of individual digital scanning devices assigned to the controlled machine tool and actuates individual digital working devices assigned to the controlled machine tool, with devices for decoding one Workpiece program data blocks and for the dependent setting of a selected memory location in a system identifier table memory to a logical state which indicates that an auxiliary function is to be carried out by digital work devices and for this purpose the control device commands of machine tool-specific routines stored in a routine memory are executed. characterized,
that an I / O image table memory ( 185 ) is provided which has a memory location for each digital scanning device assigned to the machine tool and for each digital working device assigned to the machine tool,
that the logical states of the memory locations allocated in the digital scanning devices are kept at the current machine tool state,
that the logical states of the memory locations associated with the digital work devices are set depending on both the logical state of selected scanner memory locations in the I / O image table memory and the logical state of selected memory locations in the system flag table memory, and then the machine tool status is set accordingly, and
that, depending on the logical state of a selected scanner memory location of the I / O image table memory, the logical state of a selected memory location in the system flag table memory ( 182 ) is set to enable execution of the workpiece program by the numerical Control. 2. Control processor according to claim 1, characterized by
a keyboard ( 7 , FIG. 17) for entering and processing control unit commands in the routine memory assigned to the machine tool-specific software and
a display device ( 9 , FIGS. 12B and 17) for outputting routines associated with the machine tool-specific software from its memory in the form of a ladder diagram. 3. Control processor according to claim 1 or 2, characterized in that the I / O image table memory consists of several addressable words, each containing several bits, and that those control unit commands that check selected bits, and those control unit commands that set the logical state of selected bits, each containing an address that selects a word in the I / O image table memory and a bit hint code that selects a bit in the word, and that a bit hint Circuit ( 40 ) is provided which responds to the bit indication code in the control device command just executed in order to provide a single bit from a word read out of the I / O picture table memory.