DE2743060A1 - DIGITAL COMPUTER - Google Patents

Description

Patent Attorneys D ^: p ^; .-lng. Curt Wallach

Dipl.-Ing. Günther Koch

Dipl.-Phys. Dr Tino Haibach

Dipl.-Ing. Rainer Feldkamp

D-8000 Munich 2 · Kaufingerstraße 8 ■ Telephone (0 89) 24 02 75 Telex b 29 513 wakai d

Date: <_ / ',, bf. ρ ⁴ : *: i:.!. ». ■ "1> 7V

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• 09815/0600

BATH ORIGINAL

DESCRIPTION

The invention relates generally to programmable digital computers and, more particularly, relates to digital computers, in which there is the possibility of processing individual bits that are recorded in words in a memory of the system processed according to Boolean logic.

As such, programmable artithmetic digital computers are available known. "Programmable control devices" are also known and in use, which are essentially single-bit processors operating on Boolean logic. It is true that digital computers and programmable control devices have already been interconnected in such a way that one part of the arrangement can affect the operation of the other part, but such arrangements are complicated and expensive. As far as known So far, no single device is available that is suitable for both arithmetic computing tasks of the usual kind as well as to perform Boolean logic processing, and where it is possible to execute to make programmed arithmetic operations dependent on previously programmable chained processing steps have been carried out according to Boolean logic.

The invention is based on the object of creating a digital computer which not only enables programmable Way to carry out arithmetic and related operations of a known type, but also individual ones Process bits of different words in the system's memory in a programmable manner according to Boolean logic. Furthermore, such a "combined" should be programmable Calculator for arithmetic and logical operations will be created in which it is possible to use several of the hardware parts that

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a digital arithmetic calculator to perform many of the additional functions which enable programmable logic processing, resulting in a computer that can be used in two ways, which is cheaper, smaller and easier to program compared to known computers. Furthermore, it should be the Invention enable the logical processing command address words and the multi-bit words of logic operand signals which can be switched on and off in a memory of the system to record them, to output them as well as to input them, just as if it were conventional arithmetic Command address words or numeric data words. No special memory organization is required here or special control devices, and in fact external devices, e.g. switches or flip-flops, that are used to generate logic bits for input or output signals are treated almost as if they were bits of words represented in a core or large scale integrated storage be kept ready. According to the invention, parts of an otherwise designed in a known manner are also intended Digital arithmetic calculator used to participate in performing programmed logical processing of a single bit, the program steps for the logical processing being essentially random can be nested with the program steps for arithmetic functions. Thus, a "combined arithmetic Computer and logical processing arrangement "created regarding the total computation options, the flexibility and the ease of programming is superior to an arrangement as it is better known in a simple combination of a digital computer Art would result with a programmable controller of known type. In this sense a "combined Computer and processor "are created in which the execution and the result of arithmetic steps qualify and from the result of previously performed programming

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the single bit steps can be made dependent according to the Boolean logic.

Furthermore, a "combined computer and processor" is to be created in which it is possible to concatenate the result Boolean logic operations on any bit of different words in the system's memory "store", regardless of whether these words are held in an ordinary memory, e.g. in memory cores , or in external devices, e.g. flip-flops for controlling motors, valves and the like, wherein This mode of operation can be achieved by simply programming the "input" of a logical result in a selected bit a selected memory address can be achieved. In connection with this, a digital computer is to be created that it enables a logical response signal to a selected bit of a selected one as a function of coded command words To transmit a word in the memory or to carry out an "intermediate storage" or alternatively from the selected bit of the selected word to make a 1 (set), an O (reset) or the opposite signal (invert). Furthermore, it should be made possible according to the invention, the trained in a known manner instruction address register Digital computer of known type to use to receive instruction words, by means of which conventional arithmetic Functions are required, as well as special command words to be included for the execution of functions according to the Boolean logic apply. In the latter case, certain bits of the output signal of the command address register are decoded, to generate logic signals that determine operations, with certain other bits serving to define a certain Bit of a word to be selected as a logical operand, and further other bits are used as an address to a Bit containing word to choose and to take it from the memory. Furthermore, according to the invention, the known

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Wise designed arithmetic input registers of an ordinary digital computer are used to receive a data word, since ^r ; contains a desired logical single bit operand, and to supply from the register from an input of a processor for operations according to the Boolean logic the relevant operand bit of said word, which is determined by the combination of certain bit signals from the instruction address register and contains a special logical instruction. Finally, in a "combined computer and processor", economical use of the hardware should be made possible by means of a device which normally responds to an arithmetic instruction of the usual type, but which reacts in a different way to a special logical instruction code format, the bits of the Both types of commands are present in the same number, but the binary bit selection signals containing the special command are present at predetermined bit positions.

According to the invention, this object is achieved by creating a Digital computer solved, the structure of which is expedient and relatively simple, which is not only suitable for conventional arithmetic To perform operations according to a program, but rather which enables 1. concatenated processing steps according to the Boolean logic for any selected bit of any of different selected words held ready in the memory, 2. the result of the logical processing to utilize by the fact that the result at any selected bit position within any of the various to store selected words recorded in memory and / or 3. to cause the execution of various predefined under commands within a program according to the Results of previously performed logical single-bit processing steps, and in which the logical processing takes place as a function of command words encoded in a special way, which within a Qesamtprogramm randomly with the

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Instruction steps for the conventional arithmetic operations can be nested. Existing registers and device parts are used to a large extent are required for conventional arithmetic operations in order to supply or extract signals from the logical processor, and very little additional hardware is required to do the logical processing that does To effect storage and the creation of the aforementioned dependency.

An embodiment of the invention is explained in more detail below with reference to schematic drawings. It shows:

Fig. 1 is a generalized block diagram of an inventive Digital computer in which the main parts that are related to one another partly correspond their structure and on the other hand are shown according to their function;

2a and 2b as a whole than FIG. 2 shows a more detailed block diagram a digital arithmetic computer which is suitable for logical processing steps according to the Perform boolean logic;

Fig. 3 is a more detailed block diagram of the also in Fig. 2a shown instruction address register;

FIG. T * shows the structure of a direct decoding circuit which is only indicated schematically in FIG. 2a;

5 shows the structure of a phase sequence generator and a main clock generator, which are only indicated schematically in FIG. 2a are;

6 and 7 waveforms plotted against time for comparison

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illustration of various 'Jignale' in the Computer arrangement occur during operation with certain command sequences;

Fig. 8 is a circuit diagram to illustrate / ^ the connections between the phase sequence generator and a read-only memory for generating encoded input signals for a microprogram read only memory;

9 shows the block diagram of a microprogram read-only memory and the associated decoders for generating different combinations of control signals at different times depending on the Processing various commands;

10 is a detailed block diagram of a Boolean logic processor used for Implementation of the invention is suitable and indicated only schematically in FIGS. 1 and 2a;

FIG. 11 shows a functional block diagram of an exemplary embodiment for a system memory which is shown in FIG. 2b is only indicated schematically; and

12 is a fragmentary block diagram illustrating the manner in which certain words of the system memory are generated with the aid of external hardware components such as switches and flip-flops, each of these hardware devices representing a logic bit that can be sensed or a logic bit; which can not only be felt, but also put into one or the other of two possible states.

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In the following description, reference is also made to Tables I to VII, which supplement FIGS. 1 to 12 serve and are attached at the end of the description for reasons of expediency.

1. Introduction

In Fig. 1 is an embodiment of an inventive Digital computer shown partly according to its structure and partly according to its mode of operation. First, consider the programmable basic system for arithmetic digital computing processes; to a central unit CPU includes an arithmetic unit 100 and a control unit 200, which is connected by a rail 10 with multiple lines a read and write system memory 300 are connected. The memory 300 is formed in a known manner, i.e. it has multiple storage locations for receiving, holding, and reporting multi-bit words with each bit one of two Values, i.e. the value 0 or the value 1. Each multi-bit word is stored in a location that is indicated by a unique address is designated. Some of the words stored in memory are arithmetic Command address words which, by their special nature, form a software program that is stored in memory prior to the start of the Arithmetic operations can be entered. In contrast, some of those in memory are others Convert stored words to numeric data words that are used in sequential arithmetic calculations or as a result of which can be used and / or modified. These command words and the arithmetic data words are shown in FIG 300a and 300b, respectively, in order to show that they are of fundamentally different types.

The control unit 200, to which a clock generator and a program counter are not shown in FIG ₌ 1,

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is used to sequentially execute successive commands of a program and the various facilities control within the entire recimer during each a step is performed which is indicated by a command word. You could use the digital computer and his Build control unit 200 in a known manner so that it is possible to use several in dependence on a single command Perform work sequences such as addressing an index, double precision calculations, and multiple steps extensive calculations such as multiplication, division or taking the square root, but is the one to be described below arithmetic calculator only for the sake of simplicity and brevity depending on the implementation of a work sequence limited by each command word. Thus, for the purposes of the description to be given, it can be assumed that the Control unit 200 causes the computing system to go through successive sequences of operations if it is successive retrieves and uses any command words. In one type of such operations sequence, the control unit performs Address signals over the multi-conductor address rail 11 to the memory 300 to cause it to write a command address word from the desired memory location to the rail 10 so that the desired command address word in the Control unit is transferred.

The control unit then sends the address contained in the command word called up to the memory 300 via the rail 11 to in order to cause the memory to read the data word from the address memory sections via the rail 10 of the arithmetic Unit 100 to be fed. The control unit 200 then carries out signals which are derived from the command part of the retrieved word are, via a line path 13 to the arithmetic part 100 in order to cause it to carry out the corresponding function, e.g. the supplied number data word to a previously add the word entered to the arithmetic unit or

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deduct from it.

The results of a sequence of arithmetic calculations that use consecutive data words as operands can be routed back to a specific address location in memory to be used at a later time used or given to external institutions. In the case of a "storage operation" of this type, a retrieved Command address word the control unit 200, the arithmetic unit 100 via the conduction path 13 a command signal so that the arithmetic unit sends its arithmetic answer word accumulated up to that point to the rail 10 outputs, whereupon the control unit causes the memory 300 to store the bits of this' continued as they are in the Rail appear in a location corresponding to the address represented by the fetched instruction address word is equivalent to.

These arithmetic operations, which are treated here only with the utmost briefness and which are discussed in more detail below, enable successive arithmetic operations to be carried out (e.g. addition, subtraction or division), and the result obtained is stored again in the memory to be used at a later point in time or to be output via an external device such as a cathode ray tube, printer or the like. Just to give a simple example, let us assume that a short numerical calculation process is carried out as a function of a previously introduced program, the program comprising the following steps: a) Extracting the number A from memory location 124, b) Adding the number B from storage location 126, c) subtracting number C from storage location 130, d) dividing the result by 2, and e) storing the result in storage location 140 where it can be viewed as number D. Each such numeric or ^w data "number is written in binary

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wise at the different bit positions of a numeric data word represented by a 1 or a 0; each command word is made up of a similar number of two-valued bits together, which are contained in the memory in a specific address, with a first group of the bit values in a predetermined Code format denotes the type of operation to be performed in question, and a second group of the Bit values in binary notation denote the number of the memory address at which the operand (or the arithmetic Answer) can be found or saved in the system's memory.

For numerous applications programmable alphanumeric? Digital computers and especially when processes or machines should be controlled depending on changes in perceived values or changing conditions, so that the values of variable quantities calculated step by step are changed, it is desirable to have numerous switches that can be switched on and off Devices, e.g. limit switches, safety pressure switches, motor contactors and the like, to be scanned in order to detect logical Way of determining whether the combination of their states has a predetermined relationship, i.e. a Boolean equation, and switch certain external devices on or off if the conditions are not met. Instead of programmable control devices are already used by switches and relay circuits. For example, if four switches S1 - S4 and a relay R1 for controlling a motor for driving a coolant pump are present, it can be at a specific one Control device may be desired to turn on the motor when and only when the switch S1 is closed, or when switches S2 and S3 are closed while switch S4 is open. The following Boolean equation would do this are valid:

S1 + (S2 + S3) * STf = R1

Each switch can be viewed as a bit of a word in memory, with the bit as a binary value either has the value 0 or the value 1 when the switch is open or

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closed is; the relay can be viewed as a stored bit that should be set to 1 when the conditions of the above equation are fulfilled, and that should be set to 0 (switching off relay R1) if the conditions of the equation are not met.

As shown functionally in FIG. 1, the memory 300 contains special address memory parts 300c in some of its address memory parts logical command address words. Furthermore, the memory can contain logical multi-bit data words 30Od. Becomes a certain Program step reached in which a special logical command word is called up and supplied to the control unit 200 is to be, the control unit decodes the command part of the multi-bit word, so that a logical operation code which is fed to a logical processor 400 via a line path 14. The control unit also reacts 200 to the address part of the special logical instruction word called up in order to transmit address signals via the rail 11 so that the memory 300 is caused to supply the rail 10 with the data word corresponding to the address. Though the data word is fed to the arithmetic unit 100, but the latter does not have any operand with regard to this word arithmetic function. Rather, a bit selection code is created by a specific bit group of the command words retrieved is fed to the arithmetic unit 100 via a conduction path 15 to cause a selected Bit signal of the data word via the line path 16 as a single-bit operand input signal LB to the logic processor 400 is fed. Then the processor merges a function with respect to the operand according to the Boolean logic with every pre-existing logical answer LA. These logical functions include, for example, the functions LOAD, AND, OR and XR. The logical result LA is fed in inverted form as signal LA "via a line path 17 to the control unit 200,

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the operation of the control unit under certain conditions to modify in a manner yet to be explained. Keep the logical result LA and its inverted form EA * their respective fixed binary values of 0 or 1 until they are commanded by another logical processing operation to be changed.

A method of using the logical response signal LA after it has been generated by one or more concatenated ones Boolean operations consist in storing the signal in a selected bit position of a selected word in memory will. This process, referred to herein as "caching", removes it from storing an arithmetic to differentiate calculated result is carried out depending on a special logical command word, which is called up from the memory 300 and supplied to the control unit 200. The operand word, which the desired Bit is then transferred from the memory 300 to the arithmetic unit 100, and the bit address code part of the retrieved word causes the selected bit value of the operand word via the line path 16 as the signal LB dem logical processor 400 is supplied. With the help of facilities yet to be described, the logical processor uses the input signal LB in connection with the already existing logical response signal LA for generating a bit control signal BC. The signal BC is fed back to the arithmetic unit via a conduction path 18 and also to a device which causes the original operand word along with the selected bit, which is forced, with the logical result LA match, is entered via the rail 10 to the memory 300 at the memory location which is identified via the address rail 11 by the address bits of the instruction originally fetched.

In addition to the operations described above, any

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Word can be extracted from the memory 300 and transferred into the arithmetic unit 100, specifically as a function from a special logical command word which is called up and supplied to the control unit 200 and which designates the function, that a selected bit of a predetermined word is forced to assume the value 1 (SET) or the value 0 (RESET) or to change into the opposite state (INVERTIEREK) before the operand word returns to its original Address location in memory is returned.

The foregoing brief introductory explanation with reference to FIG. 1 shows in a very general way how it is with The aid of a few additional parts in an arithmetic calculation system constructed in a generally known manner according to FIG of the invention is possible to perform programmable logic processing. More details of the structure and the mode of action and the achievable advantages emerge from the following description of further details.

2. Basic structure of the arithmetic system

According to FIGS. 2a and 2b, the system memory 300 includes output lines 301, which can be connected to rail 10 of the system when a multi-bit gate Gmr is actuated, in order to input the signals to the rail 10 which correspond to a word stored in a certain position. The word storage location is selected with the aid of numerically coded signals which are fed to the address rail 11 at the respective point in time and the reading process is initiated by a control signal MEM. Conversely, the input lines take 302 the memory 300 always receives signals from the rail 10; the supplied signals are stored in a memory address, which is designated by signals supplied via the address rail 11, but only if a Enable or write signal BTM 'of the memory control circuit

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is fed. By entering a word with 10 bits the content previously stored there is deleted in a specific memory location.

In order to avoid unnecessary details which would only impair an understanding of the invention and its advantages, a highly simplified embodiment of a typical arithmetic computer system is described below. It is assumed here that the system memory 300 is designed in a known manner as a core or large-scale integrated memory mic only 1024 word address locations, each word having a length of 16 bits. The input lines 301 and the output lines 302 each have 16 conductors, and the rail 10 also contains 16 conductors, so that at any point in time 16 bit signals can be transmitted which represent a word. Rail 11 includes 10 conductors, and the combinations of voltage values 0 and 1 that appear on these conductors allow each address of a decimal value from 0 to 1023 to be represented in binary notation. If signals appear in the address rail 11 'which represent the decimal value 285 in binary notation, it can thus be assumed that the word at the address position 285 is transferred from the memory to the rail 10 when the read signal MEH is present; otherwise, a new form of the word is entered via the rail 10 of this address position when the write signal BTM ¹ is present. Of course, the memory and the rail could be expanded to 18 bits per word to enable parity checking, but this known refinement is omitted here to simplify the description.

The only existing rail 10 in the system can receive signals from one of several sources will. If one of the gates Gmr, Gad, Gr or Gatb is enabled, the signals are sent to memory 300, the address rail

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11, an exclusive 0DER arrangement 106 or an accumulator 104. It is thus possible to supply the rail 10 with bit signals of a multi-bit word in each case from the device through which one of these gates is fed. The signals fed to the rail 10 in its lower run along the edge of Fig. 2 may be amplified by a rail amplifier 12 before reaching the portion of the rail shown in the upper part of Fig. 2, but is only one only rail 10 available for the entire system. Signals applied to the rail can each be "accepted" by any of a number of devices provided with presetting input terminals connected to the conductors of the rail, but only if the device in question receives a pre-set enable signal ¹¹ The manner in which such enable signals are supplied to an arithmetic input register 102, an instruction address register 202, a program counter 226 or the memory 300 will be explained below Rail signals to be fed in parallel to it and to be stored is enabled when an enable ^{signal AIR 1} , which is taken from a logic UIiD circuit 101, results from the fact that two signals AIR and CLK both have the value 1.

The arithmetic unit 100 shown in FIGS. 2a and 2b is shown in a greatly simplified manner, the arithmetic input register 102, also referred to as AIR, belongs to which it is an i6-bit 3 storage register known commercially Art acts. The output of the register 102 leads to a 16-bit input B of a known commercially available arithmetic logical unit ALU with a second 16-bit input A. The unit ALU carries out an arithmetic or logical treatment or a combination of the two 16-bit input signals A and B

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corresponding to that of several command input terminals that can be used as required, each of which has a release voltage with the value 1 is supplied. The result appears in the output lines of the ALU unit in the form of a 16-bit result signal F. It is true that the unit ALU can receive additional command signals and other arithmetic or logical signals Perform operations on signals that are supplied through either or both inputs A and B, but will In the following, only five arithmetic logic functions are described for explanation, each of which runs when an enable voltage is supplied to one of the five control terminals on the right-hand side of the unit ALU according to FIG. 2a. V.'ird the commanded function is enabled by a signal A, F = A applies; if a function is commanded by signal 3, the following applies F = B; when the command signal B "is supplied, F is equal to that Input signal B with all bits inverted; Consequently F = B "; if the signal A + B is supplied, the output signal is F equals the sum of the two numerical input signals A and B; if signal A-B is supplied as command, then applies F = A-B.

The output signal F of the unit ALU is the input of a Accumulator register 104 with an output ANS for 16-bit output signals fed. If the accumulator receives a "standard release signal" ACC, the output signal F is passed to the accumulator register 104 to be stored so that it thereafter when the response signal ANS appears. It should be noted here that the output signal ANS of the accumulator 104 is fed back over a 16-bit rail 105 to the input signal A to form the unit ALU. In addition, the output signal ANS of the accumulator is sent via the gate as required Gatb fed back when this gate is enabled by a signal ATB, so that the output signal is on a yet to be explained Way of the rail 10 can be fed.

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In the case of an arithmetic unit of known type, it is ensured that in some operations it is possible to feed the output signal F of the unit ALU directly to the rail 10. According to the invention, an alternative or second response signal ANS · is generated by a 16-bit exclusive OR arrangement 106, to which the signal F of the unit ALU is fed via one input and a 16-bit control signal H is fed via a second input. If an enable signal EOR is fed to the gate Grs, the output signal ANS ^{1 of} the exclusive-OR arrangement 106 is transmitted to the rail 10. This arrangement makes it possible to feed the signal F of the unit ALU directly to the rail 10, bypassing the accumulator 104, when the signal H consists only of zeros, so that the signal ANS ^{1 is} equal to the signal F. If, on the other hand, the signal H consists only of ones, the signal F appears in the inverted form, ie as the one's complement to ANS ·. The signal H is generated by a control circuit 404 to be described later.

It should be noted that the accumulator 104 can also be caused to determine the multi-bit word it contains To perform operations. For example, Fig. 2a shows that the accumulator 104 under certain conditions to be explained a command signal SACR or SACL or CLR can be supplied. If these command signals are supplied, this becomes The multi-bit word contained in the accumulator is shifted one place to the right or it is shifted one place to the left shifted or all positions are brought to zero, i.e. the accumulator is "deleted". It should be noted that a shift a binary number held in the accumulator by one digit to the right or by one digit to the left The effect is that the displayed numerical value is multiplied by 2 or divided by 2.

The previously described mode of operation of the arithmetic

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Systems is known, but it will be explained in the following using a very simple example. It is assumed that the accumulator 104 has been cleared and that a first number N1 is entered in the register AIR so that it is supplied to the unit ALU via input B, while an instruction A is supplied to the unit ALU. The number N1 then appears as the output signal F of the unit ALU. If the "3 memory release signal" ACC is now generated, the number N1 is input to the accumulator 104 so that it appears as the response ANS, the signal N1 being present at input A of the unit ALU. _V Now a second number ΓΙ2 from the rail 10 into the register 102 via leads, so that it becomes B of the ALU to the signal at the input, while this unit is supplied with a command signal A + B, the output signal F to the sum I J1 is + N2 of the two numbers. A signal ACC (storage in the accumulator) causes the signal F = N1 + H2 to be stored in the accumulator 104 so that it appears at ANS and becomes a new value at input A of the unit ALU. As soon as a number N3 is then supplied from the rail 10 from the input B of the unit ALU, while a signal AB is supplied to the latter, the output signal F assumes the value of the algebraic sum H1 + N2-N3. A storage release signal ACC ¹ transfers this value to the accumulator 104 so that it appears at the output ANS. If the gate Gatb is now enabled to apply the signal ANS to the rail 10, the result N1 + N2 - N3 of these concatenated arithmetic calculations appears on the rail 10, from which it can be transferred to memory or otherwise used . The subtraction of two numbers requires that the binary two's complement of the subtrahend is formed in the unit ALU, and that this subtrahend complement is added in binary to the minuend; these details and the processing of negative numbers are known, so no further explanation is necessary.

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The 16-bit Exclusive-OR arrangement 106 alternatively serves as the Means for transmitting the output signal F of the unit ALU to rail 10, either in its "true" form or in its one's complement form. With every pleaseil The arrangement 106 is a simple exclusive-OR gate which is established in a known manner according to the following Table of values works.

Exclusive 0DER gate

entry
fh 0 exit 0 1 0 0 0 1 1 1 1 1 0

With the above relationships in mind, it can be seen that if all the bits of the multi-bit input signal H of the array 106 are enveloped, the output signal ANS ^{1 will} simply be identical to the multi-bit output signal F of the unit ALU; if all bits of the multi-bit input signal H are made ones, the output signal ANS ^{1 is} the one's complement of the signal F, ie it corresponds to the signal F, all of its bit values being inverted. A corresponding influencing of the signal H and the release of the gate Gr by a signal EOR therefore makes it possible to supply the signal F to the rail 10 in its true form or in its complementary form.

Can be the accumulator 104 and a total of the exclusive-0R assembly view 106 as an arithmetic output register AOR, because the rail 10 can be fed from an output signal ANS or ANS _o ¹ of two devices _o

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In the basic arithmetic system, the arithmetic unit 100 is sequentially operated by a controller 200 controlled, welcbi provides the necessary timing and command signals. The controller 200 can be viewed as as if the instruction address storage register 202 belonged to it, which, as required, was provided by the output signal IAR ' an AND circuit 201 is enabled to receive signals from the rail 10. This register essentially receives always command address words and not data words, and it is treated as if it had two main parts, accommodate the first and second groups of bits, respectively, which form command words in a known format. The first group represents in coded form a desired operation or instruction, while the second group usually represents the Represents the memory address of a data word that is to be extracted from the memory as an operand, or in which a Calculation result is to be saved.

To give a simple but concrete example, Table I shows that a basic arithmetic instruction address word has a format which for the purposes of description will be assumed to be sixteen bit positions bO to b15, the first ten digits being binary Contain address values that represent any memory address from 0 to 1023. Bits b10 to b15 are coded so that they each designate one of several possible commands, e.g. LDA (load accumulator), ADD (operands for the currently add the number contained in the accumulator) or SUB (subtract the operands from the number currently contained in the accumulator) . To complete the description, a typical set of possible commands is given below treated.

According to one feature of the invention and one yet to be explained The purpose of the basic command address word

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format of the table I the bit position b1O is used by a 1 or 0 to indicate that it is an "unconditional" or a "conditional" command. That leaves five Bit positions b11 to b15 for receiving binary bit values 0 or 1, which are denoted by I in Table I, and which are after a preselected code can each designate one of 32 possible commands. To shorten the description, the size is of the system memory as well as the number of possible commands. For a computer to be launched on the market Of course, there will be more than 1024 memory locations, and the computer will be designed to have a considerably larger Can handle a number of commands, including some, many microprogrammed to carry out Steps are required.

From the fourth line of Table I it can be seen that a basic data word is only a binary representation of a numerical value is available. The combinations of zeros and ones at the bit positions bO to bi4 make it possible to to represent any desired decimal numerical value between 0 and 32767 in binary. The last bit position b15 is used by means of a 1 or a 0 to represent the sign of the number. Generally speaking, data word numbers with this format are the arithmetic input register 102 and not input to the instruction address register 202.

Fig. 3 is an enlarged view of the instruction address register 202, on the basis of which more details are given. Each of the bit positions of this memory register is, for example, a toggle circuit formed, which is set or reset when the command word taken over from the rail 10 at the corresponding Bit position contains a 1 or a 0. The 16 output lines of the command address register are indicated in FIG. 3 by iO to i15 designated; Furthermore, complement signals TT5, ΪΤ5 and ΓΤ3 * the three flip-flops at the left end of register 202

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took. Comparing Table I with FIG. 3, it can be seen that if the instruction address register 202 has a basic Command address word is entered, binary signals representing the address in the output lines iO to i9 appear while commands are in the output lines i10 to i15 Representing binary signals appear, but the signal in the output line i10 has a special meaning Has.

According to FIGS. 2a and 2b, the address bit signals contained in an instruction address word in the register 202 become are, normally via a rail 204 from the output lines iO to i9 from the input of a 2: 1 hultiplex gate 205 supplied. If this gate is enabled by a control signal EA, it is supplied via the lines iO to i9 Input signal OA supplied to memory address rail 11 to designate the memory location from which a word read out or where a word is to be entered. The lines OK to i5 constantly carry signals for the 10-3it input OA, and the signals from lines i6 to i9 are normally released via an F, which is used for masking AND gate 206 passed to form the remainder of the signal OA. Under certain, yet to be explained Conditions, the masking gates 206 are disabled in order to effect a masking and the signals at the bit positions b6 to set b9 of the 10-bit input signal OA to 0. At this It can be assumed that the input signal OA is formed by the signals that are present in all register output lines OK to i9 pending.

The command bit output lines iiO to i15 are one Rail 208 combined to form a direct decoding circuit 209 and a card formation read-only memory 210 leads. These lines are used in these facilities to ultimately determine the type of operation that will be performed

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during each part of a phase sequence which occurs after the arrival of any command word in the register 202 is carried out.

If an instruction word in register 202 contains an instruction code by means of which the use of an operand from the memory is required the direct decoder circuit 209 sends a GETOP (operand fetch) signal to a phase sequence generator 212 arrive to cause this to sequentially phase signals PHO, PH2 and PH3 to be generated, which are time-dependently generated by a signal CLK! a master clock and timing generator 214 being controlled. If, on the other hand, an instruction word in register 202 contains an operation code in which the use of a Operand is not required, the direct decoder circuit 209 does not generate the signal GETOP, and the phase sequence generator 212 then sequentially generates only the phase signals PHO and PH3.

As explained below, the read only memory 210 is during activates the execution phase PH3 of each operational sequence; it decodes the command bit signals from the output lines i11 through i15 to encoded 4-bit microprogram input signals to a microprogramra input rail MPI. During phase 0 or phase 2, i.e. when the signals PHO and PH2 are pending, the read-only memory 210 is out of order and the required microprogram input signals are from the phase sequence generator 212 is fed directly to the rail MPI.

The rail 1-3? I leads to the four control input terminals Xa, Xb, Xc, Xd of a microprogram read-only memory 220. This read-only memory is practically a permanently connected one Coding matrix, which is dependent on 16 possible input signal codes in lines Xa, Xb, Xc and Xd Output signals in various combinations of 15 output lines M1 to H15 shown in FIG. 9 appear

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? IU 3 ϋ ί ^: Ο

are. These 15 lines are in different "field groups" divided in Fig. 2b with ADDR, BUS, ALU, STOR, MISC and IPC are divided. The signals in the ADDR field designate the source from which through their binary code combinations Signals of the memory address rail 11 are to be fed. The signals in the BUS field denote by their binary combinations the source from which signals are to be fed to the system rail 10. The signals in the ALU field indicate through their binary code combinations, the command that is to be fed to the unit ALU in order to cause it to perform an operation of a desired type on their A and B input signals. The signals of the field With their binary code combinations, STOR denote a device or part of the system in which signals are to be saved from the system rail 10. The signals in the field denote HISC by their binary code combinations each one of several possible different control signals that is to be generated. The signal of the field IPC, which consists of a single signal appearing in a single line, denotes when it is present is that the program counter 226 is to be incremented.

The field group output lines of the microprogram read-only memory 220 lead according to FIG. 2b to associated field decoders FD1 to FD5. These are simple decoders, each causing an output signal to appear in one of several output lines, the output line in question corresponds to the combinational code of the input lines to which binary signals with the value 1 are fed will. According to FIG. 2b, the decoded address field signal can be a signal PC or a signal EA. Correspondingly, the decoded signal of the BUS field has one of the meanings ADTR, MEM, ATB or EOR. The decoded signal of the ALU field can appear in one of five lines,

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which have the designations A, B, B ", A + B and A-B. That The decoded STOR field signal appears on one of six possible decoder output lines while the decoded The MISC field signal appears in one of five possible output lines.

It should be noted that the STOR and MISC are provided with a gate control. This means that all output signals of these fields are held at the level 0 when a control signal K is supplied by a conditionally operating control device 403 to be described is switched from its normal value 1 to the value 0.

Finally, the control unit 200 includes a program counter 226 which, in a known manner, is used to track the entire system to switch from one program step to the next during operation. The program counter can handle 10 tandem flip-flops that generate binary output signals which decimal values are represented from 0 to 1023, and which are forwarded via a rail 228 to the 10-bit input signal PA for the multiplex gate 205 to be formed. If this gate is released by a signal PC, it transmits the output signals of the corresponding to the input signal PA Program counter 226 to address rail 11 so that system memory is instructed to use the word of the address concerned and output it via the output lines 301 or to store the signals appearing on input lines 302 at the appropriate address location. The program counter 226 is normally indexed to sequentially move from one counting state to the next; This Switching takes place depending on the positive transitions of pulses INC that are sent to the counting input of the Program counter are fed. The switching pulses are generated by an AND circuit 230 which is controlled in a manner to be explained.

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v-9

- ■? 7 AJ,:, J

Alternatively, however, it is possible to set the program counter 22f> beforehand to a desired counting state, so that its output signal ΡΛ assumes a specific numerical value. This is possible in a known manner with the aid of a presetting ^{signal PPC 1} from an AND circuit 231, by means of which the counter 226 is set in accordance with the signals which are then present in lines b0 to b9 of rail 10. Furthermore, the program counter can be cleared or reset to zero when the system is put into operation, specifically by a switch-on or start pulse PWRS, which is generated by a device (not shown) when all parts of the system are energized.

3. Special word formats

As mentioned, a basic instruction address word is τ corresponding to the first row of the table set up so that the binary ^T .7erte of 10 bit positions, that the bit positions designated by A, representing an address, while the values in the six bit positions I and U / C denote a specific operation ordered. According to the invention, however, devices are present which respond in a unique manner to one of several "special" command address words, specifically to those by means of which the logic processing or handling of a single selected bit of a single selected bit of a selected word in memory. Although the basic and special command word formats described here are only intended to illustrate the basic idea used, and other equivalent formats could be selected to achieve the same results, Table I shows the format of a machine language command code by means of which single bit operations of various specific types are determined . It should be noted that a "logical process command" at the bit positions b0 to b5 (denoted by A in Table I)

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η u 3ue; u

represents the address of an on-edge word, ie a selected word from which a selected bit is to be used. In the case of each such "logical process command" in word format, the binary values B, which appear at bit positions b6 to b9, designate a number between 0 and 15 in binary format, which identifies the desired single bit to be selected from the selected word and to be used in the various possible logical operations. Finally, the special format of a "logical process command v / orte s" contains the binary values labeled I and T / C in the bit positions b10 to b15 which, according to a previously defined code, indicate the type of logical function to be carried out ( e.g. UIiD or OR). As explained in the following, the binary value which appears at bit position b10 of a "logical process command word ¹¹ " is used to indicate whether the selected single-bit operand is to be used in its true or in its complement form during the signals denoted by I at bit positions b11 to b15 designate the operation to be carried out in each case.

There are two main types of single bit logical operations. In the operations of the first kind, of which four are possible various special operations, the selected bit signal is used as the input operand for the logical processor used. In operations of the second type, which also include four different operations, the logical answer LA stored in a selected bit position in a selected word of the memory, or the selected one Bit is brought into a desired state. Operations of the latter type are hereinafter referred to as "bit manipulation" designated. According to Table I, a "logical bit manipulation command address word" the same format as a "logical process command word" except that the U / C The designated bit at bit position b10 indicates whether the operation to be carried out is a conditional or an unconditional one Operation is. According to Table I, this means

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27A3ÜUÜ

Signal U / C for the logical bit management command word just as with the basic command word that if a 0 or a 1 appears at bits + elle b10, the Command represented by the entire word regardless of the value of the logical response signal LA to unconditional Is to be carried out in a conditional manner, i.e. only if the signal LA has the value 1.

Logical single bit operations can be performed on a selected bit of a common alphanumeric data word. For example, with the numeric data word format according to Table I, it is possible to check the single bit signal at bit position b14 and use it as an indication of whether the total numeric value of the whole word is greater than the decimal value 16,384 or not. In addition, the signal at bit position b15 of a numerical data word can be selected, for example, in order to indicate whether the numerical value is positive or negative. In some cases, however, it may be desirable to have a large number of unrelated single-bit signals available to use and / or to change during or through logical operations. A feature of the invention is that some words held at known addresses of memory 300 of known nature can each simply represent sixteen individual two-state or on / off values. Although these memory words are "data words" in the true sense of the word, their individual bit signals do not designate any numerical value as a whole. Such a data word, which contains individual _{logical bits labeled Q Q} to Q ₁₂ , is shown in Table I as a "logical bit word". Words of this kind can be entered into the memory as if they were ordinary numerical data words, and individual bit signals can be detected or changed in a manner to be explained. They actually need some of the logical bit words that are held in memory

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not in conventional core or large scale integrated storage elements to be saved. They can be signals that retain the value 0 or 1, depending according to whether corresponding associated individual switches are open or closed, or they can control the output voltage of flip-flops that can be set or reset to turn external devices on or off switch off.

4. The logical processing elements

According to the invention, a few relatively simple elements are added to the basic arithmetic system to produce a programmable logical single bit processing and a possibility of manipulation and to make it possible to program any ordinary command to work accordingly executed unconditionally or only conditionally based on the results of previously performed chained Boolean single-bit operations will. 2a shows a logic processor 401 which essentially performs two types of operations on a single bit operand input signal LB executes. It "loads" the signal LB by bringing the signal LA into agreement therewith, or it links the signal LB according to an AND, OR or Exclusive OR function with the existing logical response signal LA, which changes the latter to match the result of this operation. Used alternatively the processor 401 the operand input signal LB to generate a bit control output signal BC which is used to to cause the selected bit in the selected word to match the logical answer LA or a specific one take the desired value from the two possible binary values.

In order to give the logical processor 401 instructions regarding the particular operation to be performed (as a result of a

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particular instruction address word fetched into register 202) is the direct decode circuit 209 designed to provide the processor with five input signals LO, L1, L2, COMP, i12 and H4. Hit help the particular combination of the pending signals becomes a certain one logical function commanded to be eight different possible functions. The signal COIiP informs the Processor 401 whether the input signal Lb in its true or its complement form is to be processed logically. In the present description, the symbols "point", + and © used according to the well-known Boolean algebra to the logical operators "UTID", "OR" and "Exclusive-OR" describe; ("x and y" has the notation x «y," x or y " the notation χ + y and "x OR y" the notation x @ y). The eight remaining possible logical functions are in the Table IV compiled, where the abbreviations given have the following meanings.

LD: enter the selected bit into the logical accumulator to

Bringing LA into line with it. AN: Make LA equal to LA * LB (LA denotes the "old" ; / ert of IjA and LA the "new" or resulting value

from LA).
OR: Make LA ^ equal to LA ^ + LB.

XR: Make LA ^ equal to LA ^ (+) LB.

η ° ο

_n equals LA _o

SV: Signal LA at the selected bit position of the selected word

cache.
IV: The 'inverted' complementary form of the selected bit signal LB again at the selected bit position of the selected word

to save.
ST: The signal at the selected bit position of the selected word

set to the binary value 1.
RS: Resetting the selected bit of the selected word to the binary value 0.

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Table IV shows that a five bit code LO, L1, L2, ii4, i12 allows it to pass in a unique manner the combination of binary values of the five signals to represent eight possible special logic functions, so that opcode signals, which determine which way the logical processor 401 is to operate, the processor from the direct decode circuit 209 are supplied from, the code being based in each case on the command bits that are in the lines i11 to H5 of register 202 appear. Below will 10 explains in what way these opcode signals the specific operations of the logic processor 401 determine.

Referring to Figure 2a, a 16: 1 bit selector 402 extracts the LB signal the selected bit position of an operand word, which is selected and entered into the arithmetic input register 102 has been. For this purpose, the "bit identification signals" of a special instruction word which has been fetched into the instruction address register 202. These four Signals that are labeled B in Table I and appear on output lines 16 to 19 of register 202, represent any decimal value from 0 to 15 in binary notation and thus one of the bit positions b0 to b15. The bit selector 402 has 16 input lines, the are formed by the output lines of the arithmetic input register 102. When the decimal value of the four signals B has a certain value in the range from 0 to 15, the single bit signal from the register 102 is at its corresponding Bit position b0 to b15 transmitted in such a way that it is the logical Operand signal LB appears. For example, if the signals on lines i6 to i9 have the binary values 0101, this will be The signal from bit position b5 of register 102 is transmitted so that it appears as the single bit operand signal LB. Have the output signals of the register 202 the binary values 1011, the signal from the bit position b11 of the register 102 becomes

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the signal LB. Such 16: 1 multiplexing circuits are known and are commercially available, so no further explanation is required.

Whenever the logical answer LA is to be stored in a selected bit position of a selected word, or when the selected bit is to be processed in another way (according to the instructions IV, ST or RS), the arithmetic unit 100 is used to do this process entire selected word. The location is input to the arithmetic input register 102 so that it becomes the input signal B of the unit ALU, to which the latter the command signal B "is applied to make the signal F coincide with the one's complement of the word. The input signal is caused H of the exclusive OR arrangement 106 consists only of ones, the output signal ANS 'is the inverted form, ie the one's complement of the signal F and is therefore identical to the originally selected word Signal H contains that the corresponding bit of the signal AUS 'is inverted with respect to the value of the corresponding bit of the originally selected word. Then the signal ANS ¹ can be stored again in the memory at the originally selected word position.

To perform this selective bit reversal when executing the special logic commands SV, IV, ST and RS, the signal BC is applied as an input to means 404 for controlling the selected bit, which is is a 1:16 multiplex gate, which as required by the four-digit bit identification signals, which are then present in the register output lines i6 to i9 and represent the bit address BBBB of a particular instruction word in register 202. In other words, the bit control circuit 404 is known as a 1:16 multiplex gate

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y> 2743Ü6Ü

formed, the same via lines 16 to i9 Control signals are fed to the bit selector 40 ?. Dy Scarf tune; 4o4 gives the signal BC, which, as explained below, is made a 1 by logical processor 401 only if the selected bit of the selected word is considered to be O signal must be inverted over that of their 16 das Output lines which carry signal H and which correspond to the selected bit position. All other output lines of the control circuit 404, which carry the signal G, remain at the level 1, so that when the signal BC is a 1, the signal ANS · becomes the same as the word originally selected, except that the selected bit contained therein has been inverted is.

The signal ANS ¹ can then be stored again in the memory at the same address from which the originally selected word was taken, with the result that a bit in the newly stored word has been changed or not changed, as was necessary, to execute the relevant bit manipulation command SV, IV, ST or RS.

5. Examples of commands and their codes

The more detailed explanation below uses a limited number of eight arithmetic or conventional Commands, and nine special logical commands are discussed. To understand the entire way of working of the computer system it is necessary to use the special Specify machine language codes for the commands in question in the form of examples. Of course it is with help a marketable manufactured computer of full size possible, a considerably larger number of the most varied arithmetic or other conventional command to formulate and store, and on the basis of the limited number of Various command codes can be used in the examples discussed below.

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Λ. Ordinary beefenle

In the first eight lines of table If only eight, conventional commands are listed, which have been selected for the purposes of explanation; this is sica about the special five-uit codes at the uit parts b 11 to b1 ^r ; a basic BefeiTcode of the type indicated in the first line of Table I, each ijefehl being uniquely identified. These common commands are briefly explained below.

until

LDA 00001

ADD 00011

Charging the accumulator with a data word the address given by uits bO to b9,

Adding a numeric data word from the by the bits b0 to b9 given address to the number then displayed in the accumulator and subsequent singing of the new result into the accumulator.

■; U3 00101

Subtract a numeric data word from the address determined by the bits b0 to b9 from the number contained in the accumulator and the following Enter the new result into the accumulator.

STA 00010:

Extract the word ANS indicated by the accumulator and "store" this word in the Memory at the address indicated by bits b0 to b9.

CLA 00100:

The accumulator is cleared by setting all bit signals in the ANS signal to a binary 0 will.

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ORiGiNAL INSPECTED

274306Ü

! AR 00110:

• AL 01000

JMF 01010:

Shifting the accumulator one place to the right, i.e. shifting each binary Signals in the i6-uit-sir; nal ANS one place behind right, so that the number represented by the signal ANS is practically multiplied by two.

Shifting the contents of the accumulator to the left, i.e. shifting each binary signal in the 15 positions of the accumulator by one position to the left, so that the one represented by the signal OUT Number is practically divided by 2.

Jumping within the program sequence from which the program counter was added Command word for a memory address which is determined by the binary bit values at the address positions bO up to u9 (by presetting the program counter).

It should be noted that the instructions LD, ADD, SUB require an operand to be extracted from memory and to supply it to the arithmetic input register 102. No operand is selected for the STA, CLA, 3AR, SAL and JMP commands the memory required. The code chosen here as a simple example distinguishes between the two types of commands by the presence or absence of a 1 at bit position b11 of the relevant command word and a corresponding one 1 signal on line 111 after the command word has been transferred to the instruction address register 202.

For each of these ordinary or basic commands, bit position b10 is used to indicate whether the command is unconditional or is to be carried out conditionally. If any such word is entered into register 202, line HO becomes binary 1 is supplied if this command is only executed

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BATH ORIGINAL

should, if the then pending logical signal LA a 1 is. As explained below, the signal from the Line i10 is decoded directly and used to determine whether instruction execution continued or aborted shall be. The execution is always continued if the signal U / C in the line i10 is a 0 and thus a unconditional command. Furthermore, execution continues when the U / C signal is 1 and the Gigaal is LA is also a 1, but the execution is aborted if the signal U / C is a 1 and the signal LA is a 0 (Π = 1).

B. Special commands

Nine special commands are possible, each characterized by a specific operation which is related to of a selected bit of a selected word is to be performed. This is one at a time the word formats which are labeled "logical process instructions" or "logical bit manipulation" in Table I wear. The special five-bit instruction codes at bit positions b11 to b15, through which these nine special instructions are unique are identified are given in Table II and briefly explained below, specifically with regard to the signals, appearing on lines iO through H5 after the command word has been entered into register 202.

b15 to b11

IF 00111: "If" a selected bit (identified by BBBB on lines i6-i9) of a selected word at the memory address (identified by AAAAAA on lines iO-i5) in its true form or its complement form (by a 0 or a 1 in line HO) is 1, skip the next step of the program by advancing the program counter. i98U0fc00

LD 01011:

Λΐ; 01001

OR 01111

XR 01101

Load the selected cit of the selected word into the accumulator to match the LA signal bring with it. The selected word is activated by address signals from lines OK to named; the selected bit position is identified by binary signals from lines b6 to b9.

Enter the selected bit (identified by signals from lines i6 to i9) of the selected word (whose memory address is reported via lines iO to i5) to the logic processor, process it with the then pending signal LA according to a logic AND function and that Set logical response signal LA according to the result of the AND operation.

Enter the selected bit (denoted by lines i6 to i9) of the selected word (from the memory address denoted by lines iO to 15) to the logical processor and cause the processor to send it to the then pending signal LA according to a logical OR function process and bring the logical answer LA into agreement with the result of the OR operation.

The selected bit (identified by lines i6 through i9) of the selected word (from the by the lines iO to i5 designated memory location) enter the logical processor and cause the processor to respond with the then pending signal LA in accordance with a logical Exclusive OR function to process and the logical answer LA in accordance with this To bring surgery.

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..: 7 A 3 ϋ 6 ü

SV 10001: The then existing binary value of the logical Answer LA to the memory at the selected junction (identified by signals on lines bb to b9) at the selected storage location (identified by signals in lines bO to bf?) input.

IV 10011: Inverting (complementing) the selected bit (identified by lines io through i9) des selected location in memory (at the location indicated by the lines i0 to i5 identified address).

:: t 11011: The selected bit (through lines i6 to i9 identified) of a selected word (on the one identified by lines iO through i5 Memory address) to state 1.

RS 10111: Resetting the selected 3it (identified by lines i6 to 19) of the selected location (at the memory address identified by the lines iO to i5) to the state 0.

In the case of the four logical processing command words LD, AIJ, OR and XR, the binary character at the bi-part b10, which is shown in appears on register line i10 to indicate whether the selected bit is in its true form or in its complement form T / C to be processed. In other words, a binary 0 on line i10 causes the logic processor to treat the selected bit as a 0 or a 1 when the signal IB is a 0 or a 1, respectively; however, an in Binary 1 appearing on line HO causes the logic processor to treat signal LB as if it were a 1 or a 0 would be if it is actually a 0 or a 1.

For each of the logical bit manipulation command words IF, SV,

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ORIGINAL INSPECTED

/ 743UuU

IV, JT and RS, on the other hand, are used by the signal at bit position b10, that appears in line i10 to indicate whether the uefenle should be carried out unconditionally or conditionally (U / C). The operation is the same as that mentioned above for an ordinary logic command, i.e. every command word v / is ignored and the execution of the command is aborted if the signal U / C in the Line iiO is a 1, and the logical answer LA is the value 0 has.

According to Tables I and II, the special logical Define two groups, each of which has four special commands. In other words, the commands LD, AN, OR and XR are considered to be lo-i'-che processing operations because they can lead to the response signal LA of the logic processor being changed. The commands of the second group can are designated as bit manipulation commands, because the commands 3V, IV, -'T and IiG do not change the logical answer LA, but rather they lead to the possible Change of a selected bit within a selected word in the memory. The first group of logical Commands can be recognized in Table II by the fact that a 1-u signal is present on lines ii4 and i11 after any this instruction word has been entered into register 202. The second group of logical commands is different differs from all other commands by the fact that in the line Hi; a binary 1 signal is present after any such logical command word has been entered into register 202. As explained below, these two groups of handles logical commands in different ways to activate microprogram memory 220, but cause them to all logical commands within a certain group that the microprogram memory is activated in the same way.

For each of the nine special logical command words

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the signals at jj tr.tellen bo to b9 for identification selected bits are used, and therefore these bit positions are available not available for specifying a memory address. this means that the selected words are extracted from memory as a function of a special logical instruction must appear in memory locations, whose numeric address values are between 0 and 63. However, this does not result in any serious restriction, because there is a sufficient number of 16-hit data words that are needed to accommodate a large number of special logical operations. aside from that you can avoid this restriction by extending the bit length or the words, or by adding some of the first 63 storage locations used as intermediate storage locations, which other words from higher memory addresses can be entered by the software programming before the word in question is used in a logical operation.

6. System memory details

11 and 12, the system memory is shown schematically, to which a memory of relatively small capacity which, however, is sufficient as an example for the explanation to be given. The memory contains 1024 words, from each of which is composed of 16 binary bits b0 to b15. Thus, the address digits can represent the decimal values 0-1023, and the appearance of any of those decimal values in binary notation in the 10-bit address rail an access to the corresponding word position via decoding circuits of a known type, not shown. The 16 input lines 302 of the memory lead to the 16 bits of each word, with the exception of the logical bits to be explained, which are only to be read out Words, and the 16 output lines 301 are assigned to the corresponding bits of each word.

Basic command words and special logical command words with the formats and meanings given above

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any of the addresses of the memory can be entered, however, a software program is usually the sequential Organize commands of an overall program and generally convert them into sequential addresses. Furthermore can Data words are placed in each of the memory addresses, but they are usually placed in the addresses with the higher numbers stored. Those words that contain individual bits that are felt or by special logical Single bit commands are to be changed, are placed at the memory addresses 0 to 63, and that is why, because the six-digit operand address numbers in memory locations b0 to b5 of each special command word according to of Table I contains a bit identification code BBBB, can only represent decimal numbers between 0 and 63. These The only limitation arises from the simplification of the embodiment described here as an example, and they can be avoided in a number of ways, e.g. by designing the system in a known manner so that the Have addresses indexed.

If any word is "addressed" by signals in the rail 11, and if the write signal BTM ^{1 is} fed to the memory decoding and control circuits, the signals then present in the rail 10 and the input lines 302 are accepted and in the corresponding bit positions of the memory location saved. If, on the other hand, any word is addressed by signals in the rail 11 and a read signal MEM is supplied, the stored values of the bits in the addressed word appear in the output lines 301, from which they are supplied to the rail 10 via the gate Gmr as shown in FIG will.

In order to create a fully programmable control device, storage units for certain address locations of the Provide system memory 300 in the form of external devices instead of magnetic cores. To any chosen example

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11 and 12, the address spaces 30 to 39 and 40 to 49 for words are used, each of which contains 16 individual bits in the form of two signals -u to Q ₁ ^ naci of Table I, which contain a / Off signals or binary logical data, for example, the location addresses 30 to 39 are each formed by 16 bistable fixed value devices, e.g. 3. by single pole changeover switch. These switches can be assigned to an external machine to indicate the status of various conditions; this can be z.3. be mechanical limit switches, pressure-sensitive switches or push-button switches. On the other hand, the addresses 4n to 4 ⁽ J are formed by 16 bistable Γ single bit read and write devices, e.g. 13 flip-flops, each of which can be set or reset as ⁿ binary signals are input from the computer system each device can switch an associated device, ζ.Λ. an itotor, an indicator lamp or a solenoid valve, on or off. With regard to the known core part of the memory 300 according to FIG Reading or writing activate the memory locations 39 to 49 constructed according to FIG.

Referring to Figure 12, the external devices for words W30-V / 39 are the same for each of memory address locations 30-39 Art. Regarding the device for the word W30 it can be seen that there are 16 external switches S0-S15, their movable sliding contacts via a normally closed 16-bit gate 310 with the associated memory address output lines MOC-M015 are connected. When a sol-

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rather switch is in its normal state, i.e. according to 12 in the shutdown state, it establishes a connection to the Iasse so that it supplies a binary 0 signal. Yird If one of these switches is pressed, it will set up a connection a source for a voltage of +5 V, so that it supplies a binary 1 signal. The so formed, from "Julien and Rinsen existing "V / ort" becomes the output lines MOO-M015 is supplied when the address 30 is decoded and when the address decoding circuits 311 receive a read signal FIEM. These signals are then transmitted via the Grar gate of the rail 10 and they can be input to one of the registers 102 and 202 as shown in FIGS. 2a and 2b.

The speed with which the switches for some or all of the words 30-39 can be felt, e.g. by a suitable programming at intervals of 20 ms has the same effect as continuous sensing of the switch states. of course, the states of these switches cannot be changed by write signals extracted from the rail 10 because their opening or closing state depends exclusively on external conditions. Of course you can the memory system according to the invention with 160 switches in one expand considerably by providing an even greater number of storage words, the structure of which is the same as that of the preceding Description in relation to word V / 30 corresponds.

The external hardware for each of the storage locations W40-W49 of Figure 12 is essentially the same. The structure of the word W40 therefore applies to all of these 7 / places. According to FIG. 12, the bit positions of the word W40 are formed by 16 flip-flops FF ₀ to FF ₁ ^ of the D type. The 16 memory input lines 302 are each connected to the D inputs of these flip-flops, while the clock or trigger pulse inputs are all connected to an encoder output line labeled 40.BTM ¹

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Rail 11 is addressed, and if an i .'- write signal BTM ¹ arrives, each of the 16 flip-flops is brought into the state (set or reset) which corresponds to the binary .'Ügnal in the corresponding memory input line. When the state is set, each flip-flop generates a binary 1 signal, while when the state is reset it generates a binary 0 signal. As further explained, these signals are fed to external devices via output terminals 40/0 to 40/15. However, these signals are also fed to the associated inputs of a 16-bit gate arrangement 315, the outputs of which are connected to the memory rausgabelunrjen. The gate array 315 is normally disabled, but when the decoder circuits 311 receive signals over the rail 11 which designate the address 40 and a read signal II3I-I, the gates 315 are enabled by a signal 40-MEM, so that the corresponding binary Signals are transmitted to the memory output lines 301, from which they arrive at the system rail 10. Thus, the 16 flip-flops, from which the memory word W4O is made up, can not only be set or reset and brought into certain states by signals that are fed via the system rail, but they can also supply signals that are fed to the system rail and be grounded Display associated states that are used in processing according to the Boolean logic.

In order to illustrate the manner in which various external devices can be controlled according to the state of the data stored in the memory word 40 bit signals, FIG. 12 shows that the Q output 40/15 of the flip-flop FF ₁₅ is connected to a driver amplifier to the electromagnet of a energize on and off solenoid valve 320 when the toggle switch is set or reset. In a similar way, the output line 40/14 is connected to a driver amplifier, by means of which a motor M

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corresponding to the state of the flip-flop circuit P ¹ F ₁ - is switched on or off, furthermore the output line ΛΟ / 1 is connected to a driver amplifier, so that a signal lamp 321 is switched on or off when the flip-flop _{circuit FF 1 is} set or reset . As a last example, it should be mentioned that the / ¹ V us output line 40/0 of the trigger circuit FFq J is used via a driver amplifier to actuate a warning device 322, for example a siren or bell.

For the actual computing system, it does not matter that some words within the system memory 300 are known Sometimes they are formed by magnetic cores, while other words are formed by switches, and that other words be formed by flip-flops that are used to switch external devices on or off. However, the computer system also process signals in a manner explained in more detail below, which designate the states of external switches, e.g. the switch forming the word W3O; it can feel the states of flip-flops, e.g. those using the word W4O form, and thus also the states of the devices controlled by them; finally, the system can do the Change the state of each of these flip-flops to an associated one to switch electrical device on or off, namely by adding a 1 or an O to a specific bit position of a word, e.g. at address 40.

7. Direct decoding details

The direct decoder circuit 209 of FIG. 2a is shown in FIG. 4 in more detail. This circuit has the task of providing the logical processor 401 with encoded operational signals LO, L1, L2, i12, ii4 and COMP, and if necessary to deliver the signals GETOP and COND. The circuit detects whether a command word is in the command address register a basic operation or a special logical operation

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requests; in the latter FnIl it causes a .'5ign.nl BADDR, which normally has the value 1, reverts to the value 0 assumes, in order to thereby cause the gates 20ό to mask the bit signals which are transmitted via the lines i6 to i9 the input OA of the multiplex gate 205 are fed.

Referring to Figure 4, UKD circuits 240 and 241 generate and one HOR circuit 242 sends the signal JADDR out via lines H5, ii4, i13, i'2 and i11 supplied ßingangssignalen. From the The instruction code set shown in part c of Table II can be seen, that then, if the command in register 20 *. an oitmanipulation requires (.SV, IV, ST or Ro), the signal in the line i15 die! 10 R- '"c hai do ^ 242 causes the signal BADDR the \ 'ert to give O. If the command is a logical one Processing (LD, Ah ", OR, XR) is required, do the Signals aun the lines ii4 and i11 the output Signa "', the UUD circuit 240 to a 1 so that the BADDR signal has the value O assumes. If the command IF is concerned, the AND circuit 241 generates the output signal 1, so that the signal BADDR assumes the value O. Every other one of these nine special ones Instructions that extract bit identification information from the Lines i6 to i9 contain the signal BADDR don 17ert 1 on, and the gates 206 are influenced so that off the lines iO to i9 a full word address to the input OA of the Ilultiplexgatters 205 is transmitted.

Part d of Table II shows the values which appear on the opcode lines LO, L1, L2, i12, ii4 for each of the logical process commands LD, AU, OR, XR and the bit manipulation commands SV, IV, ST and RS. On closer inspection it can be seen that the AND circuits 243, 244, 245 and 246 according to FIG. 4 together with the OR circuits 247 and 248 generate the operation code signals LO, L1, L2, with signals being passed on directly via the lines i12 and ii4 will. As can be seen from the following, the signals LO, L1 and L2 have no effect on the first nine

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are absent according to Table II, and therefore these signals remain fields in the first nine lines of Table II are empty.

As mentioned, every instruction which contains a 1 at bit position b11, so that signal 1 appears in line 111, requires that an operand from the memory is used. Thus, Figure h shows that the GETOP signal is simply the same signal as the 'J signal on line 111.

Regarding the commands LD, Ali, OR, XR and IF according to the table II indicates the '^ i ^ nal on line 110 that the selected üit in its true form or its complementary phoneme (T / C) should be processed. For all other commands, this signal means that the function must be executed, e.h. if then ^ it is a 0 in line b10, or conditional, i.e. if the signal on line b10 is a 1, but only if the logical response signal LA then has the value 1 has. This means that a signal COMP is only generated when the signal on the line i10 for a command LD, AN, OR or XR has the 'Vert 1, and only then generates a signal COND if the signal on line i10 has the value 1 for any other command. According to FIG. 4, the AND circuits 249, 250, 251 and 252 and the OR circuit 253 for this purpose. Looking at the command code sets in the Table II, it can be seen that the output signal of the AND circuit 250 corresponds to a 1 if any of the instructions LD, All, OR, XR or IF are in register 202. From the four first commands result ii4 = 111 = i15 = 1; from the command IF results in 113 = 112 = 111 = TT5 = 1. In every case If the signal 1 appears in the line i10, the signal COIIP is a 1. However, if the output signal of the AND circuit 250 is a 0 because there is an instruction other than the five above, and if on the line is HO the signal 1 is present, the AND circuit 251 has the effect that the signal COIID receives the value 1.

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27A3Ü60

"- · Details of the phase sequence generator ^{and 1 of the Kaupttakigebers}

For controlling the successive elementary operations of the re clone rs system v / e is the main clock generator according to FIGS. 2a and 5 214 a crystal-controlled device constructed in a known manner Clock pulse oscillator 260 running at a predetermined frequency of e.g. 2.0 ITIIz works. This oscillator drives a non-stable multivibrator 261 to generate timing pulses CLK and CLK, which are e.g. 100 ns wide and 500 ns apart. These timing signals are in 6 and 7 shown at 262 and 263. The regnal CLK is used to control the various gates and to preset different registers in all parts of the system, v / ie it is explained below.

The phase sequence generator 212 of Fig. 2a controls the elementary Operations that are carried out after each one of the consecutive instructions in the instruction register 202 is to be convicted. For those commands in which, it is necessary to fetch and use an operand word, the phase sequence generator 212 measures three elements Time intervals, which are referred to as phase 0, phase 2 and phase 3 in the following. During phase 0 will be the next Command word of a software program fetched from a memory address, controlled by the program counter 226 and the command address register 202 entered; during phase 2, the required operand becomes the memory address specified by the active Command word is named, extracted and supplied to the arithmetic input register 102; during phase 3, the commanded Operations performed.

In contrast to this, with some commands it is not necessary to to transfer an operand from the memory into the arithmetic input register 102. In these cases, the Phase sequence generator only to measure a phase interval 0, which is followed by a phase interval 3, so that a Phase interval 2 is omitted.

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2 7 A 3 G G O

Straight figure? the. '' frequency generator 212 can be used as a three-state Töhler be designed to which three toggle switches 265, and 267 belong to the D-type, »such flip-flops are known and it is assumed here that each of these flip-flops is brought into an iJchaltstatus that the level of the signal corresponding to its input D at the moment is supplied, in which a positively directed Üspannungsijberganp; the associated pulse input CP is supplied. According to Fig.? each of the three flip-flops become clock pulses CLK is supplied via its clock inputs CP, while a signal is supplied via input D or the Jtexierklemme in order to the ^ etr.en or resetting of the circuit according to the Control the presence of other signals.

Assume first that the GETOP signal from the direct decoder 209 of FIG. 4 is that the flip-flop is initially set, and that the flip-flops 266 and 267 are both reset, it can be seen that the output signal PIIO has the value 1, while the signals PH2 and PH3 have the value 0. If, according to FIG. 6, the trailing edge of the next clock pulse ULT arrives at time t2, actuated a Uiiü circuit 270 the flip-flop 266 by supplying a 1 signal to its input D, since the signals GETOP and PHO both have the value 1. Thus, at time t2, if the positive transition of the impulse CLK appears, the flip-flop 265 is reset while the flip-flop

266 is set. The output signal PH2 now has the value 1 The times t2 and t3, as shown in FIG. 6. In this latter state, i.e. phase 2, passes through the signal PH2 an OR circuit 271 to the flip-flop

267 to be actuated while the input signal at input D of the flip-flop 266 has the value 0. If then the next Pulse CTE according to FIG. 6 ends at time t4, the flip-flop 266 is reset, but flip-flop 267 is set. This ensures that the output signal PH3

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Tl

maintains V / ert 1. Furthermore, a qualifying 1 -. 'Ji ^ - nal fed to input D of flip-flop 265, and that the input D of the flip-flop 267 is supplied 'irnal eliminated. Therefore, with the next pulse CLk, the flip-flop 26? reset while the tilting operation; 265 is set so that the signal PIIO now retains the value 1. This sequence of the three states P; iO, Κί2 and r,. '3 sets continues indefinitely as long as the signal GjS'i'OI- den Keep value 1.

If, on the other hand, c * as "signal GHTOP has the value 0, which always happens if there is an" instruction ir, τ. Jpeiclier is required will ger> ^: ii3 ⁷ Sir. 5 the gate 270 blocked, doc: i introduces an inverter 272. '■' igr.al ÜTToT with. the ^1: ert 1 dei.i input of a further UI j D-. I hold 273, which can generate a 1-output signal, if the J signal VjiO is additionally fed to it. It means that: J signal ΟΪΊΊΌΡ the Vfert 0 and the signal G ^ TOP the V / ert 1, it can thus be assumed that the sequence generator 212 is initially in a state in which the flip-flop 2ύ5 is set. When the r.ip lines 266 and 267 are reset, the gi-pial PI10 is passed on via the gate 27 ° and the ODPIR circuit 271 in order to actuate the toggle circuit 267, so that if 7, the next trailing edge of a pulse CLk appears at time t2, the flip-flop 265 is reset, but the flip-flop 267 is set. Comit, the signal PHO disappears, while the oignal PH3 appears. Under these circumstances, the flip-flop 26? actuated by the signal ΡΠ3 applied to its input D, but the flip-flop 26? locked, ie at your input D an O-signal appears. As soon as the next pulse CLK arrives, the flip-flop 267 is reset, while the flip-flop 265 is set. As shown by waveforms PHO, PH2 and PII3 in Fig. 7, in this mode of operation, the signals appear

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PIIO and rii? alternately in Abi.nrigi,; kei 'c of successive clock pulses, v :, ^: theirc. the signal PK2 simply changes to the level O.

V. 'is decoded in netVnI in order to generate the signal GETOP ^ u, the phase sequence generator thus generates a sequence of signals PHO, VA? As a function of successive clock pulses. and Pt-13 ^: If, on the other hand, an i ^ e error is decoded in which the use of an operand is not required, and if the "ignal ^ lAuP is not pending, the phase sequence generator only generates a sequence of signals PHO and PH3 as a function of the sequential ones Taktiraptilsen. each phase has z. Z, a length of 1 wikrosekunde, and pulse CLK shortly ^before! vn ^ e, each phase appears, can range from? 00 have a wide ns.

In order to ensure that the phase sequence generator according to FIG. 5 always starts up in the correct state when the Re c I, ne rs system is put into operation, when the computer is switched on, a switch-on pulse ^D V / R £> generated. According to FIG. 5, this pulse is fed to the set input Πι of the KIpD circuit 265 and the clear inputs CL of the flip-flops 266 xmd 267. When the computer system is switched on, the phase sequence generator 212 is first brought into a state corresponding to phase 0, in which the signal PHO has the value 1 and the signals PH2 and PH3 have the value 0.

9. Details of the card layout read-only memory and the input signals for the microprogram read-only memory

The read-only memory 210 according to FIG. 2a is a known type of code converter. In the very simple system described here as an example, it may be unnecessary to use a map-forming read-only memory, but will

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274 30B0

with fully developed systems for the practice where with a large number of possible commands is used, usually a read-only memory with e.mem address counter and an adder is used. In the present case is only note that read only memory 210 are instructions Signals on lines 111 through ii5 from the register 202, and that when it is enabled by a signal PII3 as shown in FIG. 8, its output lines supplies a certain corresponding 4-bit code. These four output lines usually contain the signal

0 when the enable signal PK3 is not available. Since the read-only memory 200 is manufactured in a known manner durc'-i ^"T? In.jrennen" of Ilatrixverbindungen, its structure can be best understood from the Table V describe in the last 11 lines of the combinations of Singangssignalen in the lines i11 to i15 represent averaging which different combinations of coded output signals are generated for lines Xa, Xb, Xc and Xd. Each of the logical process commands for determining the signals LA, ie the signals LD, AN, OR and XR according to the table IT, which cause a 1 signal to appear on the lines 111 and ii4, causes the read-only memory 200 to generate a common output code 1100 ; Correspondingly, each of the bit manipulation commands SV, IV, ST and RS, which, according to Table II, cause 1 signals to appear in lines i11 and H5, is decoded by the read-only memory so that a common output code 1101 appears in lines Xa to Xd.

Referring to FIG. 8, the phase sequence generator 212 routes the signals PHO and PH2 directly to the lines via OR circuits 275 and 276 Xa and Xb too. If signals for phase 0 and phase 2 are present according to Table V, a 4-bit code

0001 or 0010 as input signal to the microprogram read-only memory 220 to effect a "fetch" or "pull out of an operand". During each subsequent phase

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3 becomes the input signal for the microprogram read-only memory 220 then determined by the read only memory 200; this output signal for the microprogram read-only memory, appearing on lines Xa, Xb, Xc and Xd is shown in part e of Table II.

10. Details of the microprogramming read-only memory

9 shows further details of the microprogram read only memory 220 according to Fig. 2b. The structure of such a memory is familiar to anyone skilled in the art; connections in permanently stored in a matrix. It should therefore only be noted that the memory 220 has various coded input signals over the lines Xa, Xb, Xc and Xd, and that the memory certain corresponding combinations of signals appear in the 15 output lines IH to M15 leaves. According to FIG. 9, these output lines are divided into different fields. Generally speaking, the lines form H1A and M15 an address field defined by the code of signals appearing in them denotes the source from which signals are fed to the memory address rail 11 should. The lines M11, M12 and H13 form a rail field, by means of a combination of signals appearing in it any one of eight possible special signals which designate the source from which signals are to be fed to the system rail.

Correspondingly, the lines 118, M9 and M10 form an ALU field, and the coded combination of the signals appearing therein each designates one of several possible operation commands which are to be fed to the unit ALU in order to control it in the case of various commands. The lines M5, M6 and M7 form the "memory field ¹¹ and the combination of the signals appearing therein represents the relevant register or the unit in which the then appear in the system rail.

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. J \ 27A3Ü60

end signals should be stored, never Loitun ;; en I-; 2, H and HA form a field for "miscellaneous" and the combination of the '. signals appearing therein can cause one of performing several different operations. In the end the output line M1 forms a line field / the Designation IPC; a 1-signal is always fed to this line when the program counter is advanced target.

According to FIGS. 2b and 9, the output signals of the microprogram read-only memory from the fields ADDR, JUS, ALU, STORE and HISC are supplied to field decoders 230 to 2 Λ. Each of these decoders is simply a matrix of a known type with several '"ingons and a single output; their structure and mode of operation should be familiar to anyone skilled in the art. Decoders 23 and 284, on the other hand, are controlled Decoders which only allow a signal to appear in one of their output lines ^, if they are enabled by a signal 1 via an enable input 2; J3a or 2T; 4a. Table III illustrates both the structure of the microprogram read-only memory 220 as well as the output signals in lines I-I1 to H "! 5 appear at the various possible command codes, averaging which different coded input signals are generated on lines Xa to Xd. In Table III, the blank fields indicate the fact that envelopes appear in the microprogram output messages. Table VII gives the tables for the decoders 2CO to 2ΓΛ and illustrates the individual output signal that appears in one of the output lines of each encoder for various combinations of input signals that are fed to the decoders via their input lines. Tables III and VII thus give a person skilled in the art a complete picture of the structure and mode of operation of the microprogram read-only memory 220.

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■ \ us the /'.ei]e 1 of Table III \ ^ t apparent that generated during a Abrufvornanrs, which is represented by the code 0001 as an input signal for the lakroprograram-Fes twertspeicner, the Address field decoder 230, an output signal PC indicating , da.3 the address to be supplied to the rail 11 can be found in the program counter 226. It should be noted that this signal the Ilultiplexgatter 205 of Figure 2b releases so that the Zählerausgan _fc;. 5signal PA zv the address forwarded rail 11 v / ill. In the operations GETOP, JUiIP and the manipulation, the combination of input signals which are fed to the microprogram read-only memory 220 causes the address field decoder 280 to emit an output signal Kk in order to enable the multiplex gate 205 so that its input signal OA (from lines iO to iy, but excluding lines i6 to i9 when gate 206 is blocked) to rail 11. The address position is thus determined by the address part of a command word which is then located in the command address register 202.

Ss should be useful to indicate the meanings of the abbreviations used with which the output signals of the various necoder according to FIGS. 2b and 9 designated v / earth. In the case of the rail field, ADTR means that the address rail signals are to be fed to the rail; HEH means that the output signal of the memory is fed to the rail shall be; ATB means that the output of the accumulator to be fed to the rail; EOR means that the output signal is OUT 'of the 16-liit exclusive OR arrangement is to be fed to the rail. It should be noted that the signal ADTR controls the gate Gad, that the signal MEM controls the Reading of the memory controls and also controls the gate Gmr that the signal ATB controls the gate Gatb, and that the signal EDR controls the gate Gr.

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27Λ3060

In the ALU field, the command signals A and L indicate that the arithmetic logic unit ALU is to be conditioned in such a way that it only sends its input signals at A or B to its output lines at F. In contrast to this, the ALU command signal B "indicates that the unit ALU is to output its input signals in the complemented form via its output F. These command signals, which are designated here by A + L or AB, condition the unit ALU in such a way that that its output signal F is equal to the sum or the difference of the numerical binary signals A and L which are fed to their two inputs.

In the storage field STORE, the signals IAR and AIR indicate that signals then appearing in the rail are to be stored in the command address register 202 or in the arithmetic input register 102. They are supplied to AND circuits 203 and 101. The signal ACC indicates that the output signal F of the unit ALU is to be stored in the accumulator 104; this signal is fed to an AND circuit 103 in accordance with FIG. 2a. The signal ΒΪΗ according to FIG. 9 indicates that the signals then appearing in the rail are to be stored in the main system memory; this signal is fed to an AND circuit 303 which ^{generates the write signal BTM 1} when a clock pulse CLK occurs. The signal PPC indicates that the signals then occurring in the rail are to be picked up by the program counter 226; this signal is fed to the UlJD circuit 231, which then generates the signal PPC in order to effect a presetting of the counter to a number which is represented by the signals then present in the rail. The signal LAS indicates that the result of a logical processing operation is to be stored in a logical accumulator flip-flop which is described further below with reference to FIG.

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In the "miscellaneous" field, the signal CLR causes when it appears that the accumulator 104 according to FIG. The BTLOG signal indicates that the logical processor is to be conditioned for an application process; this signal appears as a function of one of the commands SV, IV, ST and RS. The signals SACR and SACL are fed directly to the accumulator 104 and have the effect that the then existing content of the accumulator is shifted one place to the right or left. The signal IPCLB indicates that the program counter is to be switched on if the selected logical bit signal then corresponds to a specific one of two possible states; this signal is used to execute an IF instruction in a manner to be explained below.

In summary, it should be noted that the microprogram read-only memory 220 with the associated decoding! 280 to 284 cod.ierve Picks up command signals during the relevant phase via inputs Xa to Xd. Depending on it only one of each field decoder output line receives a 1 signal at a time, but responds to many operations a particular field decoder does not at all. These control signals are received from the microprogram field decoders routed to various points of the system for the delivery of signals to the memory address rail and to control the system rail 10; in addition, they are sent to the unit ALU in order to carry out the function to be carried out by them and they are fed to different registers or gates to determine which of the different ones Parts for storing signals are fed, which are then pending in the system rail.

It should again be noted that the output of the decoder 283 (storage) and 284 (miscellaneous) is withheld,

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if this decoding ^ is not ^{supplied to enable a 1- 1} I Ignal via the inputs 203a and 284a. This switching off of all output signals of the decoders 2G3 and 234 has the purpose of terminating the execution of arithmetic instructions if the instructions are conditional and if the required condition is not met. This is discussed in more detail below. First, it may suffice to note that the condition control device 403 of FIG. 2b, a signal K Ängen the Steuerein ^ 2 ^Q 3n and 2 ^ 4a feeds. The device 403 is shown in FIG. 9 by an ilAIiJD circuit; 20? Formed with the three inputs COiJD, L "Ä" \ χηύ PH3. The output / signal κ of this circuit normally has level 1. However, all three input signals of the Jchaltun «;; 2:19 at the same time the V.'ert 1, ke.irt the output signal K back to the ./ert 0, and therefore the decoders 2 >> 3 and 234 cannot deliver any output signals.

FIG. 9 also shows the logic circuit for generating a .Control signal TMPC, by means of which the program counter is switched on will. The, microprogram signal IPC passes through a ODclk circuit 290, so that the 3signal IiIPC is produced; However can this latter signal also through a UIID circuit 291 can be generated when the 3 signal IPCLB and a signal ELb each have the value 1 for an effective logical bit. The signal IIIPC is fed to a circuit 227 which according to FIG. 2b, the program counter 226 is assigned to L. If this signal occurs simultaneously with a clock pulse, results The output signal HjC has a negative direction Transition on the lower edge of the clock pulse, so that the counter 226 counts up by one unit.

11. Logical processor and manipulation circuit details

As mentioned, the logical processor 401 receives a single bit input signal chosen from a 16-bit Viort and the

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'Vert O eier 1 Kibe: ι can. Furthermore, from the Direktdeciorschaloun ^ 209 according to Fig. 4 from "Onerationsfunktionsslgnale" L2, i, 1, LO, CU: iP, i ¹ 2 and i14. The logical processor generates / raises rs signals ". ¹ LU, LA, LT and r, C depending on the commanded function in order to modify the signal LA in the correct manner during the successive operations within a Boolean chain performed by steps.

Although mn could use various special circuits, FIG. 10 shows the details of a suitable logic processor 401. These details are first treated according to Boolean logic with regard to chained operations, and then the manipulation and storage are dealt with.

According to Fi _t;. A flip-flop 425 of the JK type is used as a logical single bit accumulator. This accumulator was chosen because of its properties mentioned below. V / ird an opannum; applied to input J or input K in accordance with a binary 1, the flip-flop is set or reset depending on a positively directed voltage transition that is fed to its clock input CP; if none of the inputs J or K receives a voltage with the level 1, there is no reaction to a trigger signal appearing at the clock input CF; however, if there is a voltage with level 1 at both inputs J and K, when the positive voltage transition appears at the clock input CP, the flip-flop mn turns itself, ie it changes from its set or reset state to its reset or its set state . If the flip-flop 425 is in the set state, it lets the signals LA and LA "or 1 and 0 appear at its outputs; in the reset state, the output signals LA and TK take on the values 0 and 1.

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27A3060

In the following, the mode of operation for the ^ a 11 is considered that the logical function code signals L2, L1 and LO have the I / ert 111, which corresponds to the logical command LD (load accumulator) according to Table VI. If the input signal LB is a 0 or 1 and the control signal COHP has the V / ert 0, the effective logic bit signal ELB, which is generated by an exclusive-OR circuit 426, has the value 0 or 1. If ELB is the same 0, the output signal η of the UiID circuit 428 has the value 0, but the output signal ο of an exclusive OR circuit 429 is 1, since LO is 1 iso, so that the output signal ρ of the UiID circuit 430 is 1 and causes LA to be brought to 0 or left at 0 when flip-flop 425 is supplied with a clock signal. If, on the other hand, ELB is 1, the signals ο and ρ have the value 0, but the signal η is 1, so that the osignal LA is made a 1 or left at this level when the flip-flop 425 is supplied with a clock signal. As indicated in the first line of Table VI, an instruction LD thus causes the accumulator flip-flop 425 to start with the selected! Biteingangssignal LB is charged to bring the logical answer signal LA in accordance therewith.

Of course, the exclusive OR circuit 426 causes ELB to be the complement of LB, but only if the signal is COMP has the value 1. If this is the case, the arrangement according to FIG. 10 acts as if the input signal LB would be the reciprocal of its actual value.

It is now assumed that the signal AN is required by the logical command word in register 202, so that the code for L2, L1 and LO has the form 1001. Under these circumstances, the signal LA should be brought to the level or at the level which corresponds to the response of the logical AND function LA = LA · LB. Is the toggle switch 425 already in the 1 state, LA does not need to be changed,

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if LB has the value 1. Only when LB is equal to 0 is it necessary to reset the flip-flop 425 by a clock pulse. Since the signals at LO and L2 are both equal to 1, the signals ο and ρ have the value 1 or 0 when ELB is equal to 1 or equal to 0, respectively. Thus, the flip-flop 425 is reset or left reset by a clock pulse when ELB is zero. The end result is that the new '.'fert of LA is always a 1 or 0 when the UIJD function LA _Q · LB is satisfied or not satisfied assuming COMP is zero. This self-evident fact is reflected in the second line of Table VI for the various conditions that may exist (LB equals 1 or 0 and COMP equals 1 or O).

If the logical command is an OR, so that, according to Table VI, the code 010 applies to L2, L1 and LO, the signal LA should be held in such a way that it becomes LA _n when LA _{Q is} equal to 1. However, if LA _{Q is} equal to 0, the signal should only be switched to 1 when ELB is equal to 1. In the latter case, the AND circuit 428 is qualified in such a way that the signal η receives the value 1. In any case, the AND circuit 430 is blocked so that the flip-flop 425 cannot be reset. When the OR function code arrives and the flip-flop 425 is supplied with a clock signal, LA thus remains at the value 1 if this value was previously present; however, LA is switched from 0 to 1 when the signal ELB has the value 1. This fulfills the logical OR function, so that LA = LA + LB, as indicated in the third line of Table VI.

If the logical command XOR occurs, so that the code 110 applies to L2, L1 and LO according to Table VI, the signal LA in a 0 or a 1, if it previously had the value or 0 and the input signal ELB is a 1. Has the Signal ELB has the value 1, the signals n, o 'and ρ each have the

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2VA3Ü60

Value 1, so that the clock pulse supplied at CP controls the flip-flop 425 surrounds. If ELB is equal to 0, η and ρ are both equal to 0 and the flip-flop 425 does not respond Clock signal on. Whenever the XOR command is received and decoded so that L2, L1 and LO take on the value 110, Thus, the arrangement of Fig. 10 responds to a clock pulse to ensure that LA = LA. 0LB, where the symbol (?) denotes the exclusive OR function.

In accordance with Table VI and the description above, the logic processor of Figure 10 takes a single input LB and converts it into an effective logic bit signal ELB, which is identical to LB or its inverted When the signal COMP is equal to 0 or 1. This operation is performed by the exclusive OR circuit 426 carried out. As a function of the signal ELB, the arrangement according to FIG. 10 generates a new logical response signal LA as a result of the logic function commanded by the coded signals L2, L1 and LO, the codes of these Signals correspond to the commands LD, AN, OR, XOR according to Table II. To the logic processing circuit at successive To control operations clockwise, an AND circuit 432 receives the storage signal LAS from the field decoder FD5 is supplied off, and the clock signal CLK is supplied after the signal LB is generated and on the control inputs J and K of the flip-flop 425 have the correct voltages. These control signals result from the single input signal LB, which is generated by adding the selected word to the arithmetic input register 2a, and that the bit selection circuit is caused to select the selected bit in response to bit selection signals on lines i6 to i9 as input signal LB to the logic processor.

From Table VI and Fig. 10 it can be seen that the three

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digit function code signals L2, L1 and LO as well as the input signal Form LB input signals for several facilities, namely

1. Devices 428, 429 and 430 which only respond to load function code signals (1, 1, 1) and address the input signal LB in order to apply a 1-signal to the input J or K, if LB is 1 or 0,

2. Devices 423, 429, 430 that respond only to AND function code signals (1, 0, 1) and address the input signal LB in order to apply a 1-signal to the input K only if LB equals 0,

3. Devices 428, 429 and 430 that respond only to OR function code signals (0, 1, 0) respond to supply a 1 signal to input J only when LB is equal to 1, as well as

4. Devices 428, 429 and 430 which respond only to exclusive-OR function code signals (1, 1, 0) respond in order to feed a 1-signal to the two inputs J and K only if the signal LB has the value 1.

The mentioned devices apply voltage levels with the value 0 to the inputs J and K if none of the mentioned ones Cases exists. Therefore, the logic processor 401 operates without any feedback from its output signal LA, and this signal influences the operation of the 1. to 4. Not mentioned facilities. Once the opcode signals and the input signal LB in any of their various 0 and 1 combinations according to Table VI are available are, the clock pulse, which is supplied by the AND circuit 432 from the clock input CP, only that the Flip-flop 425 is triggered or remains untriggered to cause LA to accept that state value or to maintain, which corresponds to the correct result of the function, which by the in the right part of table VI specified coded operational signals are represented.

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V *

Of course, the ELB signal is the same as the LD signal, when the true signal or the complement signal COUP is equal, and it is equal to the complement of LB when COIIP is equal 1 so that LB is treated in its true form or its complement form as appropriate.

It is true that one could in accordance with some points of view of the invention can use other and known forms of accumulating logical processors, but the in Fig. 10 illustrated novel processor advantages, since it does not require any feedback and can easily be changed by three-digit Can instruct function code signals.

When performing a Boolean chain of operations according to a simple expression chosen as an example should, e.g. according to the expression

X = (111 + ϋΖ) Ν3 ® N4,

where N1 denotes the tenth bit b9 of the memory word 44, N2 the eighth bit b7 of the memory word 25, N3 the first bit b0 of the memory word 61 and N4 the fifteenth bit bi4 of memory word 35,

it is possible to write program steps in machine language as follows:

Step 1

step 2

LD

b10 address 44

(- \

101100

01011 0 1010

After execution, LA = N1

OR

b8

Address 25

01111 1 0100 011001

After execution, LA = N1 + HZ

step 3

AT

01001

bO

Address 61

0000 111101

After the execution, LA = (N1 + ΪΤΖ) · Ν3 80981 5/0600

b14 address 35

Step 4 01101 O 1110 100011 Mach the execution LA = (N1 + flZ) .N3 0 N4

If the command word for step 1 is brought into the command register 202, the direct decoder 209 according to FIG. 2a causes this and 4 that the signal BADDR goes to zero, so that the Close gate 206 of Figure 2b to mask lines i6 through. The direct decoding circuits are also responsive to command coded signals on lines i11 through i15 (on the signals 01011 in step 1 above), so that the signals L2, L1 and LO according to Table II have the values 111 assume, and the 0 appearing on line i10 of the register makes signal COMP a 0. If the multiplex gate 205 of FIG. 2b transmits its input signal OA to the address rail 11, this is done at the memory location 44 stored word is supplied to the register AIR or 102 in a manner to be explained below. When the command register output lines i6 to i9 control the bit selector 402 by the signal combination 0110, the output signal of the register 102 at the point b9 to the signal LB. If a clock pulse occurs thereafter, the logical answer LA becomes the same the signal Ii1, which is the eleventh bit of the Memory location 44 is extracted word. This is done from the above with reference to FIG. 10 and Table VI explained reasons.

In a similar way, the logical program steps 2, 3 and 4 chosen as an example can be carried out one after the other so that after the fourth step the signal LA is the result X of the Boolean expression chosen as an example represents.

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Si ',

The signal LA remains unchanged until another logical one Process step is carried out. This is because the control signal LAS can never appear, and that the flip-flop 425 cannot be clocked as long as the decoded command is not LD, AN, OR or XR acts. However, the signal LA can be buffered for later use; alternatively it can be in a hardware tilting scarf fcungsbit of the memory are saved to turn an external device on or off. Noc - more important is the fact that the signal LA or its complement LA "can be used to determine whether a conditional Failure is actually carried out; this is discussed in more detail below.

To the signal LA in any selected bit of a To store selected memory word, the bit manipulation part of FIG. 10 and the bit control device 404 as well as uses the exclusive-OR arrangement 106 of FIG. 2a. It it is assumed that an instruction SV has been transferred to the instruction register 202 and that this instruction contains codes, which retrieve the signal at bit position b7 of the word stored in memory location 14. In machine language takes the instruction as it appears in register 202 takes the form 10001/0/0111/001110. As a result, it becomes the 16-bit word W taken from the memory location 14 and fed to the arithmetic input register 102, and the bit signal from the bit location b7 becomes the signal LB. If now the signal LB a 1 or a 0 and the signal LA is a 1 or a 0, the original signal from bit position b7 of word 14 is correct coincides with LA and there is no need to change it. However, when the signal LB is a 0 or 1 and when the signal LA has the value 1 or 0, the signal at bit position b7 of word 14 must be inverted in order to match to bring the logical response signal LA.

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ORIGINAL INSPECTED

- ^ -? 'M 3 0 6 0

Considering that according to Table II, the logic command SV results in the operation code signals L1 and LO the V / er te 0 and 1, the AND circuit 440 is blocked according to FIG. 10, while a second AND circuit 441 is enabled when an SV instruction is processed. Thus the signal a will be a 0 or a 1 when the logical response signal LA has the value 0 or 1. An OR circuit 442 forwards the signal a so that it becomes the signal c, which is an input signal of an exclusive OR circuit 444, which is the second input signal logical single bit signal LB is supplied. The signal d therefore only has the value 1 if the signals LB and LA are not equal i.e. if one of them is a 1 and the other is a 0. The signal d passes through an OR circuit 445, so that it becomes the signal f which is applied to an AND circuit 446, the output of which is the bit control signal BC is. The BC signal can only have the value 1 if a control signal BTLOG from the microprogram read-only memory or the miscellaneous field decoder 284 of FIG. 9 is then at level 1; this condition becomes one during phase 3 SV operation fulfilled. When a caching instruction SV is to be executed, the selected bit becomes the selected Word introduced as signal LB, and the bit control signal BC is only brought to the value 1 if the Signals LB and LA are unequal, which means that the selected bit of the selected word must be switched to to bring it into agreement with the then existing value of the signal LA.

Referring to Fig. 2a, the bit control signal BC is applied as an input to the control circuit 404 for the selected bit to which only one input line and 16 output lines for the signal H belong. As mentioned, the bit control circuit 404 normally leaves a 1 signal on all 16 H output lines appear, but not when the bit control signal BC

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-6ο- / 743UbU

is a 1; then the corresponding bit of the signal H, which is indicated by the signal code on lines i6 to i9 of the register 202 is determined, converted into an O signal. Consequently the signal H either consists of 16 1-bits, or it contains 15 1-bits and a 0-3it if BC has the value 0, and the relevant bit with the value 0 is the selected bit, which is the case with the example dealt with here comes from bit position b7 of register 102.

If one remembers that the selected word W, namely word 14 from the memory in the example, is always present in the arithmetic input register 102, and one assumes for the moment that the control circuit is following the signal B of the unit ALU 2a, the signal F is the one's complement of the selected word, ie F = W. The complement signal W forms a multi-bit input signal for the 16-bit exclusive OR arrangement 106, to which the 16-bit input signal H, in which the selected bit has the value 0 according to the example at bit position b7, is also fed. Therefore, the output of the 16-bit exclusive-OR 106 is a 16-bit ANS ¹ which is the original word taken from memory, ie, W has been inverted back to V /; an exception is that the selected bit is inverted with respect to its original value and converted to the opposite value by the exclusive-OR circuit if the selected bit signal did not originally coincide with the signal LA. If, in the example dealt with here, the signal BC is a 1, the signal H from the bit control circuit 404 contains only ones, but a 0 is present at bit position b7. Therefore the signal ANS ^{1 is} equal to the signal F (which corresponds to W), which has been inverted, except that in the signal ANS ¹ the signal at bit position b7 is not inverted back and in the signal ANS 'as the complement of the b7 signal of the original word W appears, which is held in the arithmetic register 102.

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After the signal ANS 'has been formed in this way, the selected bit having been shifted if necessary to match the logical response LA, the gate Gr can be enabled by a signal EOR in order to apply the signal ANS ^{1 to} the system rail 10. After this has been done, this set of signals can be stored in the memory at the original location 14. In this memory state, the value at bit location b7 corresponds to the signal LA which is formed after one or more logical processing operations of the processor 401 .

If you consider this explanation based on a specific example with respect to the memory word position 14 and the associated bit position b7 as well as the fifth line of Table VI, you will see that each word from the memory (at the first 64 memory locations 0 to 63) with the aid of an instruction SV can be brought into the arithmetic input register 102 that the selected bit of this word is defined by the command, which is fed as signal LB to the logic processor 401, that the bit control signal BC is formed in order to generate the signal H for the exclusive-OR- To generate arrangement 106, and that the arrangement 106 then ^{supplies a signal ANS 1} which represents the original word, the selected bit having the value 1 or 0, which corresponds to the logical response LA. It should be noted here that use is made of the parts of the basic arithmetic system, ie the input register 102, the arithmetic logic unit ALU, the instruction address register 202 and most parts of the control unit. The bit control signal BC assumes the value 1, and the selected bit of the selected word is only shifted if this is necessary in order to change the selected bit signal so that it corresponds to the value of the signal LA then present.

It is possible to use different signals regardless of

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whether they are through external switches, external flip-flops or
the state of memory cores are represented, to be introduced one after the other and according to logical processing instructions with the help of a chained sequence of operations
to process the Boolean logic so that a final logical answer LA is obtained. After such an answer has been created and used or stored, another answer can be generated with the aid of another Boolean sequence. Let us assume, for example, that the result of such a Boolean expression determines whether a to
controlling machine, a solenoid valve is to be switched on or off after the signal LA has finally been formed, a memory word, to which a control flip-flop for the electromagnet belongs, can be brought into the arithmetic register 102. The selected bit entsnricht a selected flip-flop, for example, the output of the flip-flop Ffy and definition of V / 40 of FIG. 12, is then manipulated so that it üuereinstimmt with the final logical response LA, and the signal ANS ¹ is then again the The same memory location is entered, here in FIG. 12 as word W40
is shown. If LA has the value 1 or 0, the flip-flop FFy is set or reset, and that for the control
Serving solenoid valve is switched on or off.

Further bit manipulation commands are possible, namely the commands IV, ST, RS. Instruction IV causes the selected bit of the selected word to be inverted; the command ST causes the selected bit of a selected word to be set to
Value 1 is brought or retains this value, and the command RS causes the selected bit of the selected word
is reset to the value 0 or left in the reset state.

With regard to the command ST, which according to Tables II and IV
leads to the signals L1, LO and ii4 having the values 1, 0, 1

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9t

-7 * - 2743Ü60

assume, it can be seen that the AND gate 441 of FIG. 10 is blocked, so that the signal a must have the value 0. On the other hand, the signals L1 and ii4 both have the value 1, so that, as shown in FIG. 10, the signal b has the value 1 and passes through the circuit 442 so that the signal c has the value 1. If the signal LB now has the value 0 or 1, the exclusive-OR circuit 444 lets the signal d appear at its output with the value 1 or 0; the signal d appears as the signal f, and when the enable signal BTLOG appears, the output signal BC assumes the value 1 or 0. If, as already explained, a selected word is brought into the arithmetic register 102 and the selected bit is fed to the logic processor 401 as input signal LB, the selected word appears in inverted form at the input F of the 16-bit exclusive-OR arrangement 106 If the selected bit signal is not a 1, the bit control signal BC becomes a 1, and after processing by the exclusive-OR arrangement, the corresponding * bit in the signal ANS ^{1 is} inverted, ie it is from a 0 to a 1 been transformed. This operation can be seen in the seventh line of Table VI, which confirms that the instruction ST always results in the selected bit being brought to the value 1, either by inverting its original value 0 or by the fact that the previous one Value 1 is retained.

In the following, the bit manipulation command RS in the eighth line of Table VI is discussed. This command leads this means that the signals L1, LO and ii4 assume the values 1, 0, 0. Therefore, the gates 441 and 440 are both blocked, so that the signal c is held at the value 0. Has the Selected logic bit signal LB has the value 0 or 1, has the output signal d has the value 0 and the signal f has the value 1. Thus, the signal BC has the value 1 when the control signal BTLOG appears, but only if the selected, through the sign

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- ⁷ ^ - 2743U6Ü

nal LB represented bit has the value 1. If the signal BC becomes a 1 and, according to FIG. 2a, the selected word appears again at AIiS ¹ , the selected bit is switched from its original value 1 to a new value 0, or its original value 0 is retained. The reset command RS therefore always results in the selected bit of a selected word being switched to 0 or left at the value 0. Of course, the signal ANS 'can then be stored again in the original location in the system memory.

The invert command IV in the sixth line of table VI causes the signals L1, LO and i12 to assume the values 0, 1, 1. If these control signals are fed to the circuit according to FIG. 10, an AND circuit 448 is fully qualified, so that a signal e with the value 1 appears at its output, whereupon the output signal f of the OR circuit 445 regardless of whether the signal d is a 0 or a 1, keeping the value 1. Command IV thus always results in signals f having the value 1 and signal BC assuming the value 1 as soon as the control signal BTLOG appears. Since an invert command always generates a signal BC with the value 1, the selected bit of the selected word in ANS ¹ always appears in its inverted form compared to the original value. Each word which is transferred from a memory location to the arithmetic register 102 when an invert ^{command comes into effect therefore appears at ANS 1} , the selected bit identified by the command being inverted. ^{The ANS 1} signal can then be stored again in the original memory location in the system memory.

An inverted form of the word appears as input F to the 16-bit exclusive-OR array 106. If required is to change the selected bit of this word, i.e. an intermediate storage according to the respective command, Inverting, setting or resetting,

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the bit control signal BC assumes the value 1, so that the corresponding selected bit of the signal H receives the value 0, while all other bits of the signal H have the value 1, so that the signal ANS ^{1 is} the original word in which the selected Bit has been inverted. If, on the other hand, the selected bit has the correct value as a result of one of the commands SV, ST and RS, the bit control signal BC retains the value 0 and the signal OUT ¹ is simply the original word in which the selected bit retains its original value.

12. Operation of the system - general A. The retrieval operation (phase 0)

When the execution of a specific command is completed, always at the end of an interval of the Phase 3, which ends with the trailing edge of a clock pulse, the program counter 226 has been switched on beforehand, so that it numerically signals the next instruction address within a program with several steps. One assumes that at the moment in which a certain phase 3 ends, for example at time ti according to FIG. 6, a phase 0 begins the output signal of the program counter a certain decimal address number xxx. When the signal PHO appears, it is a fetch code for line Xa of the microprogram read only memory forms, the decoders FD1 to FD5 generate control signals according to the first line of Table III PC, IiEM, A, AIR and IPC. As shown in the graph in FIG. 6, these have control signals during the interval between the times ti and t2 each have the value 1. This Control signals are sent to the multiplex gate 205t, the memory 300 and the gate Gmr, the unit ALU, the AND circuit 203 and the OR circuit 290 of FIG. 9 during the entire phase 0 interval. The signal IPC is generated the signal INPC, which is fed to the AND circuit 230 according to FIG. 2b. A clock pulse 262a only appears during the last

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9 *

- ¹ N- ? 7 U 3 ί. ' 6 U

th part of the interval of phase O and is thus through the AND circuits 203 and 230 passed on.

The signal PC causes the multiplex gate 205 to be the output signal PA of the program counter 226 of the address rail 11, so that the command word at the relevant memory address as a result of the read signal! EH to the memory output lines and is fed to the system rail 10 via the gate Gmr. The access time of the memory is approx 200 ns in the known memories, so that the selected command word is supplied to the rail in good time before near at the end of the phase 0 interval, clock pulse 262a appears.

However, if the clock pulse 262a appears, it activates the AND circuit 203 to generate a preset enable pulse IAR ', which the bad address register 202 while the presence of the clock pulse 262a causes the command word to be stored, which is then transferred from the memory to the rail 10 is transmitted. Since AND gate 230 is partially enabled by signal INPC, clock pulse 262a also fails a corresponding positive pulse HiC at the switching input of the program counter 226 appear, which then reacts to the negative trailing edge of the pulse INC to to increase its counting result by one unit from xxx to xxx + 1.

At the moment, however, in which the program counter 226 is incremented is, the phase sequence generator 212 replaces the signal PHO with the signal PH2 in those cases in which the instruction just fetched to instruction register 202 requires an operand, and direct decoder 209 is caused to to generate the GETOP signal.

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9 «

D. Feeding the operand to the arithmetic register (phase 2)

As soon as the signal PII2 appears, the input code according to part b of Table III, the microprogram read-only memory is supplied, changed from the code after the first line of Table III to the code after the second line. Therefore, the field encoder output signals are combined into a combination of the signals EA, MEM, A and AIR. The signal EA appearing during phase 2 is in the lower part of Fig. 6 is shown; the signal MEM retains the value 1 according to FIG. The signal present during phase 2 is AIR also shown in FIG.

Depending on the signal EA, the multiplex gate 205 is conditioned so that it receives its input signals OA, which the Address output lines i0 to i9 of the register 202 are taken to the address rail 11, and the signal MEM conditions the memory 300 and the gate Gmr so that the content, i.e. the operand, of the system rail 10 from the Address position is entered. In this way, the operand word fetched by an instruction word becomes the memory removed and fed to the system rail.

The signal AIR appearing during phase 2 causes a partial release of the AND circuit 101, and when the clock pulse 262b appears near the end of the phase 2 interval, this circuit is fully activated to a pulse AIR, which, while the clock pulse 262b is present, causes the arithmetic input register 102, to receive and store the operand signals then present in the rail. Thus, an operand fetch operation includes during a phase 2 measures to take the respective data word from the memory, which is determined by the operand address which is located in the command word which is then contained in the command register 202.

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$ 9

- ⁷ ^ - ^ 7 4 3 O 5 O

It should be noted that the command signal A, which the unit ALU during a fetch phase O or an operand fetch phase 2 is fed, only causes the contents of the accumulator to be fed to the output F via the unit ALU. Although this is of no particular importance in the simplified system dealt with here, it is possible in practice monitor the contents of the accumulator during phases 0 and 2 by treating signal F as a status word will. In the present example, the command A, which is supplied to the unit ALU during phases 0 and 2, can be be ignored.

C. Execution of the command (phase 3)

Simultaneously with the trailing edge of the clock pulse 262b, the phase sequence generator 212 replaces the signal PH2 with the Signal PH3. Therefore, the map read-only memory 210 of Fig. 8 is activated to have encoded input signals the microprogram read-only memory supplies, the combination of these input signals uniquely the respective Represents the instruction which is indicated by the five upper bit signals, which due to a then in the register 202 stored command word appear in lines i11 to. Thus corresponds during each execution phase 3 shows the combination of the output signals from the field decoders Fig. 9 those decoded output signals that are in the Parts c through h of Table III are shown, and this applies to each of the various possible commands. Each specific one Combination of control signals generated in this way leads to a different result.

To give an example, the execution of the LDA instruction during phase 3 is shown graphically in the lower part of FIG. According to Table III, during phase 3 of an LDA sequence of operations at the field decoder outputs, the Control signals B and ACC generated. Therefore, this causes the

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is called ALU, the signal B supplied to this unit, input signals B, which represent the data word that was previously used as an operand was fed to the input register 102, according to FIG. 6 during the entire interval of phase 3 between the points in time t3 and t4 to be fed to output F. In addition, the ACC signal causes the AND circuit 103 to be partially enabled is so that when a clock pulse 262c appears at the end of the phase 3 interval, a corresponding pulse ACC accordingly The lowermost waveform in FIG. 6 is applied to the memory enable input of the accumulator 104. The accumulator now saves and signals the operand data word at ANS, which was previously taken from the memory and during the Phase 2 is stored in the arithmetic input register 102 has been. Thus, an accumulator load command LDA has the effect that a specific operand is taken from the memory, the input register 102 is supplied and then transferred to the accumulator 104 during phase 3, whereupon the operand word at ANS appears. FIG. 6 uses the example of the LDA command to illustrate the three steps Operation following the fetching of any instruction that requires the use of an operand; these commands are each marked with an asterisk in Table III.

The GETOP signal occurs with the STA, CLA, SAR, SAL and JMP commands, for which no operand needs to be used during the polling phase 0 does not appear. Therefore, as shown in FIG. 7, the phase sequence generator does not generate a signal PH2, and the Alternating intervals of phases 0 and 3 are measured by the signals PHO and PH3.

In these circumstances the operation is during the interval the retrieval phase 0 exactly the same as it was described above with reference to FIG. 6, and actually plays The retrieval process is the same for each command. However, since, as shown in FIG. 7, the signal PH2 does not appear and therefore the signal PH3 immediately follows the signal PHO,

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an execution phase 3 runs off immediately after a command word has been transferred to the command address register 202 is. The signals on lines i11 through H 5 from the retrieved Command word thus cause the read-only memory 210 to supply the microprogram read-only memory 220 encoded input signals immediately after phase 0, and the Field decoders generate the required combination of control signals to perform the operations described in accordance with FIG the command word contained in register 202 are required.

FIG. 7 shows two examples of instructions in which no operands are used. In this regard, reference is made in particular to the illustrated interval of execution phase 3. Assuming that the error STA has been fetched into the register 202 during phase 0, the microprogram field decoders output signals EA, ATB and 5T14, as shown in FIG. 6, when the signal PH3 appears given in Table III and in t'ig. 7 is shown. The signal EA causes the multiplex gate 205 to supply the address-representing bits of the command word, which then appear on lines iO to i9, to the address rail 11 in order to condition the memory system 300 so that it receives signals at the desired memory location. The signal ATB is supplied to the gate Gatb to open it, so that the accumulator output signal ANS is supplied to the rail 10. The signal BTM causes a partial release of the memory control AND circuit 303, and when the latter is supplied with a clock pulse 262c near the end of the interval PH3, a pulse BTM ^{f is} generated which enables the system memory so that the signals at the addressed memory location which are then fed to the rail from the accumulator 104. Thus, an accumulator store command STA causes the signal ANS then present in the accumulator, possibly previously as a result

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several chained arithmetic calculation processes has been formed, the system memory at the designated location is entered.

According to FIG. 7, after the termination of the phase 3 interval at time t2, the phase sequence generator 212 causes the signal PHO occurs and the next interval of a phase 0 is measured, so that the next command word from the Memory address designated by the program counter 226, which was previously used during the end section of the previous interval of a phase 0 has been.

Furthermore, Fig. 7 shows the operations resulting from a JMP instruction. If the JMP command is issued during phase 0 j η the command register 202 is fetched, no GETOP signal is generated and the phase sequence generator goes immediately to phase 3. The lower bit positions of a command word JI-IP designate the address of another command word, that is to be used next, and that does not follow in numerical order the address PA, which is then replaced by the Program counter 226 is reported. If the code JMP appearing on lines i11 to 115 enters read-only memory 210 causes the microprogram read only memory 220 to supply appropriate input signals, the field decoders generate according to Table III and the lower part of FIG. 7 output control signals EA, ADTR and PPC. The signal EA is conditioned the multiplex gate 205 »so that it transmits the signals from the lines iO to i9 to the address rail 11, however, the system memory 300 does not respond since neither a signal PTM nor a signal MEM is supplied to it. The signal ADTR opens the gate Gad, so that the numerical address value then present in the rail is sent to the system rail 10 is transmitted. The signal PPC causes a partial release of the AND circuit 231, which occurs during the end section of the inter-

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JOS

In addition, a clock pulse 262c is supplied to phase 3 according to FIG. 7. The output signal of the circuit 231 is a pulse PPC ¹ which enables the program counter 226 to be preset to the numerical counting state, which is represented by the signals then present in the rail 10, in order to numerically represent the address position of the next instruction to be used. If, for example, the program counter was in state 126, so that it would then cause it to take an instruction word from memory location 126 during normal operation, instruction JMP can preset the program counter to count result 285 or 63 so that when the next Interval of a phase 0 begins, a command word is used which appears in memory location 285 or 63.

From the above description it can be seen that the computer system according to the invention responds to a wide variety of instructions, only a few of which have been dealt with, some of which require the use of an operand taken from memory, and of which still others are executed directly without a Operand is required. The conventional or basic arithmetic commands are used in a sequence of programmed steps, with jumps being switched on if necessary, in a known manner in order to generate responses to individual or chained arithmetic operations, these responses as signals ANS from the accumulator ΪΟΙ * appear and then can be stored in any desired memory location with the help of the execution of an accumulator storage command STA.

D. Effect of special logical commands

The specific logical instructions are generally executed in accordance with the sequence described above with respect to the instructions in which an operand is used, but these instructions do not result in arithmetic operations. Much more

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sot

they lead to processing according to the Boolean logic or to bit manipulation in the logical processor 401, where as an input signal LB the selected bit of a selected word is used, both through a in the command register 202 fetched special command word can be designated.

1. Logical process commands

As already briefly explained, always works when one of the four logical process commands from lines 12-15 of the table III is fetched into the command register 202, the signal BADDR from the value 1 to the value 0 over to the masking gate 206 to block. In addition, the GETOP signal appears instantaneously if 0 during the interval of a phase a special command word is entered into register 202. If one of these logical process commands is called, it is run through thus the system becomes a phase 2, and a selected word corresponding to the signals on lines iO through i5 becomes fed to the arithmetic input register 102. The signals from lines i6 to i9 then condition the bit selector 402 such that the selected bit signal of the selected word appears in the logic processor 401 as input signal LB. It also performs the direct decoding of the signals from lines i10 to i15 that result from the retrieved Command word result, for generating corresponding coded control signals L2, L1, LO, COMP, 112 and i14. These signals determine the particular function that the logical processor 401 performs using the single bit input signal LB.

After phase 2 depending on a logical process command is complete, and when the interval of a phase 3 begins, the read-only memory 210 performs according to FIG Table III sends the input code 1100 to the microprogram read only memory 220 and generates the associated field decoders

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only the logical control signal LAS (storage of the logical Answer). As mentioned, the control signal LAS effects a partial conditioning of the AND circuit 432 according to FIG. 10, and when near the end of the phase 3 interval the clock pulse appears, flip-flop 425 is actuated to to store the result of the logic function commanded with respect to the input signal LB. Sonit becomes the signal LA brought into that state or left in that state, in which it forms the answer or the result of the executed logical process function LD, AN, OR or XR. Zv / ar can of course have different logical voltage combinations do appear on control lines L2, L1 and LO when ordinary arithmetic commands are processed the signal LAS does not appear under these conditions, so that the flip-flop 425 according to FIG. 10 is not clocked and that it is not switched over as a function of the voltage levels appearing at its J and K inputs.

2. Bit manipulation commands

If any of the logical bit manipulation commands SV, IV, ST and RS is used during a phase 0 of the type described in the command register 202 is retrieved, the signal BADDR returns to the value 0 to disable the masking gates 206, so that the input signal OA for the multiplex gate 205 through which then appear in the lines i0 to i5 Command word signals is formed. Therefore, during the phase 2 interval, the selected word is written to the arithmetic input register 102 transferred. The bit selector 412 controlled by the signals from lines i6 to i9 causes the selected bit of the selected word to appear as input signal LB for logic processor 401. In addition, those appearing in lines i10 to i15 initiate Signals of the logical command word direct decoder 209, the logical processor function designation signals

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L1, LO, i12 and ii4 to be supplied. This leads to the Arrangement nacia Fig. 10 generates a signal f which determines whether the signal BC has the value 1 or not if the gate 446 is later enabled by a control signal BTLOG.

During phase 3 of the execution of a logical bit manipulation command, the read-only memory 210 feeds the input signals 1011 to the microprogram read-only memory 220, and the associated decoders FD1 to FD5 generate the control signals EA, EOR, 5, BTII and BTLOG according to Table III. As a function of the signal EA, the multiplex gate 205 is conditioned in such a way that it allows the signal OA to reach the address rail 11. The memory address signals therefore designate the same memory location from which the selected word was read out during the previous phase 2. The control signal E causes the unit ALU to make the output signal F the complement of the input signal B, the latter being the selected word which was transferred from the memory to the input register during the preceding phase 2. The signal BTLOG enables the gate 446 according to FIG. 10 in order to make the control signal BC a 0 or a 1, which, as explained above, depends on the value of the signal f, which is determined by the type of bit manipulation function commanded and the value of the input signal LB is determined. The signal BC acts on the bit control circuit 404, which is conditioned by the bit selection signals from the lines i6 to i9 and then generates the input signal H for the exclusive-OR arrangement 106, the selected bit contained therein having the value 0 or 1, when the signal BC has the value 1 or 0. The output signal ANS ^{1 of} the arrangement 106 is then equal to the originally selected word, the selected bit being inverted or not, as corresponds to the commanded logic function and the value of the signal LB.

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The signal EOR opens the gate Gr in order to feed the signal ANS ^{1 to} the rail 10, this multi-bit signal corresponding exactly to the data word which was taken from the memory during the previous phase 2, and the selected 3it being manipulated as required to execute the bit manipulation instruction contained in register 202.

The signal BTM exists during the entire phase 3 and causes a partial release of the AND circuit 303. As soon as the clock pulse appears during the end portion of the interval of phase 3, the signal BTM ^{1 occurs} as a pulse to prevent the input of the then in the rail 10 to cause existing signals in the memory location, which is designated by the signals in the address rail 11. Thus, the originally selected word is re-entered from the memory into the same memory location, with a single selected bit of the word being changed as is necessary to execute the relevant instruction SV, IV, ST or RS.

3. Conditional arithmetic instructions

According to the invention there are facilities that make it possible the control or execution devices at one to block any command that is not a logical process command and that is coded so that it forms a conditional command if the logical response signal LA does not have the predetermined value 1 or 0.

In the first line of Table I, the symbol U / C at bit position b10 only means that if the coded command value contains a 0 or 1, the command is an unconditional or a conditional command. Is it a conditional Command, the signal COND according to FIGS. 4 and 9 becomes a 1 as soon as the relevant command is entered in register 209 is retrieved.

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40 t

In the embodiment described here, during the execution of phase 3 at least one control signal generated by the field decoder FD4 or FD5, from which the final Execution step results. For example, appears in phase 3 of the ADD command according to Table III, the ACC signal; this signal enables the AND circuit 103, see above that the pulse ACC can be generated in order to transfer the result F of the unit ALU into the accumulator 104. Will however, if the ACC signal is destroyed, the entry cannot be made and the execution is aborted. So on this Way, the execution of any conditional command can be blocked if the signal COND is a 1, according to 9, the signal K is made a 0 when L "ä" = 1 (LA = 0) is. The signal K with the value 0 simply disables the field decoders FD4 and FD5, so that even if an interval of phase 3 is measured, no command can be executed.

Of course, you could also use other or equivalent circuit elements and connections to achieve the same effect. For example, the phase sequence generator could be controlled by signals COND and LA in such a way that it simply jumps from phase 2 to phase ο when these two signals are present. This would prevent execution because the map read-only memory would not be enabled by a signal PH3. Furthermore, the microprogram read-only memory could be designed in such a way that it receives the signal COND as an input signal, so that it generates output signals during the phase which do not lead to a control signal when they are decoded. Furthermore, the signal K could be fed as a third input signal to all AND circuits, for example the AND circuit 103 »in order to block them during phase PH3 when TJ. = 1 and COND = 1. It is true that devices of the most varied types could be used, but the only thing that matters is that the control unit is blocked in order to prevent the execution of a command coded as conditional.

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prevent if the previously formed logical answer LA then not a predetermined state of two states, and State 1 is referred to here.

E. The IF command

There is an instruction in which a certain bit of a certain Word is chosen, and which thus to some extent resembles a special logical command, although at the selected bit is used neither for logical processing nor for manipulation. This one with IF The instruction designated is used to cause the next operation instruction within a program sequence to be skipped becomes, if the selected bit of a selected word, which has either its true form or its complement form, is a 1. It is therefore useful to describe here the operations that are performed when the command IF is fetched into command register 202 during any phase 0 interval.

The first six bit positions b0 to b5 of an IF instruction designate the operand word to be selected, while the bit positions b6 to b9 denote the bit within this word that is to be checked. The bit position signal at b10 in one Instruction IF denotes by a 0 or a 1 whether the selected bit is used in its true sense or in its complement form shall be. The other bit positions designate b11 to b15 the IF command code according to Table II.

After fetching an IF command word into register 202 operations during phase 2 are exactly the same as with any of the command words described above. In other words, the selected word is transferred from the memory to the rail 10 and the arithmetic input register 102 is input and bit selector 402, responsive to signals on lines i6 through i9, causes the input signal

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LB for the logical processor 401 the value of the selected Bits in the selected word. If, according to FIGS. 4 and 10, the signal on line i10 is a 1, which indicates If the selected bit is to be treated in its complement form, the COMP signal has the value 1. In in this case, the exclusive OR circuit 426 makes the signal ELB the complement of the signal LB; otherwise ELB has the same value as LB. At the end of the phase 2 interval for an IF instruction, the ELB signal exists in the logic Processor of Fig. 10, and it becomes the UlID circuit 291 according to FIG. 9 supplied.

When the phase sequence generator 212 enters execution phase 3 and the read-only memory 210 is enabled, the latter responds to the IF instruction code to supply the microprogram read-only memory 220 with a unique combination of input signals. The associated field decoders then generate only the control signal IPCLB in accordance with Table III. If this signal is present during the interval of a phase 3, and if the signal ELB has the value 1, the AND circuit 291 of FIG. 9 produces the output signal 1, which passes through the OR circuit 290 to the signal INPC of AND Circuit 230 according to FIG. 2b. When a clock pulse appears near the end of the phase 3 interval, a corresponding pulse INC is applied to the count input of program counter 226. When the trailing edge of this pulse appears, ie exactly at the end of the phase 3 interval, the program counter 226 continues to count by one unit. If you consider that the program counter was incremented at the end of the interval of the previous phase 0 so that it is ready to call up the command word from the memory, which is the one which is to be used next in a program sequence, this causes The program counter is incremented during phase 3, which runs depending on an IF command, so that the program counter is incremented twice. When the next phase 0 begins, one step of the program is simply skipped.

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The IF command is therefore a convenient way to edit any Check the bit of any word to determine whether it is a normal numeric data word, or a word that only contains logical bit signals that are generated by external switches or flip-flops, and skip the next program step if the checked bit is either a 1 or a 0. Y / if the bit b10 in the command word IF has the value 0, the next program step command is skipped if the checked bit has a 1 is; however, if the bit b1O in the command word IF has the value 0, the next program step command is skipped if the checked bit has the value 0.

13. Typical program sequences that the computer according to the invention can run through

Having explained the various machine language commands and the individual operations resulting therefrom above an explanation of commands in English-language symbols will be given below, v / ie they of can be used by a programmer in setting up program sequences. To initiate it is necessary, however, to allocate specific memory locations to the numeric data words and the logical bit data words in order to facilitate the description certain software program sequences as examples.

The following assumptions are made:

The number N1 is stored in memory location 452. The number N2 is stored in memory location 25. The number N3 is stored in memory location 85. The number N4 is stored in memory location 96. The two-state signal R is at bit position bi4 of the memory location 29 saved.

The two-position signal S is at bit position b3 of the memory location 18 saved.

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4η

The two-state signal T is through the switch S8 Storage location 30 according to FIG. 12 is formed.

The two-state signal U is through the switch S12 of the Storage location 30 according to FIG. 12 is formed.

The two-state signal V is formed by the flip-flop circuit FFg of the memory location 40 according to FIG.

The two-state signal W is formed by the flip-flop FF _{15 of} the storage location 40 according to FIG.

The two-state signal X is formed by the flip-flop circuit FF _{1 of} the memory location 40 according to FIG.

A. Boolean signal processing with control of external devices that can be switched on and off

It is assumed that it is desired in a certain part of an overall arithmetic and logic program, according to Fig. 12 to turn on the solenoid valve 320 when the number N2 is positive and the signal R is a 1, or when the switch S8 is closed (T = 1) and the flip-flop FFg is set is (V = 1). One stored in bit position b15 of word 452 0 or 1 means that the number N2 is positive or negative. This can be explained by the following Boolean Display expression:

Switch on valve 320 if ((N positive) »R + (S8» FFG) J

V / = (N1 positive.R) + (T-V)

If these measures are to be carried out and program step 442 to be started, a program could be used, for example write with commands like this:

step LD complement command word 25th and location AT true b15 word 29 442 SV necessarily b14 word 63 443 b0 444

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-vT ' true command 2Ί A 3 0 6 0 step
and location true b8 445 LD true b6 word 30th 446 AT unaffected
things bO word 40 447 OR b15 word 63 448 SV './location 40

These program instructions would be transferred to memory locations 442 bis in a known manner. Help of a punched tape or one Card reader.

If during later operations the program counter 226 the When counting result 442 is reached, bit 15 of word 25 is tracked to accumulator KipO circuit 425 in its complementary form Fig. 10 is input so that LA becomes a 1 or 0 when the number N2 is positive or negative, respectively. The program counter switches to state 443.

Then, in accordance with the command taken from .Stelle 443, the jit 14 is brought from the location 29 into the logic processor 401, specifically with the aid of a UIJD operation code, so that LA _n assumes the value (N1 positvR). The program counter then advances to state 444.

The signal LA is then stored in a buffer location. The V / ort 63 is transferred to the register 102 and its bit b0 input to the logical processor 401, the one Receive cache opcode. The word is stored again at position 63, its bit b0 starting with LA matches, i.e. represents the result of (N1 positiveR). The program counter 226 transitions to state 445.

A logical command word is retrieved from address 445. It causes bit b8 of word 30, i.e. T, to be loaded, so that LA coincides with it.

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A logic command word is now fetched from position 446 in order to bring LB into agreement with bit b6 of word 40, ie with V, and so that the logic function code commands an AND operation. The signal LA _n receives the value (T »V). The program counter switches to state 447.

Next, the instruction is fetched from location 447 by which LB is brought into agreement with bit b0 of word 63, which was stored in the previous step 443, to represent (111 positive »R), whereupon processor 401 receives an OR -Function code is supplied. The LA _n signal becomes a response that is the following expression:

(N1 positiveR) + (T »V)

After LA is formed in this manner, and when the program counter reaches state 448, the latch command word is fetched. It causes word 40 to be entered into register 102 and LB to be brought out of that register in accordance with bit b15. The control signal BC is made a 0 or a 1 when LA is equal to or different from LB. Thus, the signal BC makes the bit b15 of the signal H a 1 or 0, and the exclusive-OR arrangement 106 brings ANS · into agreement with the original word from position 40, but with the signal b15 coinciding with LA. ANS ^{1 is then entered} again into memory location 40. It can be seen from FIG. 12 that if LA is equal to 1 at this point in time, the flip-flop FF is set or left in the set state; however, if LA equals 0, FF ^ _{0 is} reset or left in the reset state. Thus, the ultimate result of the chained Boolean operations is to turn the solenoid valve 320 on or off according to the Boolean logic response.

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Of course, the computer according to the invention makes it possible, too to realize numerous other types of Boolean equals by means of appropriate programming. Be it notes that you can use logical 1-bit signals in the Boolean sequences, which are activated by a switch or the like. generated, e.g. the signal T in the program example above, but also selected bits from numeric data words, e.g., according to the above example, the signal N1. The purely logical words according to the last line of Table I can be mixed with numeric words according to the penultimate line of Table I to produce Boolean Receive input signals. The logical answer LA at the end of a Boolean sequence does not need to be in a toggle switch to be saved; rather, it is possible to use them as an identifier in a specific bit of a specific word of the Core memory and then retrieve it at a later time for review or use. Further No sequential program steps need to be carried out in a Boolean chain of operations. It some of the logical operations can be performed, then arithmetic operations can be performed, and finally the Boolean chain can be resumed since LA contains the partial result.

B. Conditional arithmetic operations

As an example, it is assumed that it is desired to store the sum of N1 and N4 as the new value of the number N3 as part of an overall software program, but to subtract N2 from it, and only if one of the logic signals S and U but not both signals are in the 1 state; the result is then to be divided by 2, but only if the flip-flop FF ₁ according to FIG. 12 is in the reset state. The following steps are required for this:

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/ MC

--93 -

a) Add N4 to N1.

b) Subtract N2 from the result if 3 0 U.

c) Divide the result of a) and b) if the signal 40/1 according to FIG. 12 is a 0.

d) Save the result as the new value of N3.

In order to perform these operations under the stated conditions, you can write part of a program that begins with step 183, for example, as follows:

step LDA command bit 3 word 452 183 ADD necessarily bit 12th word 96 184 LD necessarily word 18th 185 XR true bit 1 word 30th 186 SUB true word 25th 187 IF conditional word 40 188 SAL complement 189 STA necessarily 190 necessarily

If the program counter 226 reaches the count 183, the basic command LDA is called up from the memory location 183. the Number N1 from memory location 452 is entered into accumulator 104 and displayed at MS. The unit ALU becomes a Command signal B supplied for this operation according to Table III.

As soon as the program counter reaches the state 184, the command ADD is called from the memory location 124. He causes that ANS and N4 (the operand from memory location 96) are added and the result in the accumulator as the new value of ANS is saved. Of course, during this operation, the ALU unit receives the command A + B.

If the program counter reaches state 185, the specific Command retrieved from memory location 185, and that

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/ 14 ϊ

Bit 3 of word 1o, i.e. S, v / i, is loaded to become the signal To become LA; this is done in the manner described with the aid of a logical process operation.

As soon as the program counter 226 reaches state 186, the special command word is retrieved from memory location 186. The bit signal b12 (switch S12 of FIG. 12) of the Word 30 is supplied as signal LB, while the logical processor 401 is an operation code for an exclusive OR receives over lines L2, L1 and LO. LA is brought into this state or left in the state that S φ U where the value 1 is only present if S or U has the value 1, but not if for both Signals the value 1 applies. It should be noted that steps 105 and 136 have not changed the signal ANS, they always have still represents the sum of N1 and N4.

If the program counter 226 reaches the state 187, the conditional arithmetic command "Subtract" is called up from the memory location 187. The operand IJ2 is brought from the memory location 25 into the input register 102, and an instruction AB is fed to the unit ALU. Then the signal at F becomes IJ1 + N4 - N2. 4 and 9, however, the signal COND is 1, and therefore during phase 3, when PH3 is 1, the signal K is 0, provided that TK is 1, that is, LA is 0 Has. If the signal LA, which represents the result of 3 © U, is equal to 0, the field decoders FD4 and FD5 are disabled and the accumulator memory signal ACC, which would normally be generated according to Table III, maintains the value 0. Therefore, the signal at U is not transferred to the accumulator 104 when LA has the value 0, but such a transfer occurs when LA is equal to 1. Thus, the subtraction step 187 is a conditional step and is only carried out on the condition that LA is 1; in this programming example

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game, this condition is that S (±) U = 1. Depending on the state of 3 and U, the signal AIiS at the end of step 187 therefore represents either (li1 + Il4) or (IM + U4-N2).

If the next special IF instruction location 188 is fetched and the program counter is increased to 189 during phase 0, bit 1 of text 40 is made the input signal LB, and since the instruction contains a complement designation (a 1 on bit position b10), the signal COMP 4 and 10, Fig according to. the value 1, so that the signal ELS a 0 or a 1, if the selected bit b1 is 1 or 0, ie, when the flip-flop FF ₁ is set or reset. Thus, during phase 3 execution, the IPCLB signal is 1 or 0 (Table III and FIG. 9), and IKC is 1 or 0 when ELB is 1 or 0. In the first case, the INCP signal has the value 1 and the program counter 226 is switched from 139 to 190 on the 2nde of phase 3, as explained above with reference to FIG. 7. In the latter case, the program counter remains in state 189.

In this latter case, the instruction is next fetched from the memory section 189, and the execution of phase 3 results in the control signal SACR being applied to the accumulator 104 in order to shift the contents of the accumulator one place to the right. Depending on whether S @ U = 1 or 0, the signal ANS is either or .

If, however, the signal 40/1, ie the bit 1 of the word 40 corresponding to the flip-flop FF ₁ according to FIG. 12, has the value 0, so that ELB has the value 1 during step 188, step 189 is skipped and the step immediately 190 executed. Regardless of whether step 190 follows step 188 or step 189, the STA instruction is fetched from location 190 and the ANS signal is stored in word location 85 where it represents the number N3.

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449

The calculated value stored in this way at N3 can be one of the following values:

_if 30 _{U = 1 xmd FF} is set back;

II when S (+) U = 0 and FF _{1 is} reset;

III N1 + N2 - H4 if 3 © U = 1 and FF _{1 is} set; or

IV N1 + 112 if S © U = 0 and FF _{1 is} set.

Several important features of such conditional arithmetic operations should be noted. First, the logical operations that lead to a result according to Boolean logic can be mixed with arithmetic operations more or less randomly, because they usually do not influence each other. In the example discussed here, the preliminary sum N1 + Uh is left in the accumulator 104 while the logical process steps 185 and 186 are carried out. It is only necessary that the end result of a Boolean chain be formed and signaled by LA before an arithmetic operation is performed which is conditioned by this end result. Second, the response from a long chain of Boolean sequences is retained in the form of the LA signal until some further logical process step is performed. Therefore, the signal LA can be used as a condition factor in several subsequent arithmetic steps. In addition, the final response LA of a Boolean chain of logic commands can be temporarily stored in a known bit of a known location, and then it can be transferred back to the logic processor, using a one-step command LD shortly before an arithmetic step, which should be conditioned by the final answer. Alternatively, a final logical response can be cached at a known bit address within a known word address, and then this response can be saved as a selected bit in

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an IF instruction can be used which precedes any arithmetic or logical step which is to be caused by this response. In the above example, the flip-flop FF _{1 of} the word 40 may have been set or reset by a logical response before the program step 133, and nevertheless the programmed step is only executed if the signal at bit 1 of the word is a 0, ie if the flip-flop FF _{1 is} reset.

The computer according to the invention thus offers extraordinary flexible and convenient programming options, with the end result or even the execution being different arithmetic calculation steps leads to various numerical results, which are based on certain relationships between multiple logical single-bit two-state signals directed by individual cores within a multiple Word address comprising cores of a memory system of a known type or by external switches, flip-flops or others devices that can be switched on and off can be generated. In particular it should be noted that a chain of Boolean operations can be carried out by, for example, programming steps 465 through 475 so that a response at LA which, when it has the value 0, indicates that a complete set of arithmetic steps 477 to 485 is not needed for a particular run of a complete program. Under these circumstances, the Jump instruction JMP can be programmed at step 476, it can be conditional, and it can be made to work with the step 486 names its bits b0 to b9. When it is executed, a jump is then made to step 486. Thus, steps 477 to 485 are skipped if a previously formed Boolean logic response, i.e. the signal LA, which has the value 0.

It is true that there are numerous other examples of program sequences describe with those in the computer according to the invention

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111

-9 * - 27A3060

can be worked, doc ^. probably the two above Treated simple examples are sufficient for any person skilled in the art the flexibility and advantages of the invention To make the computer recognizable. BeL a fully trained Computer that works with all normal arithmetic Command codes works, e.g. for multiplying, dividing, extracting the square root, forming the reciprocal value, etc., and not just with The limited basic commands of the example described are the logical and the conditional programming options almost unlimited, so that the requirements of any system to be controlled can be met.

As mentioned, the logic processing part of the invention works Calculator with the aritimetic calculation part in that it qualifies certain operations of the arithmetic part or enables operations to be carried out conditionally. The arithmetic part can cooperate with the logical part in that it is part of the elementary part takes on and performs logical work to save time. An example is a process or machine control system called, which includes a very large number of switches, as described in EIg. 12 are shown at SO to S15. It could 160 V / words with 16 switches each or a total of 2560 switches. Often it is only necessary to determine whether any switch in a group with e.g. 160 words is closed is. If only one programmable controller were used, it would be common up to now to use these switches to check with the help of chained OR operations, which include 160 program steps. According to the invention, however, it is possible, in a simple way, to bring each of the ten words into the accumulator and to do it through ten arithmetic programs Compare steps with 0. The "Compare with 0" command is a common arithmetic command Command which, however, was not taken into account in the above description of a simple digital computer. if

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any of the ten comparisons for the entire V. ^r the result of place "is not O" liofert, a flag can Z.3. a toggle switch, can be set to indicate that at least one of the 160 switches is closed. This indicator can be used to control subsequent operations. Although the computer according to the invention can only be operated as a programmable control device, it enables a faster and more flexible execution of some of the programmable control functions, since with some d ^! of its functions its arithmetic part can be used.

It should also be noted that in numerous practical applications, in which programmed control devices or computers are used, whole parts of a complete program can only be executed, but otherwise skipped, if the status is at least one of e.g. 256 Switches has changed since the previous program run. With a programmable controller, this would be make it necessary to save the state of each switch uni de: i saved state with that during the next Compare the current state of the program. According to the invention, on the other hand, it is possible for each program run To store 16 '/ orts from switch status signals and compare them for the same numerical values of the same "switch words" as those of the arithmetic unit must be entered on the next run. The comparison command is a known arithmetic command. Thus, with the aid of only 16 comparison program steps, it is possible to convert the arithmetic part of the Cause the computer to report whether the state of any of 256 switches during the last pass has changed, and this means that 256 program steps can be replaced v / grounds that would be required if a single bit logical processor were used for this purpose.

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Claims (1)

Patent attorneys D i ρ I. - I π g. Curt Wallach Dipl.-Ing. Günther Koch Dipl.-Phys. Dr Tino Haibach ? 7 4 3 U H U Dipl.-Ing. Rainer Feldkamp D-8000 Munich 2 · Kaufingerstraße 8 · Telephone (0 89) 24 02 75 ■ Telex 5 29 513 wakai d Date: September 24, 1977 Our reference: 15 929 - Fk / Ne Patent claims U c he A programmable digital computer characterized in that (a) a basic arithmetic system is provided which includes a read / write system memory (300) which can accommodate multi-bit words at a variety of address locations, some of these words representing encoded commands and addresses, while other words represent data and some of the command address words have a special code format to represent a logical command, a bit address and a memory address, an arithmetic unit (ICO) with inverted bit inputs and outputs, a conduction path "between the system memory (300) and the arithmetic unit (100) and control means (200) for generating successive sequences of operations, including the extraction of an instruction / address word from the memory, the supply of the operand represented by the address part of the extracted word from the memory arithmetic unit and the execution of the command part of the extracted word include that (b) a logic one-bit processor (400) is provided which is responsive to the various logic operation codes to perform various functional operations upon application of a two-state input signal (LB) and that the control devices (200) continue to respond to a special command word taken from the memory devices for transmitting the 809815/0600 ^{# /} " ORIGINAL INSPECTED determined corresponding to the bit address part of the extracted word Bits of the operand fed to the arithmetic unit (100) as an input signal to the logical processor (400) and to perform the function represented by the command logical portion of the extracted word. 2. Digital computer according to claim 1, characterized in that the control devices on a dem Special command word taken from memory, responsive devices for controlling the arithmetic unit (100) such that each arithmetic operation on the supplied operand as the result of the extracted Command word is omitted. J. Digital computer according to claim 1, characterized in that the control devices (200) on the logical command part of the extracted word command responsive devices include the logical Control the processor to process the input signal in its true or complemented form. 4. Digital computer according to one of the preceding claims, characterized in that the read-write system memory (300) Can accommodate and indicate multi-bit words at a variety of address storage locations the command address words having a special code format form a first group representing a logical command of bits, a second group of bits representing a bit position in a word, and a third a memory address Representative group of bits have that the arithmetic unit (100) an input register and a Output register comprises an instruction address register (202) and a conduction path between the system memory and the input, output and command address registers is provided that the output from the control devices (100) • 09 815/0600 274306Ü called "on successive operation sequences the removal a command address word auscfera memory and the Transfer of this command address word to the command address register (202), the supply of the operand from the system memory to the input register determined by the Storage space is represented by the then siegnalisiert Address output of the command address register and include the execution of the function, which is represented by the command address output then signaled that a logical Eln-Eit processor (400) is provided which is responsive to the various logical operation code signals to various functional parts Operations (for example AND-, OR-EXCLUSIVE-OBER-SV-IV-ST-, RS operations) depending on a supplied to execute input signal (LB) having two possible states, and that the control devices (100) further means responsive to the second group of bit signals from the instruction address register when this contains a word having a special code format for the special bit signal from the input register to be transferred as an input signal (LB) to the logical processor, which corresponds to the bit position shown, devices, which respond to the first group of bit signals from the instruction address register when this is a contains a special code format word for supplying logical operation code signals to the logical processor, corresponding to the logical command represented by the first group of bit signals, and means to actuate the logical processor to perform the logical function performed by it then is shown as the input signal supplied code signal. 5. Digital computer according to claim 4, characterized in that the control devices (100) further Include means responsive to the first group of bit signals from the instruction address register, • 09815/0600 27UO6O if this contains a word having a special code format to control the logical processor in such a way that that it processes the input bit signal either in true or in complemented form. Digital computer according to claim 4, characterized in that the first group of bits denies the represents a logical command in any particular command word falls into two categories of code, viz logical processing and bit manipulation, and that the control facilities continue to operate on the address the first group of bit signals from the instruction address register when the function shown is in the the first category falls in order to control the logical processor to have the signaled logical accumulator output (LA) corresponding to a Boolean function processed, which are represented by this first group of bit signals, which are then used as an input signal to the logical Processor, and include means responsive to the first group of bit signals from the instruction address register respond if the function shown falls into the second category, to which the input register supplied word to the memory address position, which is then stored in the command address register is signaled after the bit of this word which forms the input signal (LB) to the logical processor is changed has been or has not been, the change or non-change being determined by the logical command code signals which are fed to the logical processor. Digital computer according to one of the preceding claims, characterized in that some of the words stored in the read-write system memory represent special logic commands, bit addresses within a word and word addresses, that the logic one-bit processor uses Boolean logic working processor 1st, the devices for signaling an accumulated • 09815/0600 * ^{/ #} Output bits (LA) and logic opcode signals includes responsive means for changing the output bit in accordance with the logical operation to which an the one-bit input signal (LB) is carried out that on a special command word taken from the control devices responsive devices for supplying logical operation code signals (LOC) which are taken from one of the Word represented logical command correspond to the logical processor that facilities are provided are provided, which are based on the by the control devices as a result of the extracted special command word address to the arithmetic unit supplied operands to a special bit of the operand, which is the bit address part of the special command, as a one-bit input signal (LE) to the logical processor, and that means for operating the logical processor are arranged to change the accumulated bit so that successive special instructions are selected Bits of desired words can be used to perform Eoolean chain operations according to a program of steps perform, into which arithmetic steps are distributed, the final result being the accumulated Bit signal is shown. 8. Digital computer according to claim 7, characterized in that the control devices have devices to control the arithmetic unit such that no arithmetic operation is performed on the arithmetic unit supplied operands is carried out as a result of the extracted special command word. 9. Digital computer according to claim 7, characterized in that the devices responsive to the operands supplied to the arithmetic unit include devices which respond to any special command word taken from the control devices. • 09816/0600 * ^A speak and control the logic processor so that the in-bit input signal is selectively either in the true or complemented form is processed. 10. Digital computer according to claim 7 »marked lehne t by devices that respond to the signaled state of the accumulated output bit (LA) to the Execution of commands to be influenced by the control devices and the arithmetic unit. 11. Digital computer according to claim 10, characterized in that the usual coded commands and Words representing addresses have an unconditional / conditional designation bit include that the arithmetic system responsive to a extracted command word means to generate a conditional signal if the designation bit in this word indicates "conditional", and for the presence includes devices responsive to the conditional signal to prevent the execution of a removed instruction, if the conditional signal is present »and the signaled accumulated output bit (LA) is a predetermined one of its two possible states. 12. Digital computer according to one of the preceding claims, characterized in that the read z ^ write system memory of the basic arithmetic system is designed for receiving and signaling multi-bit words at a plurality of address locations that some of these words represent coded commands and addresses while others of these words represent numerical data and / or multipath the on / off binary bits, with some of the command address words having a special code format in which a first group of bits represents a logical command (e.g. load, AND, OR, EXCLUSIVE-OR operation) , while a second group of bits 809815/0600 2743Ü6Ü represents a bit position in a word and a third group of bits represents a memory address of a data operand represents that the arithmetic unit has an input register (AIR), an output register (ACCUM, ECR) and a Instruction Address Register (IAR) includes a conduction path between the memory system and the three registers it is provided that the control devices of the basic arithmetic system are consecutive Execute sequences of operations that remove an addressed command word from the memory and store it extracted word in the IAR register, the supply of Data operand word signals from the memory address then signaled by the IAR register Group of bits and the storage of these data operand word signals in the AIR register and the execution of the instruction represented by the first group of bits signaled by the IAR register at this point in time involve the one-bit logical processor facilities for generating an accumulated one-bit logic output signal (LA) and includes means responsive to (a) a one-bit logic input signal (LB) and (b) logic opcode signals that perform various logic functions (e.g., load, UNES OR, EXCLUSIVE-OR link) denote air, the output signal (LA) to change according to the input signal (LB) and the designated logic function (for example LA _n = LA _Q · LB if the function is AND), that the control devices continue Means for determining that the IAR register contains a special format command word requesting some logical operation, Means gen, responsive to this determination to the logical processor as an input signal LB guide the signaled bit zuzu from the bit position of the AIR-register corresponding to the bit position represented by the second bit group signals IAR register of which is shown. 809815/0600 £ 743 060 also responsive to this determination means for supplying operation code signals that of the logical Function represented by the bit signals of the first group from the IAR register to the logical Processor and means for operating the logical processor such that the output bit signal (LA) is changed according to the logical operation determined by the opcode signals and then existing Value of the input and output signals is shown so that the logical output signal (LA) has the value of chain-like Boolean logical operations which are performed sequentially on selected bits of selected memory data words, these operations are executed by program steps that are arbitrarily or accidentally included in the arithmetic operation program steps are inserted and that the input and instruction address registers of the arithmetic unit are both for the Boolean operations as well as for the arithmetic operations Operations are used. I). Digital computer according to claim 12, characterized in that the control means furthermore Include means responsive to opcode signals derived from the bit signals of the first group of derived from the IAR register in order to control the logical processor in such a way that it receives its received input signal (LB) processed in true or complemented form. 14. Digital computer according to claim 5, characterized by devices which respond to the state of the logic output signal (LA) for modifying the operating mode the control devices and the execution of commands, which are entered in the IAR register. 15. Digital computer according to claim 12, characterized in that each usual command and address • 09815/0600 * ^{/ #} word includes an encoding of the command bits to indicate when the arithmetic operation is to be conditionally performed and that further means for generating a conditional signal (CGND) responsive to the first group of signals from the IAR register when the encoding of these bits makes this indication, and means are provided which only respond to the presence of the conditional signal (COND) when the logical output signal has a predetermined one of its two states in order to modify the operation of the control means in order to suppress the execution of the instruction which is represented by the first group of bits which are then signaled by the 'TAh -'.-. c register, so that any programming step which excludes logical operations is selectively dependent on the result of one or more previous ones Boolean logic steps can be done. 16. Digital computer according to one of the preceding claims, characterized in that the read-write system memory of the basic arithmetic system can hold and signal that some of the words have a certain code format for representing commands and addresses, while other words have a code format by which data is represented, with some of the words having a code format in which a first group of bits represents one of a plurality of special logical commands, while a second group of Eits a desired bit address within a word and a third group of bits represents a word address, that the arithmetic unit has multi-bit input and output lines, that the input and output lines are connected to the system memory via a conductive path, that control devices for Generation of successive operational sequences provided are, these operating sequences the removal of a command address word from an address space of the memory and the transfer of this word to • 09815/0600 · /. BATH ORIGINAL / 743Ü6Ü arithmetic unit, the supply of a data word operand from an address location in the system memory to the arithmetic unit where the address space of the address corresponds to that is represented in the extracted word and includes the execution of the instruction with the operand, which is represented by the removed command address word that the control devices continue to have devices to generate some of the operational sequences, the execution of which involves the storage of the signals (ANS) from the output lines of the arithmetic unit in the address space of the memory that corresponds to the address that it is shown by the removed command address word that a logical bit-cannipulator is provided, the operation code inputs (Ll, LO, il2, 114), a one-3it input for receiving the logic signal (LB), and means for generating: a bit control signal (EC) includes, its state both from the operation code signals applied to the inputs and the state of the logical Signal (LB) depends, which is fed to the Ein-Eit input that means for supplying a selected signal of the supplied to the arithmetic unit Data word are provided at the input input, the selected bit signal in its bit level Bit address corresponds to that extracted by the second group of bits in a special logical command address word is shown that devices for supplying logical operation code signals that the logical command correspond to that taken by the first group of bits in a special logical command address word are shown, are provided to the operation code inputs, and that means for supply of the incoming lines of the medical unit Data word to the output lines of the arithmetic Unit are provided, with a selected bit corresponding to the state of the bit control signal (BC) inverted or directionally inverted by the bit manipulator 80981 S / 0600 " ^A. -U- / 7A3ÜBU where this one bit of the E te Hc corresponds to the by the second group of bits in one, extracted particular logical command word is shown, so that the return of the output of the arithmetic unit the memory address space defined by the third group of bits in an extracted special logical command address word is shown, leads to the selected bit of the data word having the desired state. 17. Digital computer according to claim l6, ~ eke η η ζ c ί: ■: r. e by devices for signaling a logical accumulator output (LA), the devices for generating a bit control signal (BC) and the device for forwarding the data word fed to the input lines of the arithmetic unit to the output lines together forming devices which are fed to the arithmetic unit Introduce the data word back into the memory at the original address location, but the selected bit of this data word has the same status as at the accumulator output. 18. Digital computer according to claim 16, characterized in that the Gperationscodeignale supplied by the devices for supplying the operation code signals to the Cperationscodeeein tons represent either SET, RESET or IKVERTIER signals, and that the devices for generating the bit control signal (BC) and the means for transferring the data word fed to the input lines of the arithmetic unit to the output lines together form means for reintroducing the data word fed to the arithmetic unit into the memory at the original address location, but the selected bit of this data word is in the one state 0 or in a state which is inverted from the original state . I09815 / 06Ö0 BATH ORIGINAL 77A306Ü 19. Digital computer me claim 16, characterized g e k e η η ze rejects any of the command address words including those whose format includes first, second and third groups of bits, one in the opcode Drawing includes that the command must be carried out unconditionally or conditionally and that further facilities for signaling a logical accumulator output (LA) and a part of the control devices forming devices are provided, which on any removed and command address word supplied to the arithmetic unit respond to prevent the instruction from executing if it is labeled conditional and the accumulator output (LA) has a predetermined one of the two possible states. 20. Digital computer according to one of the preceding claims, characterized in that the read / write system memory of the basic arithmetic system can accommodate reversible Blt words at a plurality of address locations, that some of the words have a code format for representing ordinary commands and addresses that other of the words have a code format for representing data, that some of the instruction address words have a special code format in which a first group of bits represents one of a plurality of special logical instructions, while a second group of bits represents a desired output address in a word and a third group of bits represents a memory address location of a word that the arithmetic unit includes an input register (AIR), an output register (AOR), an instruction address register (IAR) and a conduction path connecting the input, output and instruction address registers to the memory, that the control unit obligations successive sequences of operation cause that the removal of an instruction address signal from an address signal from an address location of the memory the Uberfüh- • 09815/0600 / 7UÜ6U delivery of this signal to the register (IAR), the supply of data word operand signals from the address space of the memory to the AIR register, this address space corresponding to the address represented by signals from the IAR register, the execution of the function, by the instruction part of the word previously transferred to the IAR register with the data word operand signals from the AIR register and in some cases the transfer of the word signals at the output of the AOR register for storage in the memory, these Storage takes place at the address location which is represented by the instruction address word, which is then signaled by the IAR register that the logical bit manipulator C pe rat ions code-j. Includes input terminals, a one-bit operand input terminal and means for generating a bit control signal (EC), the state of which depends on both the signals supplied to the code input terminals and the signal at the operand input terminal that means for supplying a Lin- Bit input signals (LB) from the AIR register are provided at the operand input terminal, the bit location of this signal corresponding to the bit address represented by the second group of bits in the output signals from the IAR register is, after this contains a extracted special code form is shown in the output signals from the IAR register after this has taken a spec ialbefehlhViort contains that? Devices for supplying the data word signaled by the AIR register to the AOR register are provided, but a selected bit of this word is controlled with respect to its state in accordance with the state of the bit control signals (BC), this device by 109815/0600 ORIGINAL INSPECTED /? 7A306ü Bit signals in the second group controlled by the IAR register so that the position of the selected bit corresponds to the bit address in a special code format command word and that means responsive to the first group of bits in the special code format signals from the IAR register are provided, which are then generated by the AOR register signals back into the memory to the Transfer address location represented by the third group of bits in the signals from the TAR register. 21. Digital computer according to claim 20, characterized in that a logical one-Blt processor the Bit manipulator is assigned and means for generating an accumulated one-bit signal (LA), its State is changed in accordance with a logical processing operation code connected to the operation code input terminals is supplied when successive one-bit input signals (LB) to the one-bit TOperand input terminal and to the accumulated signal (LA) includes responsive means for determining the state of the control signal (BC). 22. Digital computer according to one of the preceding claims, characterized in that the basic arithmetic system includes a Bei'ehlsadressenregister, a system memory, devices for extracting an instruction address word from the memory and for transferring it to the instruction address register, and devices responsive to instruction address signals from the register Execution of the command represented by the extracted word includes that devices are provided for generating a single-bit main control signal (LA) that has two possible states, that devices for generating a conditional signal (COND) responding to the command address signals from the register. are provided when the E command represented by the extracted word • 0981S / 06ÖÖ is so designated that it is conditioned and that institutions to ineffective the facilities for the implementation: the foreseen commands represented by the extracted word sine, urr to prevent the execution of the command when the conditional signal (COND) is present and the main control signal (LA) has a predetermined one of its two states. 23. Digital computer according to claim 22, characterized in that the devices for generating the one-bit main control signal (L / v) have a one-bit processor operating using Eoolean logic, which the main control signal (LA) corresponding to the preceding chain-like ^{Boolean 1} shear operations that are performed thereby. 24. Digital computer according to claim 22, characterized in that means for successive Supply of selected bits of selected words from the system memory as operand inputs to the Boolean 'see Processor together with logical operation commands are provided (for example LD, AN, Oi-I, XR) in the form of words are contained in system memory so that chain-like Boolean operations are performed, to determine the state of the main control signal (LA). 25. Digital computer according to one of the preceding claims, characterized in that the read / write system memory of the basic arithmetic system, a number of multi-bit words at respective address locations can receive and signal that some of the words have a code format for representing commands and addresses have, while other words have a code format for representing data and wherein the E instruction address words have a common code characteristic (for example a 0 or a 1 in the BIO bit), which indicates 1098 1 5 / OSOO · /. ORIGINAL INSPECTED 2743Ü6Ü that the instruction is unconditional or conditional, that the arithmetic unit has an instruction address register (IAR), an arithmetic input register (AIR) and an arithmetic output register (AOR), that a conduction path is provided between the system memory and the registers (IAR, AIR and AOR) is that the control devices generate successive sequences of operations which the removal of signals representing an instruction address word from a programmed memory address location and the transfer to the IAE register, the supply of signals representing a data word from the DspeicheradrtSGcnplatz, which is represented by the removed signals in the IAR register is, for register AIR, the execution of the function which is represented by the signals forming the command word from the IAR register, based on the data words in the AIR register, that means for generating a one-bit main control signal having two possible states (LA) are provided there s changes from time to time, and that means are provided to prevent the control means from performing any function called by an instruction address word that is transferred to the IAR register and signaled as soon as the extracted word and the IAK- Register signals indicate that the illustrated instruction is conditional and when the main control signal has a predetermined one of its two possible states. 26. Digital computer according to one of the preceding claims, characterized in that the system memory of the basic arithmetic system can accommodate a plurality of multi-bit words, some of which are command words and some data words that a reversing bit command address register (IAR) is provided is that devices for transferring various command words from the system memory to the IAR register are provided that with a first predetermined number of bit outputs of the IAR register devices for • 09815/0600 · / · / 7 A 3 ϋ ό ϋ execution of an arithmetic instruction are connected, the is represented by a extracted word with a second predetermined number of bit outputs of the IAR register Means for selecting a bit signal from a selected ^ e hr-B it signal of a word connected signaled elsewhere in the digital computer, the selected bit being a Bit space corresponds to that represented by the code of the second plurality of bit outputs, and that Γinrichtungen are provided for using the selected bit signal. 27. Digital computer according to one of the preceding claims, characterized in that the read / write memory of the arithmetic system has η word locations each with a length of m bits for receiving and signaling multiple-Eit words that some of the words have ordinary commands -Address words with ρ bits, which represent different coded commands, and with np bits, which represent a memory address location of an operand word to be used, that other of the words are special command address words with ρ bits, which represent different special coded commands and with b-bits , which represent one of m different bit locations in a word, v.'obel the remaining npb bits represent a memory address location of an operand word to be used, that the arithmetic unit has an Eefohlsadressenrerister (TΛ70 and an arithmetic input register (ATR) v; e 1st that a Line path between the system memory and the arithmetic unit including incl The registers (IAR) and (. "-. TR) are designed so that control devices are provided for transferring successively programmed instruction address words into the IAR register at the beginning of the successive operation sequences, the control devices having devices which, during each sequence (1. ) the supply of an operand word from the memory location, which corresponds to the code of the np or npb bits, which are signaled by the IAR register, into the AIR register 109815 / 06ÖÖ / · / 743Ü6Ü perform and (2.) perform the function that corresponds to the code of the ρ bits specified by the IAR register it is signaled that devices for receiving the b bit signals from the IAR register are provided, which the Signal of a selected bit from the AIR register to a selected bit port, the selected bit corresponding to a bit location defined by the b bit signals from the IAR register and means for utilizing the selected bit signal are provided on the terminal so that any desired bit of various desired memory words the bit connection by taking a special command address word can be fed. 28. Digital computer according to claim 27, characterized in that the useful devices include a Bode ¹ see logical processor. 29. Digital computer according to claim 28, characterized in that some of the control devices is responsive to the ρ bits signaled by the IAR register so as to set the Boolean logical processor to control that a Boolean function is carried out, which corresponds to the code of the ρ bits in a extracted special command word. 30. Digital computer according to claim 29, denotes marked by means of storing the output signal (LA) of the logical processor to any selected bit location of a desired word location of the System memory. 21. Digital computer according to claim J50, characterized in that the storage devices of the output signal respond to a "backup" code, which is represented by the ρ bits of a special command word that was transferred to the IAR register, • 098 1 S / 0600 · / · that means for supplying a word from the; üpr icher place signaled by the IAR register n-p-b bits are shown in the ATR Rcgister and that on the b input signals from the IAR register appealing facilities to customize the selected Bits of the supplied word to the output signal (LA) the return of the extracted word back to the original Storage space are provided. 32. digital computer according to rincm of the preceding claims, characterized in that ? ir. taktgc :; tcuerter accumulating logical processor without feedback is provided, which responds to an E in-bit input signal (LE) to generate a logical kin-bit response signal (LA) on the result of a "LADE", - "AND" -, " GDER ¹ 'or "EXCLUSIVE-OR" operation, which is represented by function code signals that the processor has a ^T K flip-flop with J and K control connections, a clock input (CP) and an output connection (o) to which the Response signal (LA) appears exclusively on "LAl! E" function code signals and the input signal (LB) responsive devices for supplying a 1-level signal to the .'- or K-connections when the input signal (l £) is on a 1- or an O-level, exclusively to "u:;:" - puncture code signals and the input signal (LB) responsive devices for supplying a 1-level signal to the K terminal only if the input signal (LB) has an O- Level, excluding "OR" function code signals and the E Input signal (LB) responsive devices for supplying a 1-level signal to the J-connection only if the input signal (LB) has a 1-level, and exclusively to "EXCLUSIVE-OR" function code signals and the input signal (LE) Responsive means for supplying a 1-level signal to the .T- and the K-terminal only when the input signal LB has a 1-level, include that the above • 098 1 S / 0600 · / · BATH ORIGINAL / 7A3Ü6Ü Executions mentioned include devices that apply 0-level signals to the T and K connections with the exception of the above-mentioned cases that further devices for supplying a pulse to the clock input of the TK-Fllpflops are provided if one of the above-mentioned devices the respectively specified Has applied 1-level signals so that the response signal (LA) has a new value (LA) having two possible states in accordance with the Boolean functions LA _n = LD, LA _n = LA · LB, LA = LA +113 or LA = LA (+) LB regardless of the no no Fact assumes that the signal LA does not participate in the operation of the aforementioned devices. Digital computer according to claim yi, gekennzeichn et by devices for the selective inversion of the input signal LB before it is fed to the devices for determining the levels at the J and K connections, so that the processor responds to the input signal in true or complemented form appeals to. Digital computer according to claim 32, characterized in that g e k * e η η draws, that the level at the .T and K terminals controlling devices means for supply a 1-level signal to the T-terminal whenever the input signal has a 1-level and when the opcode signals a "LOAD", "OR" or " "EXCLUSIVE-OR" function denotes and facilities for feeding a 1-level signal to the K connection always include when the input signal is one Has 1 level and the opcode signals reject an "EXCLUSIVE-OR" function tee or if the input signal has an 0 level and the operation code signals denote a "LOAD" or "UiJD" function. 109815/0600 / Ί U 3 C) h U 35 · Digital computer according to claim yh, characterized in that the devices controlling the level at the J terminal have a first AND gate which receives the input signal (LB) and which is actuated by any operation code signals with the exception of the information code signals The "AND" function denotes that the devices controlling the level at the K terminal have an EXXLUSIVE-OR gate which is used to receive the input signal (LB) and an "enable-inverted" signal of iodine signals which represent a "CHARGE" - or "AND" function, is switched on, and have a second AND gate which receives the output of the EXCLUSIVE CDER gate is operated by any operation code signals, with the exception of the code signals which designate an "OR" function and that the outputs of the first and second AND gates are connected to the .T and K terminals, respectively. J56. Digital computer according to claim 35, characterized in that the operation code signals three each two possible status signals (L2, Ll, LO), which are encoded so that "LOADING" as 1,1 *, 1; "AND" as 1,0,1; "OR" as 0,1,0 and "EXCLUSIVE-OR" as 1,1,0 denotes 1st and that the signal Ll as an input to the first AND gate is supplied while the signal LC is fed to the EXCLUSIVE-OR gate and the signal L2 is fed to the second AND gate. Digital computer according to one of the preceding claims, characterized in that a clock-controlled accumulating logic processor without feedback is provided which responds to a single input signal (LB) having two possible states in order to generate a single response signal (LA) having two possible states to the result of a "LOAD ¹¹ -," AND "-," OR ¹¹ - or "EXCLUSIVE-OR" operation to convert, which is represented by function code signals that the processor has a JK flip IO981 5 / 060Ö BATH ORIGINAL 2743Ü60 flop with J and K 3 control connections, a clock indane and an output connection (Q) at which the response signal (LA) appears, devices for supplying a 1-level signal to the! connection only if the input signal (113) has a 1 Level and the function code signals designate any operation with the exception of the "AND" operation denote an "AND" operation or when the input signal is 1 level and the function code signals denote an "EXCLUSIVE CDLR" operation, and means for supplying a clock pulse to the clock input after any function code signals and the input signal (LE) to the above mentioned facilities, includes, and that the response signal (LA) has a new value (LA _n ) corresponding to the Boolean functions (LA "= LB) f ür "LADEN", LA "= LA" · LB for "AND", LA _n = LA + LB for "OR" and LA _n = LA _Q © LB assumes, regardless of the fact that the response signal is not to the the above »facilities are in place and do not affect their mode of operation. 809815/0600