DE2739615A1 - LSI semiconductor store unit - is formed so that each area can be tested before connection and only fully operable areas are connected - Google Patents

Abstract

The store unit is in the form of an undivided semiconductor chip with internal central control and selection circuits in addition to the storage field proper. The total circuits on the chip is divided into redundant areas, so that more areas of each type are available than is functionally necessary. Each area which can be replaced by another area of the same type is provided with additional metallisation spots for test signals application, so that it can be tested for perfect functioning. Only fully operable areas are connected with other areas or to the supply voltage.

Description

Large-scale integrated semiconductor memory module in the form of a

undivided semiconductor wafer.

The invention relates to a large-scale integrated semiconductor memory module in the form of an undivided semiconductor wafer with internally arranged central circuits, like control and selection circuits next to the actual memory field.

Semiconductor memory components are - calculated per memory cell - around the cheaper, the cheaper the finished semiconductor wafers, the so-called Wafers are what make the wafers today, the so-called chips for the individual Semiconductor memory components are obtained by dividing the more storage locations are housed on a chip and the more usable chips a semiconductor wafer owns on average. At present, with a doubling of the packing density, i. the number of active elements per unit area, and a simultaneous doubling the optimal platelet size within a period of three years expected. Both influencing variables mean a reduction in the cost of storage per storage location and at the same time an increase in reliability. The latter results from the fact that in the case of large components, fewer contact points per memory location to be attached to chips are.

This development can be achieved by moving to the largest possible chips, i.e. an undivided semiconductor wafer can be accelerated. The goal is the construction of large, moderately fast memory for data processors Systems with a storage capacity of more than 10 M bytes with an access time of less than a microsecond. The reliability in operation such a working memory should be at least as large as that the smaller main memory that is common today. This development step is natural only with modern, but already manageable, technological ones according to the prerequisites Procedure to be carried out.

In this context it is well known that it is currently hopeless is to produce semiconductor wafers that are well utilized in terms of area. Around With the technological processes mastered today, it is nevertheless an economical one To obtain yield, therefore, has hitherto been a semiconductor wafer in a plurality divided by surface areas in which the same masking or etching processes in parallel or process steps for building diffusion layers or epitaxial layers are executed. A completely treated semiconductor wafer then has in these Area areas each have identical circuit arrangements, e.g. a memory arrangement.

By dividing the finished semiconductor wafer into a large number of chips, which each have such a surface area, by contacting them of external connection lines, by embedding in a housing and contacting them of the connecting lines to external housing connections is then created from this in each case a finished building block. As a first approximation, the probability for one increases improved yield, i.e. the ratio between the number of defect-free chips and the total amount of all building blocks produced, the smaller the surface area of a building block.

There has therefore been no shortage of attempts to look for ways of how individual errors or faulty memory areas in a memory module are harmless can be made so that faulty memory modules can still be used are. An elegant method of rendering imperfections in a store harmless. chen, is the use of error-correcting informational code that causes so many errors Allow correcting, as expected as the maximum number of faulty bits in a memory word will. Such multiple errors can also be corrected with convolutional codes, which, however, only contains several errors in an im able to remedy the remaining error-free memory word.

There is always a difficulty in correcting multiple errors in the fact that in the codes used for this purpose, the ratio of the number of correctable Error for the necessary redundancy is still very unfavorable.

Another well-known replacement and correction method was for magnetic Memory or larger systems are proposed, which consists in storing words in memory several times to read and re-enroll. But it is for memories made from undivided semiconductor wafers insufficient, since it is based on the assumption that only a few small memory areas are defective.

Effective means of improving the yield are known methods, which mark defective memory areas through technological interventions or bypass. However, these procedures require special processes for targeted changes on memory cells or their connections. Because of the partly individual conductor tracks such processes in the known form may be too expensive. Furthermore is it is known to sort memory modules according to where they are defective Contain partial areas and then use these blocks in a memory in such a way that that from the address of a memory word it can be concluded which bit position this memory word can be faulty. With this method you can opposite save redundancy with other correction methods, but it is necessary for large error densities no longer sufficiently effective.

According to the known prior art, on the other hand, there are correction methods particularly advantageous in which defective memory areas are bypassed by readdressing will. This is done in a memory module that precedes the actual memory module Auxiliary storage preferably a programmable read-only memory, Defective memory areas identified and by recoding the memory address replaced by perfect memory areas. If the content of the upstream Auxiliary memory can also be changed later, so many can, first Identify errors in the memory module that occur during operation and bypass.

The invention is therefore based on the object of a large-scale integrated To create semiconductor memory device of the type mentioned, with a economic yield can be produced by means of manufacturing technologies that are manageable today is where, in particular, the increased potential for errors caused by a greater Number of active elements on a chip, namely the undivided semiconductor wafer be mastered. This object is achieved according to the invention in that the entirety of the circuits combined on the semiconductor wafer in each case in redundant form executed areas is divided so that more areas of each type to choose from stand as functionally required that each area passed by another Area of the same type can be replaced geometrically and functionally by additional ones Metallization patches for test signal connections is designed so that it almost must be fully checked for proper function and that only fully functional Areas conductively connected to the other or connected to operating voltage are.

This solution has the following advantage: In the structure structured in this way of a semiconductor memory is already the failure of defective areas, both at central circuits as well as in the actual storage area. This structure offers the possibility of eliminating defective areas from the outset; however, a semiconductor wafer can still be used as long as there is only one sufficient Number of functional areas of each type is available. The functional ones Areas can be made up with a few individual line connections, in particular for connecting signal voltages to the tested and functional areas merge into one unit.

As further developments of the invention described in the subclaims There are quite a number of ways to show this additional short Establish line connections that depend on the scope of a series production but also the prevailing errors in one form or another are to be added.

Embodiments of the invention are shown below with reference to the drawing described in more detail. 1 shows an undivided semiconductor wafer in schematic form Representation with the areal division of the memory areas, FIG. 2 a Excerpt from the representation according to FIG. 1 for an 8 K memory area, FIG. 3 a schematic block diagram for a 32 K memory module and FIG. 4, 5 and 6 each an example of embodiments of zentra len circuit parts in Detail.

In Fig. 1, the areal subdivision of an undivided Semiconductor wafer shown in 36 storage areas Si to S32 or SR, which are shown in FIG Based on conventional manufacturing technologies as "virtual" memory modules can be understood and each should have a capacity of 8 K bytes, where 1 byte comprises 4 bits. The memory elements of these virtual memory modules are designed like conventional dynamic MOS memory cells. So here is not elaborated on this.

However, the rough structure of this memory structure shows that eight Memory areas, e.g. S1 to S8 together with a reserve area SR a memory block form, which is connected to central circuits ZS via central connecting lines ZL via which the memory module exchanges the external signals.

The block of the central circuits is no longer shown here. - divided into two parts of about the same size and thus circuit groups, each part of which contains the same circuits three times in order for necessary redundancy to take care of errors. The mentioned circuits of the memory module are located Everyone essentially within an inner area surrounded by an edge line RL1 the semiconductor wafer, in which the lowest density of defects is expected can.

Another area between this edge line RL1 and one Another edge line RL2 is theoretically already with an increasing density of defects afflicted. Because the marginal zones defined with it because of a relatively high density of imperfections can only contribute little to the total storage capacity of the semiconductor wafer, these remain free from the start and contain active semiconductor circuits only lines from or to the semiconductor wafer with the active memory areas and central circuits. These are mainly potential lines 0V-L, + 5 V-L and + 12 V-L.

In Fig. 2 is a section of this planar division of the Undivided semiconductor wafer for an 8 K memory area shown in more detail. Between the ground potential, indicated by two potential lines 0V-L, there is a surface area defined by a length L and a width B, which is one of the 8 K memory areas Sn takes up. The actual area has the largest share in terms of area Storage area with 2 x 2 K storage cells SZ, on both sides of 2 x 64 evaluation circuits BW are arranged. Left or right justified close to this storage area Areas for 2 x 64 word decoders W-DEK. These decoding circuits are also provided twice as 2 x 64 flush-connected beneath the storage area Bit decoder B-DER. Buffer circuits are assigned to the decoding circuits AWB or ABB for the word or the prefix of a memory address.

The address itself is shown over here schematically as a connection pad ADR connections supplied. Additionally, finally, are on top of that the storage area then, compensation circuits KP provided. The remaining one Space between these and the potential line 0V-L above stands for here Lines not shown between the word decoders W-DEK and the word address buffers AWB available.

Others are also to be regarded as internal with regard to this memory area Tending control and signal lines are not shown in FIG.

This is different with the actual potential lines. Here are schematically shown connection pads AF, over which the multiple redundant provided Partial circuits of this memory area can be supplied with the operating potentials individually are.

An overview of the functional interconnection of the individual Subcircuits of this shown with reference to FIGS. 1 and 2 in an areal division The block diagram of FIG. 3 gives the memory module. This block diagram for a 32 memory module initially contains memory blocks corresponding to the memory blocks shown in planar form in FIG. 1 each have 8 memory areas e.g. S1 to S8 and a reserve area SR.

The remaining circuits shown in further blocks in FIG. 3 are to be assigned to the central circuits ZS. These are in particular selection, control, Data input and data output circuits as well as internal logic circuits. The external signal connections for the corresponding address or

Control signals marked with ~ * ~. Are redundant circuits If such signals are to be fed in twice, corresponding signal connections must also be included , I ** fl.

In addition to address input circuits W-AD, B-AD, C-AD for the word, Bit or chip address with the specified address connections A ~ * to A17 * the input side of the memory module a release circuit CE, the so-called "Chip Enable" circuit shown in Fig. 4 as an example of such an input circuit is shown in detail. This circuit example shows that also with this Memory module the so-called "Chip Enable" signal CE * as in conventional memory modules is processed, with the one restriction that output circuits are redundant are provided that then four paired comparable release signals CEG, CEG 'and CEG bzs. Run EEFI.

There are still input flip-flops on the input side of the memory module for control signals, such as the so-called "refresh signal RF *" or an operations signal L / S * for a memory op- ration "read" or "write" shown. The input side also contains redundantly provided data input circuits DI, to which the data paths with the input signals DI1 * to D14 * or DI1 ** to Dz4 ** assigned.

The output signals of these input circuits are each to one connected by two address release circuits ADE1 and ADE2. There are those Output signals A # 'to 7T t of the input circuits for the word and the bit address W-AD or B-AD to the first of these two circuits, the output signals of the others Input circuits connected to the second address enable circuit ADE2. The circuitry implementation of this circuit is shown in detail in FIG. 5 in reproduced in a section. Here, in one input circuit, the two mutually inverse signal states, for example a bit position from the chip address A13 'or A13' in a NOR circuit with each other and with an enable signal CEG ' to one and linked.

All output signals processed in this way from the connected input circuits are in parallel via a decoupling transistor of the common evaluation circuit which derives the address release signals, e.g. AE2, from it.

According to Fig. 3 are to form the word and bit address or the chip address Decoding circuits A-DEK or C-DEK are provided, which are connected to the outputs of the input circuits for the word and bit address or for the chip address are connected are. The second of these decoding circuits C-DEK has chip enable circuits on the output side CE1 to CE4 connected, each one of the blocks for the memory areas SN assigned.

An example of a detailed circuit that is partially that of the central Address decoding circuit A-DEK assigned to circuits, partially one of the memory areas To be assigned to Sn is shown in FIG. 6. Here is where the central circuit attributable left part an output signal An 'of the address input circuits with Block release signals r T linked and thus an output signal Ang is formed. This address nal for a memory area Sn is there, in turn linked with module and address release signals 5r or AE1 and buffered.

The output signals of this buffer circuit An and xn form a pair the address signals for a memory area Sn.

As shown in Fig. 3, the central circuits continue to assign a selection circuit CS, in which a block # enable signal FEZT with linked to an output signal of the refresh input circuit RF to form a selection signal that is fed to the individual memory areas Sn in parallel. In the end this also includes a data output circuit DO, in which output flip-flops to the Data outputs of the memory areas Sn are connected in parallel, their output signals D01 * to Do4 * represent the 4 bit positions of a read memory word. In Fig. 3 it is no longer shown that this memory module can also be used as a 64 R or 128 K memory module can be organized in which two bits or only one bit is the smallest addressable Represent unity. In this case they are also in the central circuits on the input side further flip-flops are provided, which the control signals for this Store operating modes and their output signals to the chip enable circuits CE1 to CE4 and the data output circuits DO.

This memory module described with reference to FIGS. 3 to 6 is located The following functional concept is based on: The control signals for the semiconductor wafer are the same in nature as any other conventional dynamic MOS memory chip. All inputs and outputs are TTL-compatible The storage capacity of the memory module is 32 K x 4 bits. With special input signals, which can be set to 0 or + 12 V externally, is also a storage mode possible with a memory organization of 64 K x 2 or 328 K x 1 bit. A refresh control signal enables it to be in each of the four memory blocks, but also in each of the 8 K memory areas to regenerate 128 bits of stored information at the same time. Here is the power supply with a sufficiently low resistance to the individual memory areas. At a Refresh The data outputs of the 8 K memory areas become the cycle blocked.

Except for the direct ones familiar from conventional memory modules Inputs for the data bit positions and a write signal are provided, which these signals as well as the address bit positions at the beginning of a memory cycle allow buffering, for a memory that does not have to be able to read-write cycle, This simplifies the control. The data output signals are in flip-flops cached until a new storage cycle begins.

To reduce crosstalk on the signal lines between the 8 K memory areas and the central circuits of the semiconductor wafer worked on these lines with a voltage swing of + 5 V.

In addition to the block diagram explained in FIG note that the address input circuits for the address bit positions A10 * to A16 * must be set up separately for each memory block. There are still only 32 Chip enable lines Crn are provided, although there are also four other spare memory areas SR are given. This gives the possibility of an intact reserve area to the corresponding chip release line of another non-usable memory area of the same memory block. Apart from that, however, is for everyone Storage area of the semiconductor wafer has its own central chip enable amplifier intended.

Except for these amplifiers, all central circuits are double or executed three times. They are grouped together and only free from defects Groups are connected to the operating voltage, i.e. to a + 12 V-L potential line.

The specific possible sources of error in such a one-off memory chip built up on an undivided semiconductor wafer are faults on the central wafer lines to be expected. There are conclusions or interruptions Al conductors, connections or interruptions in diffused cross connections between the AL conductor tracks and the memory areas as well as thick oxide defects, i.e. conclusions between Al and Si, but also dilnoxide errors in the lines directly connected transistors conceivable. The chip enable lines CEn, from which each only runs to a single memory area, can here because of the rest Possible errors are neglected.

Because of this and others, even with conventional memory modules possible, therefore well-known sources of error are a part of the circuits on the Semiconductor wafer provided as redundancy.

A little more than half of the circuits are redundant, i.

H. can be made available for use if others, ugly circuits fail. These similar subcircuits are like this constructed that they have additional Metallisierwigsflek ken on the in one Test probes can be attached and can therefore be tested independently. During this test, the central circuits are checked for function first, then each individual sub-area of the 8 K memory areas for itself.

Finally, it is checked which of these 1 K sub-areas is within of a memory area influence each other. The results of these exams provide a plan for individual connections and an address translation table for programming a programmable one to be connected upstream of the semiconductor wafer Read-only memory.

For step-by-step testing of different sections of the semiconductor wafer the mentioned additional Metallisierungsflek ken as test points to put on of test probes especially at the interface between the central circuits and the individual 8 K memory areas. The division of the semiconductor wafer in individual, separately testable areas is absolutely necessary if one takes into account how the test time is already extended with a transition from 1 K to 4 K sub-areas.

After the memory module has been encapsulated in a housing and a possibly "burn-in" these tests are repeated. Included can Deviations, unless they have led to a total failure of the memory module still taken into account when programming the read-only memory to be connected upstream will.

After this functional test, the operating voltage, i.e. the 12 V potential line 12 V-L only to those memory areas or sub-circuits of the central circuits who have passed this test with no errors. Because of only today mastered technologies, it should also be preferable to also collect the or distribution lines from or to the individual storage areas individually to manufacture.

Stand as manufacturing techniques for such individual connections several options are available: In particular, the connection of error-free Part of the circuits to the operating voltage is through known thermocompression methods possible. For individual connections from central lines to or from the storage areas however, this technique is relatively expensive. Instead, such Conductor tracks, for example, by re-metallizing those that have already been passivated Surface of the semiconductor wafer and by etching this new metallization up on the desired conductor bridges and the bonding pads for external connections. Another possibility is to place the silicon at the desired connection points to uncover and the connectors subsequently conductive by ion implantation close. Finally, there is also contact between the aluminum and silicon layers possible by means of individually controlled laser beams. Choosing one of these The method is particularly dependent on the fact that there is a large tolerance range has in the safe area, so these conductor bridges are only slightly susceptible to errors exhibit.

5 claims 6 figures L e r s e i t e

Claims (5)

Patent application for a large-scale integrated semiconductor memory module in the form of an undivided semiconductor wafer with internally arranged central circuits, like control and selection circuits next to the actual memory field, d a d u r c h e k e n n n z e i c h n e t that the entirety of the on the semiconductor wafer summarized circuits are each divided into redundant areas so that there are more areas of each type to choose from than are functionally required are that each area that can be replaced by another area of the same type is geometrically and functionally through additional metallization spots for Prüfsig nalan connections is designed so that it is almost completely flawless Function is to be checked and that only fully functional areas with the others are conductively connected or connected to the operating voltage. 2. Large-scale integrated semiconductor memory module according to claim 1, characterized characterized in that the line connections required after testing, in particular the connections to a potential line carrying the operating voltage as so-called Bond lines are designed according to a thermocompression process. 3. Large-scale integrated semiconductor memory module according to claim 1, characterized characterized in that the line connections required after testing individual areas by repeated metallization of the already passivated surface the semiconductor wafer and paragraphs of this new metal layer down to the desired Conductor bridges, apart from the connection pads for external ones, which are required anyway Connections to the housing are made. 4. Large-scale integrated semiconductor memory module according to claim 1, ^ by characterized in that the line connections required after testing individual areas by exposing the silicon within Si conductor tracks the desired connection points and then making these connection points conductive are made by ion implantation. 5. Large-scale integrated semiconductor memory module according to claim 1, characterized characterized in that the line connections required after testing individual areas by contacting between one metal and one Si conductor track piece within the desired conductor tracks by means of an individually controlled laser beam are made.