DE2737983A1 - CIRCUIT ARRANGEMENT FOR GENERATING A DELAY AND / OR DAMPING - Google Patents

Description

P ο t e η t π η w d I τ e Dip !. Ing.H.ms-Jürgen Müller Dr. rer. Lut. 'Πιοίταη Berendt

Lucile-Grahn-StroBe 38 D 8 Viunchen 80

Our reference: A 14 Lh / fi

FERRANTI LIMITED

Hollinwood, Lancashire, England

Circuit arrangement for generating a delay and / or a damping

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The invention relates to a circuit arrangement for generating delay and / or attenuation of a single input signal at a plurality of separate output connections.

It relates in particular to a circuit arrangement for multiple delay and / or attenuation of a single one Analog signal.

Particularly in the field of simulators, it is desirable to apply a single analog input signal to each of a number of output terminals, but in each case the analog signal should be subjected to certain variable and different conditions in terms of time delay and / or attenuation. Such signal treatment can be carried out using a number of separate analog circuits, but this is very expensive since a large number of circuits are required.

The invention is therefore based on the object of designing a circuit arrangement of the type mentioned at the outset in such a way that that the aforementioned disadvantages are avoided.

According to the invention this is achieved by a first memory device for storing information that defines each separate delay period that is imposed on the input signal, a delay device to impose the delay periods on the signal, a second memory device for storing information that defines the attenuation that each Input signal is applied, attenuation devices to generate the attenuation and to apply the signal, a control device for controlling the storage of the information in the first and

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of the second storage device and sequentially the separate delay information and the attenuation information to be applied to the delay means and the attenuator means, and by an output means to apply each modified input signal to the to place the corresponding output terminal.

An example embodiment of the invention is explained below with reference to the drawing, the single figure of which is a block diagram of the invention in conjunction with a sonar simulator shows.

In a sonar system, for example, a field of eight receiving transducers is arranged in a circle to enable the receiving or Form receiving station. Any signal received by the receiving station has a certain amplitude, from which the area or the distance can be derived. The direction of the signal source can be determined from the relative Times can be determined in which the signal is received by each transducer. Provides in a simulated system thus a change in the time delay course applied to the conventional sonar unit, changes the bearing of the simulated target, while an attenuation of the signals changes in the range or the distance of the Represents the goal.

The circuit arrangement has two inputs. One input AI is the analog input signal that represents the normal sound of a particular object or vessel. The other input CI starts a number of parallel inputs from a computer defining the attenuation and delay to be applied.

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In order to achieve a considerable attenuation range, are two attenuators are provided in the circuit arrangement. One of these elements is the analog signal attenuator AA, to which the analog input signal is applied. The strenght the attenuation, which is common to all converters and which can be changed in moderately coarse steps, is determined by the computer inputs, which are temporarily stored in the buffer memory CBS get saved.

A memory AWS stores the decoded computer information relating to a further attenuation that is applied to the input signal is placed, whereby this attenuation can be different for the different converters. This storage AWS receives its inputs from the buffer memory CBS and stores the attenuation information for each of the eight outputs which simulate the eight transducers of the receiving station. The memory AWS also has a control input that is applied by a function selector FS, which is also operated by the computer outputs.

A data selector DS receives from the computer buffer memory CBS a sequence of information which represents each separate converter in a predetermined sequence. The information is given to the first storage facility AWS and then to a second storage facility DWS. This second memory receives the Delay information from the buffer memory CBS and stores it at addresses indicated by the data selector DS will. The memory DWS also receives the output of the function selector FS. The work of the data selector DS will controlled by a converter counter TC, which periodically receives up to nine clock pulses CK from a central clock (not shown) counts. The output of the delay memory DWS is counted with a memory address counter MC summarized in a digital adder DA, the

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Counter MC is clocked by the output of the converter counter.

The analog signal emitted by the attenuator AA is passed through an analog / digital converter ADC and then as a parallel 6-bit output to a memory with direct access RAM. In practice, this memory consists of six separate memories, each of which Can store 256 separate bits. The storage and reading of the memory RAM is carried out by the converter counter TC controlled and addressed by the output of the digital adder DA. The 6-bit output of the RAM memory is on Attenuators ATT given, the attenuation of which is set by the output of the memory AWS. The muted digital signals are stored in a temporary memory TS as they occur and they are read out and connected to the eight output terminals via digital / analog converter DAC. The temporary storage TS is through a Decoder DC controlled, which receives clock signals CK and information from the converter memory TC.

The operation of the circuit is described in detail below.

The analog input signal is continuously applied to input AA and through the analog attenuator AA and the Analog / digital converter ADC led.

Set the series of computer input signals applied to the buffer memory CBS and the function selector FS the delay and / or attenuation to be applied. The signals are successively in a predetermined cycle applied and the function selector FS shows through the memory of its output whether the existing at the same time Computer signals represent a delay or an attenuation.

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First of all, the analog input signal AI should be considered. This signal passes through the analog attenuator AA, in which a certain degree of attenuation is applied to the signal, as indicated by an output of the buffer memory CBS. The damped signal is then digitized by the analog / digital converter ADC, from which it is called a parallel 6-bit output exits. This signal is then applied to the memory RAM at addresses specified by the converter address counter TC can be determined. This counter is activated by a clock pulse and it repeatedly counts up to nine such impulses. Eight of these periods are used to read information from different memories, while the ninth pulse of the period, which occurs every microsecond, is used to convert information into the To write memory and via the memory address counter MC in the memory RAM. In the case of memory RAM the digitizing six-bit signal is transferred to the first memory location by the first write pulse from the address counter MC enrolled. The next write pulse, a microsecond later, has the consequence that the digitized signal, which then is present, is written into the second memory location, etc. After 256 write pulses, the memory is full, with location 256 holds the latest information while location 1 holds the information, the 256 microseconds was previously generated.

At the same time that the digitized signal is stored in the memory RAM , the information representing the delay that is to be applied to each of the eight outputs is stored in the delay memory DWS. The output of the buffer memory CBS at any point in time includes both the identity of the simulated transducer and the corresponding delay, assuming that the function switch FS has determined that this output relates to a delay. The data selector DS sends this signal to the

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Delay memory DWS placed so that In a place that refers to this converter, the corresponding delay information is stored. If eight consecutive Write pulses from the converter counter are applied when the corresponding data are at the output of the buffer memory CBS, then the delay information that is based on refers to each converter, stored.

One period of the converter counter TC contains eight read pulses which are used to read information from the delay memory DWS. When read from this memory is, the output is through the digital adder DA with the number or count of the memory address counter MC added so that the corresponding location of the RAM memory is read. For example, if the information stored in the memory DWS, if the memory counter is everywhere If it is zero, represents a delay of 5 microseconds, then the output of the digital adder also represents represents a delay of 5 microseconds. This leads to a readout from the memory location that digitized the Signal that was stored 5 microseconds later than the one that represents the delay. In the same Way if the delay is 134 microseconds and the memory counter is set to 7 microseconds, that corresponds to location 7, then memory location 8 represents a zero delay and memory location 142 represents a 134 microsecond delay. The actually addressed memory location is the one that has a delay of Represents microseconds. Thus, the appropriate digital signal can be generated and displayed with respect to each simulated transducer the attenuator ATT can be placed.

As mentioned above, the analog signal can already be attenuated before it is digitized and stored in the memory RAM.

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-X-

This damping is the same for all simulated converters. The attenuation that applies to each of the transducers is through determines the output of the buffer memory CBS at the point in time at which the function selector indicates that a Attenuation information is supplied and it is also accompanied by information that the in question Converter identified. This information is stored in the attenuation memory AWS via the data selector DS in the same way as the delay information was stored, i.e. once during each counting period of the converter memory TC. In the same way, the information from the attenuation memory AWS during the eight read pulse periods in each Counting period of the counter TC read. The output from the memory AWS at any point in time sets the attenuator ATT to the digitized 6-bit signal to give the desired degree of attenuation, which is read from the memory RAM, as described above.

The attenuator provides e.g. eight degrees of attenuation, from zero to the maximum, and each successive output from Memory RAM is subjected to the required degree of damping and then in a part of the temporary memory TS stored according to the transducer it represents and under the control of the decoder DC. After eight consecutive reading periods, the temporary memory contains TS digital signals that relate to all eight simulated converters. A single pulse from decoder DC causes · all information from the temporary Memory is read out at the same time, converted into analog form by the eight digital / analog converters DAC and that it is then applied to the eight output terminals.

The various work steps described are part of a continuous process. The computer information will

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updated every few seconds while reading and Inscribed information stored in Ar is done as the simulated situation changes.

The circuit arrangement described can be expanded to simulate more than eight transducers and it can be designed so that it has more than one analog input receives.

The circuit arrangement can also be used in other fields where there is a multiple delay and / or attenuation is to be applied to one or more signals.

Clock circuits, timing circuits and gate circuits, have been omitted from the circuit for reasons of clarity.

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Claims (10)

Claims 1. Circuit arrangement for generating a delay and / or attenuation of an input signal at a plurality of separate output terminals, characterized by a first memory device for storing information defining each separate storage period imposed on the input signal, delay means for imposing the delay periods on the signal, a second Storage means for storing information defining the attenuation applied to each input signal, attenuation means for the To apply attenuation, control devices to control the storage of the information in the first and the second storage device and successively the separate Delay information and the attenuation information to select them to the delay device and to apply the attenuator means, and through output means, to apply each modified input signal to the corresponding output terminal place. 2. Circuit arrangement according to claim 1, characterized in that a common memory device is provided to both the delay information and the attenuation information store, as well as a selection device to the information in the common memory device accordingly to place the first or the second storage device. ORIGINAL INSPECTED 809810/0746 3. Circuit arrangement according to claim 1 or 2, characterized in that the delay device has a memory in which the input signal is successively transferred to separate memory locations is placed. 4. Circuit arrangement according to claim 2 or 3, characterized in that the control device address means for determining the address in the memory containing the input signal which has been delayed to the extent that it is due to the special memory location in the first Storage device is determined. 5. Circuit arrangement according to claim 4, characterized in that the address device an adder to the delay stored in a particular memory location of the first memory device is stored, with a further delay to add by a predetermined Relationship between the separate outputs is determined. 6. Circuit arrangement according to one of the preceding claims, characterized in that that the damping device has an attenuator which can be adjusted to different damping strengths is as determined by the contents of the second memory and that each output is the Delay unit is successively applied to the attenuator. 7. Circuit arrangement according to one of claims 1 to 6, characterized in that the output 809810/0746 input means means for storing each having separate delayed and attenuated signals, and means for applying these signals one after the other to the corresponding output terminals. 8. Circuit arrangement according to one of the preceding claims, characterized in that Means are provided in order to apply an attenuation to the input signal for all outputs is the same. 9. Circuit arrangement according to one of claims 1 to 8, characterized in that the input signal is an analog signal, and that devices are provided to the input signal to digitize before it is applied to the delay device and to the damping device. 10. Circuit arrangement according to claim 9, characterized in that the output device has a device for each output terminal, to convert the delayed and attenuated signals into analog Reshape shape. 809810/0746