DE2736368A1 - Aperture correction circuit for video signals - has full adders and digital delay circuits giving correction signals - Google Patents

Abstract

The circuit includes a first full adder (5) to which the digital video signal is fed directly and inverted and delayed. There is a second full adder (7) to which are fed the output of the first adder and the inverted and delayed video signal. There is a store (10) to which the output of the second adder (7) is fed, a third full adder (11) to which the output of the store and the inverted and delayed video signal are fed, and an overrun logic (14) to whose input the output of the third adder is fed and from whose output the aperture-coreected digital video signal is taken.

Description

short version

A method and a circuit arrangement for aperture correction are disclosed of a digital video signal. With full adders and digital delay stages a digital correction signal is derived, which is stored in a read-only memory is influenced depending on the signal value before the digital video signal to be corrected is added.

PRIOR ART The invention is based on a method for aperture correction a digital video signal according to the preamble of the main claim.

One such method is from the magazine: "The Royal Television Society Journal ", Sept./Oct. 1973, pages 261 to 264, in particular page 262. However, this known method is very sensitive to interference with respect to small signal-to-noise ratios in the video signal to be corrected. In addition, one is implemented using this method Circuit arrangement relatively complex in terms of circuitry.

The object of the present invention is therefore to provide a method and a Scnaltungsanordr.ung according to the type mentioned to indicate which these disadvantages do not exhibit.

Advantages of the invention The method according to the invention with the characterizing Features of the main claim has the advantage that a digital Evaluation Influence on the function value curve of the digital correction signal can be taken. A read-only memory in the correction signal path takes over the digital one Valuation. The measures listed in the subclaims can do the same Circuit arrangement by simply changing the delay time of the delay stages for both horizontal and vertical aperture correction of a digital Video signal can be used. Frequency dividers previously required can be omitted.

Drawing Further advantages and details of the invention are shown in following in one embodiment with a drawing based on several figures described and explained in more detail. The figures show: FIG. 1 a block diagram according to the invention, FIG. 2 a graphical representation of the transmission behavior of the read-only memory and Fig. 3 timing diagrams to explain the block diagram.

Description of the invention The block diagram of Figure 1 shows a Circuit arrangement for the horizontal aperture correction of a digital video signal.

The digital video signal can, for example, consist of an analog video signal be derived. The derivation is usually carried out by means of an analog / digital converter. This process is shown schematically in FIG. A terminal 1 is used the analog video signal BA fed to an analog / digital converter 2 at its output an n-bit PCM-coded video signal should be removable. The analog / digital converter 2 contains a sampling circuit which, depending on the at one Clamp 3 lying sampling pulse signal f samples the analog video signal BA in terms of amplitude. The sampled amplitude values are then used in the analog / digital converter 2 quantized and pulse code modulated. The n bit PCM video signal should be at the output of the analog / digital converter 2 are present in parallel. In the following Example n = 8 can be assumed.

The digital video signal is used once for horizontal aperture correction a D flip-flop 4 and, on the other hand, an input of a full adder 5. In the D flip-flop 4, the digital video signal is one clock period of the on terminal 3 lying sampling pulse signal fA delayed, that is, by one pixel period. The inverted output of the D flip-flop 4 is connected to another input of the full adder 5 connected. A carry input (Rlemme 6) of the full adder 5 is present Voltage level that corresponds to the logic potential H. Will be instantaneous digital video signal denoted by A and delayed by one pixel period and inverted digital video signal with B, so is at the output of the full adder 5 a digital signal A-B can be removed. This signal, in contrast to the undelayed digital video signal A now over a different range of quantization levels. During the range of quantization levels of the undelayed digital video signal A ranges from 0 to 256, now in the digital signal A-B becomes a range of +256 quantization levels recorded. By inverting the delayed digital Videosig> alsB and the simultaneous application of a logic level from H. Terminal 6, the full adder 5 works as a subtracter.

The digital signal A-B which can be taken off at the output of the full adder 5 is fed to an input of a second full adder 7.

This is at another input of the full adder 7 by one pixel period delayed and inverted digital Si-signal A-B, which in the following with (B-C) referred to as. The digital signal A-B is delayed with another D flip-flop 9, which is caused by the scanning pulse signal fa at terminal 3 is clocked. By applying a logic voltage level H to a terminal 9 of the carry input of the full adder 7 becomes a at the output of the full adder 7 digital correction signal of the form A-2 B + C received. This correction signal indicates a quantization range of +512 quantization levels. The full adder 7 thus acts like the full adder 5 as a subtracter.

The digital correction signal of the form A-2 B + C thus obtained becomes is supplied to an input of a further full adder 11 via a read-only memory 10. The read-only memory 10, which can consist of a PROM or ROM, operates as a Code converter.

The digital correction signal is based on a specific characteristic curve valued and inverted at the same time. The evaluation of the binary values is shown in FIG at the output of the read-only memory 10 as a function of the binary values at the input of the read-only memory 10 shown by way of example. The dash-dotted line indicates the function of a linear transmission behavior with a gain ratio of; : 1 again. The fully marked line, on the other hand, indicates the programmed transfer function in the read-only memory 10. Thereafter, small and large correction signal values fed to the full adder 11 only with maximum amplification factors <1, while medium or greater correction signal values in the amplification ratio of 1: 1 / to the full adder 11 arrive. As from the curve of the fully drawn line in 2 can be seen, very small correction signal values are not transmitted. This measure ensures that, for example, noise in the to be corrected Correction signal values returning the video signal are excluded from the aperture correction will.

A weighted correction signal obtained in this way is combined in the full adder 11 with the non-inverted delayed digital video signal B at the output of the D flip-flop 4 to form an aperture-corrected digital video signal of the form B - F (A - 2B + C) (terminal 12). In a downstream overflow logic 13, the signal at terminal 12 is checked to determine whether the value range of an n-bit word is exceeded. The most significant bit (MSB10) of the signal at the output of the read-only memory 10 and the bit with the most significant value (MSB11) of the signal at the output of the full adder 11 are indicative of this. The overflow logic complies with the following truth table: MSB1o MSB11 0 0 normal range of values OL positive overflow (limited a-sf i-1) LO negative overflow (limited to 0) LL normal range of values At the output of the overflow logic 13 (terminal 14), the aperture-corrected digital video signal can be removed.

The mode of operation of the block diagram in FIG. 1 is described below are explained in more detail with reference to the diagrams of FIG. 3.

In FIG. 3a, the dash-dotted line represents a jump in brightness from black to white in an analog video signal. The corresponding binary values of the jump in brightness after digitization shows the fully exhausted Line, where a dot period length of the sampled video signal ta = 1 / fa. The continuous jump in brightness is caused by the digitization process converted into a step-shaped jump in brightness. The decimal values of each Quantization levels and the corresponding binary values (8 bits) are to the right of the Diagrams of Fig.3 shown. In Fig.3a is the jump in brightness of the undelayed digital video signal A shown, while in Figure 3b by one pixel period (iça) delayed corresponding jump in brightness is shown. In Fig.3c the jump in brightness shown in FIG. 3b is shown inverted. Such a; -brightness jump would with a digital video signal A according to FIG. 3a at the inverted output of the D flip-flop 4 be removable. By adding the binary values of the brightness jump According to FIGS. 3a and 3c, at the output of the full adder 5, a curve according to of Fig.3d obtained. In Fig.3e, the signal shown in Fig.3d is by one further pixel period duration ra delayed and reproduced inverted. The signal 3e can be removed from the inverted output of the D flip-flop 8. By addition of the binary values in the signal curves of FIGS. 3d and 3e becomes that shown in FIG. 3f Binary value history received. This signal can be taken from the output of the full adder 7. The initially selected range of n-bits is exceeded by 2 bits. At the exit of the read-only memory 10 is after the previously described evaluation of the correction signal (Fig.3f) a signal according to Fig.3g can be removed.

In the present embodiment, this signal was with the Factor F = 1 / L evaluated, inverted and at the same time back to the value range of an n-bit value. By adding the course of the binary values according to FIG with the weighted correction signal according to FIG. 3g, a horizontally-aperture-corrected one is obtained Jump in brightness at terminal 12 of full adder 11.

A subsequent digital-to-analog conversion process would result in a analog video signal (dash-dotted line) can be obtained, in which Jumps in brightness compared to those in FIG. 3a delayed by two sampling pulse periods and are steepened.

As mentioned at the beginning, the circuit arrangement according to the invention remains not only limited to horizontal aperture correction of digital video signals. By changing the delay time from a single pixel period to a line period a digital video signal can also be corrected for vertical aperture. Instead of a single D-flip-flop would then be a series connection of several D-flip-flops step. The number of D flip-flops in the series connection became the number of Scanning period duration per line period correspond.

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Claims (7)

Method and circuit arrangement for the aperture correction of a digital Video signals patent claims 1. Method for aperture correlation of a digital video signal, in which a correction signal is the digital delayed by a certain amount Video signal is added, characterized in that the correction signal before an addition to the digital video signal delayed by a certain amount digitally evaluated by recoding according to a specific characteristic function will. 2. The method according to claim 1, characterized in that the recoding of the correction signal takes place in a read-only memory (10) which is programmed in this way is that small and medium values of the correction signal fed to the read-only memory are rated less than average values. 3. The method according to claim 1, characterized in that the by the addition receivedc video signal fever an overflow logic is performed, which limits the value range of the n-bit words of the digital video signal to 0 or 2n-1. 4. The method according to claim 1, characterized in that for derivation of the correction signal from the video signal to be corrected by one pixel or Line period delayed digital video signal is subtracted and in front difference signal obtained in this way by one pixel or Line period duration delayed difference signal is subtracted. 5. Circuit arrangement for performing the method according to claim 1 to 4, characterized by a first full adder (5), one input of which the digital video signal is fed, at the other input with a first delay stage (4) delayed and inverted. video signal is ur & d at the carry input of which there is a logic potential H, a second full adder (7), one input of which is removable from the output of the first full adder (5) Signal is fed, at the other input that with a second delay stage (8) delayed and inverted output signal of the first full adder (5) is located and at the carry input of which there is a logic potential H, a read-only memory (10), the input of which is connected to the output of the second Vclladder (7), a third full adder (11), one input of which is the one at the output of the read-only memory (10) detachable weighted correction signal is fed to the other input the video signal delayed with the first delay stage (4) is and is connected to it Carry input is a logic potential L, and an overflow signal for limitation the range of values of each n-bit word per scanned pixel in the digital Video signal whose input is connected to the output of the third full adder ('1) is and at the output of which the aperture-corrected digital video signal can be removed is. 6. Switching arrangement according to claim 5, characterized in that for a horizontal aperture correction the time delay of the first and second Delay stage (4 and 8 is a sampling period of the digital video signal. 7. Schaltungsancrdnung according to claim 5, characterized in that for a vertical aperture correction, the time delay of the first and second Delay stage (4 and 8) a line period of the digital video signal amounts to.