DE2724646A1 - Semiconductor memory unit with matrix array - has switching transistors, address buffers and pulse generators - Google Patents

Abstract

The semi-conductor memory unit has a matrix with rows and columns and a read amplifier in the middle of each column. The read amplifier has two cross-wise coupled driver transistors and a load transistor for each driver transistor. A circuit arrangement is provided so that the gate electrode of each load transistor is coupled with the adjacent side of the column conductor. In one embodiment, a matrix of 128 rows and columns is connected with 7-bit address buffers (12, 14) a pulse generator and an input/output control unit.

Description

Semiconductor memory device

The invention relates to a semiconductor memory device and especially on fast circuit arrangements for an N-channel MOS memory with Memory cells that work with a transistor.

In the production of digital arrangements, especially small computers, MOS random access memories (RAM) are widely used. The abilities and the cost advantages of such memory arrangements have continued to grow in recent years increased. The cost per memory bit increases with MOS random access memories in the same way as the number of bits or memory cells per unit increases. Increasingly large random access memories are standard building blocks in the industry become, for example, 256-bit memory, 512-bit memory, 1024-bit memory and finally 4096-bit memory. For example, a 4096 bit random access memory is in the U.S. Patent 3,940,747. Manufacturers are currently starting of semiconductor components with the production of random access memories with 16 384 bits, so called 16 K-RAM; see the magazine "Electronics" of February 19, 1976, pages 116 to 121 and of May 13, 1976, pages 81 to 86.

As the number of bits in a semiconductor chip increases, so does the Cell size, and inevitably the size of the storage capacitor is in each cell smaller.

Also the number of cells on a point line in the cell matrix increases so that the capacity of this line increases. These factors set the Decreases the size of the data signal present on a point line. A full digital one Level, i.e. the difference between the signal value ~ 1 "and the signal value" O " in one of these structural units, for example, be 10 or 12 volts. The voltage difference between a signal value "1" and a signal value "O" for the to a point line in the memory matrix from the selected cell coupled to a transistor However, data can only be one or two tenths of a volt. To read this Various circuits have been proposed for low level signals.

Examples of sense amplifiers are shown in U.S. Patent 3,940,747, supra articles mentioned in the journal "Electronics", U.S. Patent 3,838,404, the journal "Electronics" of September 13, 1973, Volume 46, No. 19, pages 116 to 121 and the IEEE Journal of Solid State Circuits, October 1972, page 336.

When applied to storage devices that have a high packing density, require high operating speed and low power dissipation, such as as required in the 16K random access memory are those proposed above Sense amplifier associated with disadvantages.

Some have a high power loss and excessively long charging times for the managerial staff. Others require a high instantaneous current and a critical one Clock control.

In one embodiment of the invention, a circuit is specified, in which many undesirable properties of previously known sense amplifiers are avoided will; In this circuit, the load transistors are in a bistable sense amplifier via tracking capacitors (bootstrap capacitors) and parallel transistors controlled. This circuit has its own clock signal source with an intermediate voltage value needed to control the gate electrodes of the parallel transistors; this own Clock signal source is no longer in a further embodiment of the invention needed.

The output data usually taken from one side of a column line, and data input takes place on the same side, even if the addressed cell is on the other Side lies. For units with a high packing density, as is the case with a 16 K RAM the capacitance of the column lines or the read lines becomes high, resulting in a delay due to the period of time the lines take for charging or discharging to the full logic level. It is therefore preferable to use the logical ones Read levels on the column lines on each side of the sense amplifier and with Using intermediate output buffers to generate output signals with a high level.

The operating speed of a store is generally its Understand reading time and its writing time.

The read time is the time interval for accessing data from memory is required, and the write time is the time interval that is needed to write data to memory. The speed with The ability of these operations to be performed is critical as the trend is in digital Arrangements in which these memories are used have passed in the last 10 years go that ever higher operating speeds have been required. In the In semiconductor industries, great efforts have therefore been made to memory to develop at higher working speeds.

The read time of a semiconductor chip is influenced by several factors. One factor was the time lag between the sense amplifiers stabilizing within the memory chip and the switching through of the output signal of the sense amplifier to the data output line of the chip. This time delay was introduced on purpose, this ensured that the sense amplifiers had stabilized before their output signal has been switched through. The capacitive load on the sense amplifiers is carefully balanced during a read, and that balance would disturbed and lead to Lesef selectors if the sense amplifiers are before their stabilization would be switched through.

This time delay was typically implemented in an RC read clock generator realized in which two transistors A and B and a capacitor for one working were used as an RC timing control element. The transistor A was with its source electrode to a voltage source Vdd and with its drain electrode to a circuit point N connected.

The transistor B was with its source electrode at the node N and with its drain electrode to ground connected. The condensation gate was also inserted between node N and ground.

Before a read operation, transistor A was turned on, and the capacitor was charged in this way. Was during a read the transistor B turned on, so that the capacitor was discharged. The discharge time was designed to last longer than that used to stabilize the sense amplifier. required length of time was; the sense amplifiers were then switched through, when the discharge was finished.

One difficulty with this RC read clock amplifier was that the RC time constant is always considerably greater than the stabilization time of the Sense amplifiers had to be made, and not made equal to this read time could. This was because the timing parameters of the RC element and the sense amplifiers due to the different structure of the two circuits could not possibly be matched exactly to one another. Sense amplifiers are fundamental a differential voltage sensing device and not a simple RC discharger.

This difference in circuit design also had the consequence that the timing parameters of the two circuits are different with respect to temperature changes behaved.

The result was that the read time of the memory chip was undesirable was long.

Typically, a semiconductor random access memory receives one Multi-bit address from an external circuit, this address being the selection of one or more specific cells within the random access memory for writing or reading data. The address will from other parts of the system separately from the random access memory. A requirement the circuit of the random access memory is that the timing and the voltage values (or the digital values) of the address signals to which the Memory must respond, must be compatible with the rest of the system.

The voltage values are often the input address of a memory low voltage values of bipolar circuits, for example voltage values of TTL circuits, and no high voltage values as in MOS circuits; the input address signals with a low voltage level, there are difficulties in setting up the address input buffer. This is the case because such signals are logic circuits with MOS components do not switch through completely; so these signals are difficult to read. That However, reading such signals must be performed accurately and quickly in order for the Storage system can be reliable and fast.

Address input buffers have been developed which are provided with address signals work at low voltages.

An example of an address buffer is in patent application P 26 47 892.2 shown; this buffer circuit does result in speed improvements and low power dissipation and noise levels, but a need remains after improving these factors with the increase in the packing density of memory circuits.

In semiconductor memory systems, basic clock voltages are applied to memory components created like random access memory, and the components then internally generate different ones additional clock signals and further control voltages depending on the basic clock. The random access memory must react quickly to the basic cycle, so that the speed or access time of the storage system is fast. at 4 K or 16 K bit random access memories currently in use, as they are in electronics of February 19, 1976, pages 116 to 121 and May 13, 1976, pages 81 to 86 the basic clock signal is a row address strobe signal (RAS signal). That Itç signal causes the line address to be entered in multiplexed form, and it also acts as the basic clock signal for the system. The speed at which the memory chip the leading edge (the transition from a positive value to ground) of the t signal can determine forms a limit of the speed or the access time of the Memory. The section of the RAS signal that is critical for the timing of the device is the leading edge or the side transitioning to negative values, and it controls usually an input transistor that acts as an inverter; the outcome of this Negators must charge to a full logic level quickly in order for a Number of other circuits to be triggered in the device. The capacity of the However, input transistor delays charging of this output node.

A semiconductor random access memory receives one of several bits existing address of external circuits, and this address causes the selection one or more specific cells in the random access memory for writing or reading data. The address is separated from other parts of the system generated by random access memory.

A requirement placed on the circuitry of the random access memory is that they are dependent on timing signal values and voltage values or digital signal values can work in the address signals that are compatible with the rest of the system. The digital signal values in System are often based on the operating voltages of bipolar components (TTL operating voltages ) and not determined by the operating voltages of MOS components.

The address entries in the random access memory should correspond to the external Only subject circuits to a minimum current load, and those to be determined The circuit applied to the address signals should have a minimum of noise or noise Generate changes in interference voltage. The address buffer circuit should only be used during a very narrow time window in the course of the operating cycle of the digital device respond to the address signals so that the address signals are used for adjustment of the next access cycle before the current cycle ends is.

Address buffer circuits that are appropriate in this regard work, are in the above-mentioned articles in the magazine "Electronics" described. Even so, there is a continuous improvement in these factors, in particular the speed required when the cycle time of computer arrangements is increasing makes higher demands.

With the aid of the invention, therefore, fast-working circuit arrangements for a MOS random access memory; in particular should: by means of an embodiment of the invention, a sense amplifier can be created, the one low power dissipation and a high working speed as well as a high sensitivity Furthermore, a semiconductor memory arrangement is intended to be created with the aid of the invention be that with higher speed and shorter access time or reading time is working. Furthermore, a. Intermediate output buffers are created to handle the transfer of data from a cell matrix to the output terminal of a memory array. According to One embodiment of the invention is intended to provide a memory with improved read time and providing a memory read clock generator; this reading clock generator should be constructed as a differential voltage reading circuit. In this embodiment According to the invention, the read clock generator should be designed so that it has an output signal generated within a few nanoseconds when the sense amplifiers stabilize to have. In this embodiment of the invention, the read clock generator is also intended designed in such a way that its timing parameters are dependent on the Change the temperature as well as the timing parameters of the sense amplifiers.

According to a further embodiment of the invention, a circuit for determining memory address signals and an address input buffer with relatively faster operation can be created, the address input buffer should be designed so that it accurately receives input signals with a low voltage value notices.

According to one embodiment of the invention, a MOS random access memory is also intended created with a fast input circuit for logic or timing signals and a circuit is to be created that has the capacity of its input isolated from its output node so that the output node can charge quickly; a clock signal input for a MOS / LSI component is also intended that can operate at high speed.

According to a further embodiment of the invention, an improved Circuit for determining address signals or other logic signals in a MOS random access memory or the like, and in particular one fast working circuit can be created in terms of response time control, voltage and load are compatible with the rest of the system in which the component can be used.

According to a first embodiment of the invention, in a MOS random access memory with a transistor containing cells uses a sense amplifier that crosses two Driver transistors coupled and connected as a bistable circuit in the middle each column line in the memory array. Load transistors for the driver transistor pairs are only used during part of the operating cycle with the aid of a control arrangement switched on by the clock. The driver transistors are in two different ways connected to ground, which are formed by two transistors connected to different Points in time are switched on by the clock. During an initial reading period the current through the driver transistors is kept at a low value, and it can then take on a higher value during a later period of time, so that a full logic level output is produced. The load transistors are after the initial reading period, i.e. during the later time period switched on by the clock with the help of bootstrap capacitors. The gate electrodes the load transistors are connected directly to the point lines via shunt transistors connected, their gate electrodes each directly to the point line on the each opposite side of the sense amplifier are connected.

The bypass transistors cause the load transistor to be blocked on the zero going side of the sense amplifier so they do that way Save energy and enable faster operation.

According to a second embodiment of the invention, in a MOS random access memory with cells with one transistor a sense amplifier with two cross-coupled and driver transistors connected as a bistable circuit in the middle of each column line used in the memory matrix. Load transistors for the driver transistor pairs are switched on by the clock only during part of the operating cycle; before that time the cells have been addressed. The driver transistors are about two different ones Paths connected to ground formed by two transistors connected to different Points in time are switched on by the clock. During an initial reading period the current through the driver transistors is kept at a low value, and it can then increase to a higher value during a later period of time, so that a full logic level output is generated. The load transistors are from the clock after the initial reading period, i.e. during the later time period switched on with the help of bootstrap capacitors. The gate electrodes of the load transistors are connected to the control lines with the help of shunt transistors, a selected voltage value is applied to their gate electrodes; these transistors effect the blocking of the load transistor on the zero-going side of the sense amplifier.

According to a third embodiment of the invention, in an MOS random access memory with cells with a transistor a bistable sense amplifier in the middle of each Column line used. An intermediate output buffer has inputs that can be accessed via the Column decoders are connected to each side of the sense amplifiers. The intermediate output buffer contains two cross-linked and as a bistable circuit connected driver transistors as in the second embodiment of the invention. Pre-charge / load transistors for read circuit points on the drain electrodes of the driver transistor pairs are only used during part of the operating cycle with the aid of a control arrangement switched on. The driver transistors can easily with the help of a component be connected to ground, or they can be connected to ground in two different ways which are formed by two transistors operating at different times be switched on according to the patent application P 27 19 726.8. These read breakpoints are coupled to the column lines at the beginning of an initial read period; the signal on one side of the column line goes low while the signal is on the other side stays high. During this initial reading period, the Current through the driver transistors is kept low and he can during a later time period become higher, so that an output signal with full logic Level is generated. The precharge load transistors are used during the initial Read period, i.e. during the later time period, switched on by bootstrap capacitors. The gate electrodes of the precharge load transistors are connected to the source electrodes of the Driver transistors connected via shunt transistors, their gate electrodes each directly to the reading switching point on the other side of the bistable Circuit are connected. The shunt transistors cause the blocking of the precharge / load transistor on the zero-going side of the bistable circuit, so that energy is saved and faster operation is possible.

According to a fourth embodiment of the invention is a bistable Amplifier connected to a differential voltage sensing transistor. The bistable The circuit structure of the amplifier corresponds to the memory read amplifier of second and third embodiments of the invention. Thus the two circuits same timing properties. The bistable amplifier is powered by a clock signal activated at the same time that the memory read amplifier is activated will. Both circuits therefore stabilize at almost the same point in time. The differential voltage sensing transistor determines when the bistable circuit is has stabilized, and it generates a to indicate that stabilization has occurred Output signal, In a fifth embodiment of the invention, two are crosswise uses coupled transistors with set and reset nodes that are initially are charged to a predetermined value. The set and reset circuit points cause a coupling to two load transistors; each load transistor has one Control node that is initially charged to a different value.

An input address signal is generated by further charging (or discharging) the precharge voltage at the set and reset circuit points with two different Speeds determined. These speeds depress the state of the Input address signal off.

A current discharge circuit represents the different charging (or Unloading) speeds fixed. In response, the drain circuit conducts selectively precharge from the set or reset node and from the control node of the corresponding load transistor. The state of the Input address signal is thereby applied to the load transistor control nodes held.

According to a sixth embodiment of the invention, in a clock input circuit made use of an input transistor for a MOS / LSI circuit device, on its gate electrode the leading edge of the transition from + V to ground Clock input signal is present. The input transistor is in series with a second one Transistor whose drain is connected to the output node.

An intermediate point at the drain of the input transistor is connected to the gate electrode of a control transistor, its drain electrode is connected to the gate electrode of the second transistor. This circuit arrangement causes the second transistor to turn off when the interposing point is a Sufficient voltage has been reached to switch on the control transistor. Wern the second Transistor is blocked, the output node charges faster because it is isolated from the input capacitance.

The output node is across a bootstrap load transistor connected to the supply voltage.

The gate electrode of the second transistor is on one before the leading edge of the input signal.

In a seventh embodiment of the invention, an address buffer for a semiconductor memory of two cross-coupled MOS driver transis formed gates that act as a difference detector; one of these transistors is larger than the other, so that an imbalance arises. The address input signal is applied to one side of the differential pair by a transistor device. the Switching points at the outputs of the differential pair are set before the address is entered preloaded to a high value; shortly after entering the address, these output nodes equal charges of two capacitors are applied, causing a discharge of the node is prevented, which should remain at the value "1". The state of the output circuit pins of the cross-coupled transistor pair is detected and address signals become generated and retained immediately after the same charges are applied; then the address input signals can change without the internal Address signals are influenced. The cross-coupled driver transistors can have two transistors leading to ground, which are connected to different Times are switched on.

The features of the invention will now be given by way of example with reference to the drawing explained. They show: FIG. 1 a block diagram of a semiconductor memory arrangement, in which made use of the various embodiments of the invention FIG. 2 is a perspective view of the storage arrangement of FIG in a housing, Figure 3 is an electrical circuit diagram of a matrix of memory cells for the arrangement of Figure 1 with sense amplifiers according to the first embodiment of the invention, Fig.4a to 4k timing diagrams of voltages applied to different Points of the arrangement according to Figures 1 and 3 occur.

Fig. 5 is a detailed diagram of the voltage on the control lines of the The circuit of Fig. 3 as a function of time, Fig. 6 is an electrical circuit diagram a matrix of memory cells for the arrangement of r - '#. i with sense amplifier according to the second embodiment of the invention, Figure 7 is an electrical circuit diagram a # matrix of memory cells for the arrangement of FIG. 1 with intermediate output buffers according to the third embodiment of the invention, FIGS. 8a to 8i are timing diagrams of Stresses at different points of the arrangement according to this embodiment of the invention occur, Fig.9 shows a detailed diagram of the voltage at certain circuit points of the intermediate output buffer of Fig. 7 as a function of time, Fig. 10 and Fig. 11 FIG. 8 is an electrical circuit diagram of an intermediate output buffer and timing diagrams of FIG Tensions in this buffer according to a variant of the third embodiment, Fig.12 a block diagram of the connections to the differential read clock amplifier according to a fourth embodiment as applied by the MOS random access memory according to FIG 13 is a circuit diagram of a special embodiment of the differential read clock amplifier of Fig. 12, 14 is a timing diagram to illustrate the on different circuit points in the circuit of Fig. 13 occurring voltages, FIG. 15 is a circuit diagram of the fifth embodiment of the invention, and Log. 16 is a timing diagram of voltages at selected circuit points of the circuit of Fig. 15, Fig. 17 a circuit diagram of a variant of the fifth embodiment of the invention, Fig.18 a timing diagram of voltages at selected node points in the circuit from Fig.17, Fig.19 an electrical circuit diagram of a circuit according to the sixth Embodiment of the invention, FIG. 20 shows a time diagram of voltages in the circuit from Fig.19, Fig.21 an electrical circuit diagram of the circuit of the seventh embodiment of the invention, FIGS. 22a to 22e, time diagrams of voltages at different points the circuit of Fig.21 and Fig.23a to 23e time diagrams of voltages at different Points of the memory arrangement according to Fig. 1, in which the circuit of Fig. 21 is applied will.

Description of the exemplary embodiments In Fig. 1 is a MOS memory device illustrated in which the various embodiments of the invention are applied can be. The memory arrangement can be designed in different sizes but the invention is for use with a very high memory Packing density with 16 384 memory cells on a silicon chip with one surface of 0.32 cm2 (1/20 inch) determined by means of the N-channel silicon gate MOS process is made with self-adjustment. The memory arrangement consists of a matrix 10 out of 16,384 memory cells, generally divided into 128 rows and 128 columns are; each cell is a so-called single transistor cell, as described in the magazine Electronics, May 13, 1976, pages 81-86. A row decoder 11 selects one of the 128 row lines by a row or X address which is contained in a 7-bit line address buffer 12; a column decoder 13 selects one of 128 column lines by a column or Y address is formed in a 7-bit column address buffer 14. These addresses are via seven address lines 15 are applied to the semiconductor chip in the time division method. A row address scan input signal (RAS in Fig. 4g) at input 16 is at Value OV free the line address buffer 12 so that it accepts a line address, contains the address bits A0 to A6. In the same way, there are: a column address scan input (= in Fig.4h) at input 17 at the value OV free the column address buffer so that it takes a column address (bits A7 through A13) from lines 15.

The row and column addresses must be used during the period shown in Fig. 4f specified Periods of time. To uniquely define a bit out of 16,384 cells (214 = 16,384) fourteen address bits are required. An input / output control circuit 18 is connected to the matrix 10 via the column decoder 13; she works so that data is applied to the column lines from a data input pen 20, or that data is recorded on the column lines and to a data output pin 21 under the control through a read / write input 22 (RW) and under the control can be applied by various internally generated clock and logic voltages. the The assembly requires several different supply voltages at pins 23; these include supply voltages Vbb, Vcc and Vdd and ground Vss. Some circuits are of course also designed so that they can be operated with one or two supply voltages work instead of the three supply voltages mentioned.

Typical voltage values are: Vdd = 12V, Vbb = -5V and Vcc = + 5V. Like can be seen in Figure 2, the unit of Figure 1 has the shape of a silicon chip 24, which is in a housing 25 with sixteen connection pins 26 corresponding to the above mentioned sixteen input and output lines is housed. Thin gold wires connect contact areas on the silicon chip 24 with internal connections of the pins 26. A cover, not shown, seals the structural unit. The housing 25 is 18 mm (3/4 inch) long and 8 mm (0.30 inch) wide making a large number of these housings can be housed on a standard size printed circuit board. For example, a small computer can run a whole computer on a small circuit board Contains 32K or 64K word memories (sixteen bits per word).

The conventionally constructed decoder 11 effects selection of one of the 64 row lines 29-1 on the left or one of the 64 row lines 29-2 on the right. A row wire is a metal wire that almost extends The gate electrodes smn 128 MOS transistors extend over the entire width of the chip drives in the 128 memory cells assigned to this row. The seven address bits A0 to A6 in the row decoder 11 select one row line 29 from 128 row lines off so that the signal on this line goes high while the signals keep the remaining 127 lines low.

The line address (which is denoted by X in Fig. 4b and Fig. 5) is on the selected line 29 for the duration of the = signal, as in FIG Fig.4g can be seen. The address bit A6 causes the selection of the left or the right side, which means that it is the activation of lines 29-1 or the Lines 29-2 allows. The six address bits A0 to A7 then select one of the 64 lines in the selected half. The address bit A6 also determines the Activation of dummy cells in the unselected side via dummy cell address lines 27 for the duration of the RAS signal, which is splendid.

Exact description of the first embodiment (Fig. 3 and 5) of the invention includes the memory array of Figure 1 in the middle of each column line Sense Amplifiers 30. The sense amplifiers serve the purpose of being on the selected column line detect generated low signal level when a cell is addressed, and convert this low signal value into a full logic level.

In Figure 3, a sense amplifier 30 according to this embodiment is the Invention represented in part of the matrix.

The sense amplifier 30 basically contains a bistable flip-flop circuit with two cross-coupled driver transistors 31 and 32 together with associated Load transistors 33 and 34. Two nodes 35 and 36 are connected to the respective Halves 37 and 38 of the column line connected. These circuit points 35 and 36 are connected to the gate electrodes of the opposite transistors 31 and 32, so that the cross-coupled circuit is created. With one half of a column line 64 cells 40 are connected to form line 37; the same goes for the line 38. Each cell consists of a transistor 41 and a capacitor 42; the The gate electrode of each transistor 41 is connected to a row line 29-1 or 29-2 controlled (the row line is also referred to as word line and X line), and each row line is connected to 128 gate electrodes of similar transistors 41. In the matrix 10 of this embodiment, the sense amplifiers are on each side 30 a total of 64 row lines are available, and of course there are also 128 sense amplifiers present, so that only a very small part of the matrix 10 can be seen in FIG is. Each sense amplifier has a dummy cell 44 on each side, which is connected to the respective column lines 37 and 38.

The dummy cells are constructed in the same way as the memory cells 40; she each contain a transistor 45 and a capacitor 46 cause transistor 45 in the dummy cell row on the side to be turned on of the sense amplifier, which is the corresponding determination by the bit A6 of the row address selected cell 40 is opposite what at the same time as the The selected memory cell 40 is addressed. Each column line 37 or 38 is connected to a reference voltage line 48 via a transistor 49, the gate electrodes of these transistors being driven by the clock signal 7; this causes lines 37 and 38 to be equally charged from a reference voltage value, that as a voltage value Vdd or as a slightly below this voltage value Vdd is selected; for example, if Vdd has the value + 12V and the value of Vt is around 1V, then the voltage Vref can be around 10 or 11 volts be. However, in order to simplify the circuit layout, the voltage Vdd to be used. The load transistors 33 and 34 are connected to the voltage Vdd, and they are controlled by the circuitry to be described. The flip-flop circuit that the transistors 31 and 32 begins to work before the transistors 33 and 34 are made conductive when one is connected to the drain electrodes of the transistors Circuit point 50 is connected to ground.

The circuit point 50 is connected to ground via two separate paths, which in this case contain two transistors 51 and 52, which are driven by clock signals # 1 and # 2 are controlled. The transistors 51 and 52 have different dimensions, so that the amount of current drawn by them from node 50 to ground Vss is different. The voltage at the circuit point 50 thus changes as a function of which of the transistors 51 and 52 is on. The transistor 51 is the smaller transistor, and transistor 52 is measured about twice as large on the component ratio, i.e. the ratio from width to length of the canal. All 128 sense amplifiers 30 in matrix 10 use the same pair of transistors 51, 52; a line 53 connects the circuit points 50 of all sense amplifiers to one another.

When a clock signal # 1 (Fig. 4c) becomes positive, it is a read operation triggered, and the flip-flop circuit goes into a stable state in which either the transistor 31 conducts and the transistor 32 is blocked, or vice versa. The switching direction depends on the voltage difference on lines 37 and 38 from, which in turn depends on whether in the selected cell 40 the signal value 1 or the signal value "O" was saved. Since on one of the lines 37 or 38 a slightly higher voltage than is applied to the other line also at the gate electrode of one of the transistors 31 or 32 a slightly higher one Voltage than the other transistor, so that a transistor when the clock signal passes # 1 conducts slightly more current than the other transistor to a positive value.

For a smaller component ratio of the transistor 51, the Voltage at node 50 is higher and it can be shown that the sensitivity of sense amplifier 30 during the initial period 58 with the voltage at the node 50 for a given threshold voltage and digit line voltage are directly related stands. The circuit of Figure 3 described so far results in a high operating speed, since the precharge voltage on the column lines 37 or 38 (which maintain the value "1 n ought to) tends to stay higher during this initial reading period, i.e.

during the period in which the # clock signal # 1 is turned on is, but before clock signal # 2 transitions high. It means that the sense amplifier of FIG. 3 has a minimum charging time for the column lines 37 or 38 for refreshing the signal value "1 n results, since the node of the read amplifier, which should maintain the value "19, during the initial Read does not discharge to a low voltage.

FIG. 5 shows the time-dependent course of the voltage on the column lines 37 and 38 are shown enlarged at the time when the clock signal # 1 is switched on.

Before addressing one of the row lines 11-1 or 11-2 through an address signal and before the transition of the clock signal ~ 1 to a high value During the time period 53, the voltage on the column lines 37 and 38 is on the voltage value Vref or about Vdd, as balanced by the charging over the line 48 is set. At time 54, the signal is on one of the lines 29-1 or 29-2 high and the voltages on leads 37 and 38 separate slightly by, for example, 50 to 100 millivolts due to the fact that one of the storage capacitors 42 is connected to one side while a dummy cell capacitor 46 (which is smaller than the capacitor 42) is connected to the other side. At time 55, clock signal ~ f goes high and one of lines 37 or 38 begins to discharge to the value "O" during the time period 58 while the others only a little, not over about 0.3 volts, like lines 56 and 57 show. During time period 58 and before time 59 when the clock signal # 2 is turned on, transistor 31 or transistor 32 on the other conducts Side of the selected cell stronger than the transistor opposite the dummy cell, if the signal value ")" was saved. If the signal value "O" was stored, the reverse is true.

Corresponding to the main feature of this embodiment of the invention the sense amplifier 30 of Figure 3 contains a special arrangement for controlling the Conductance of the load transistors 33 and 34. The nodes 61 and 62 at the Gate electrodes of load transistors 33 and 34 are connected to the source of the clock signal # 2 via switched capacitors 63 and 64 and also to the column lines 37 and 38 connected through transistors 65 and 66. In contrast to the circuit according to the aforementioned patent application, the gate electrodes are the transistors 65 and 66 via lines 67 and 68 to opposite column lines, respectively 37 and 38 connected. In the circuit according to this patent application was its own Clock signal required between Vdd and an intermediate voltage below Vref changed from about 8 volts; this is not necessary with the circuit described here. The clock signal # 2 indicated in FIG. 4d and also in FIG. 5 switches the transistor 52 a.

The capacitors 63 and 64 act as tracking or bootstrap capacitors, and they generate a high drive voltage to the gate electrodes of the load transistors 33 and 34. This enables the column line to which the Value "1n is to be renewed, as line 56 of FIG. 5 shows; this accelerates of course, the restoration of the tension of the value nln in the selected memory cell 40. The transistors 65 and 66 ensure the discharge the control voltage at one of the nodes 61 or 62 on the gate electrode of the load transistor on the zero-going side of the sense amplifier. This reduces the power consumption of the sense amplifier, and the operating speed is improved.

During the duration of the clock signal 7, which is shown in FIGS lines 37 and 38 become nodes 35 and 36) at a level 70 precharged while the address signal X and the clock signals ~ 1 and p2 have the value Have "O"; the nodes 61 and 62 are connected to the transistors 65 and 66 charged to level 72 during this time period. The level 72 is different from level 70 by the voltage drop across transistors 65 or 66. The switching points 61 and 62 are switched between these nodes during the clock signal X2i inserted transistor 73 balanced; the clock signal gl is applied to the gate electrode this transistor. If the clock signal ~ assumes the value "0" at time 71, then the column lines 37 and 38 are disconnected from the voltage Vref, and at the same time, the nodes 61 and 62 are isolated from each other, since the Transistor 73 is blocked. The transistors 65 and 66, those of opposite Column lines are driven, now form discharge paths, so that (a) the charge at node 61 or 62 and at the bootstrap capacitor 63 or 64 connected to the side of the sense amplifier going to "1" is connected during reading is not discharged and (b) that the charge at the other circuit point and at the bootstrap capacitor, the is connected to the side going to "O", is discharged, when the voltage on the column line decreases during reading. Because the voltage difference between the column lines 37 and 38 by charge sharing of the dummy cell capacitor 46 and the memory cell capacitor 42 arises and since the signal at the selected X line 29-1 or 29-2 and dummy cell select line 27 goes high the same procedure as above in connection with the time period 58 of Fig. 5 was mentioned. Since the clock signal # 1 assumes a high value at time 55, the amplification of the voltage difference begins. The initial level 72 of the voltage at the node of the nodes 61 and 61, which changes to the value "1" 62 is maintained until time 59 of FIG. 5 while the others begin can drop to the value ~ 0 ", as line 75 shows, because the voltage at node 35 and 36 during time interval 58 changes, like that Let lines 56 and 57 be seen. As long as the separation is less than Vt, you can do not turn on transistors 65 and 66, but one is turned on when the separation at time 77 reaches the value Vt. At time 59, the clock signal # 2 then high, causing the voltage (line 72) on the gates of the Follow-up load transistors 33 and 34 via the capacitors 63 and 64, so that also the transistor 52 is turned on, while the discharge of the value "O" passing side is accelerated, as the line 57 in Figure 5 shows. if at time 77, the voltage on the column line changes to the value "0" Page by the value of a threshold voltage Vt below the instantaneous value on the Value ~ 1 "passing page falls off, the reading process is finished, and one of the transistors 65 or 66 is turned on and the voltage starts at the bootstrap capacitor 63 or 64 this side to discharge, so that way the corresponding load transistor 33 or 34 is blocked. At this point you can the voltage values at nodes 61 and 62 separate the lines 75 and 75 in Fig. 5. For example, if it is assumed that the node 35 represents the side going over to the value tioi (which means that a selected Cell on column line 37 has the value "O" or a selected cell on the column line 38 stores the value nln) if signal X is high during time interval 54 is, then the voltage at node 35 assumes a value that is slightly is less than the voltage value at node 36, which means that the node 36 corresponds to line 56 of FIG. 5, while node 35 corresponds to line 57 is equivalent to.

Starting at time 55 when the clock signal changes to ~ 1 the voltage difference between the nodes 35 and 35 becomes a high value 36 amplified during the initial portion of time period 58, but the voltage is at the circuit point 35 up to the point in time 77 not yet by a threshold voltage Vt dropped below the voltage at node 36.

If clock signal # 2 goes high at time 59, then the gain of the voltage difference increases between 56 and 57, and the node 36 begins to discharge rapidly towards the voltage value Vdd via transistor 34, while the node 35 via the transistors 31, 51 and 52 moves more slowly discharging against Vss. At time 77, the voltage at node 35 is one Threshold voltage Vt below the voltage at node 36 has dropped, and transistor 65 turns on while node 61 is fast against Vss, as indicated by line 75. This arrangement increases the sensitivity of the circuit is not reduced, since the voltages at the circuit points 61 and 62 held at level 72 until reading upon disconnection occurs of the voltages on the column lines has occurred by a threshold voltage Vt. It should be noted that there could be an extremely short period of static operation, i.e.

when the load transistor 33 is on the side transitioning to the value ~ 0 " and the ground lead transistors 51, 52 are simultaneously conductive when the point in time 77 would occur after time 59. This time period between the point in time 59 and the point in time 57 would be insignificant.

When selecting the timing of the transistors 52 and on The clock signals applied to the bootstrap capacitors 63 and 64 exist at a speed # / power impairment. When the clock signal # 2 when applied to the bootstrap capacitors 63 and 64 is slightly delayed compared to being applied to transistor 52, so that the column line voltage 57 transitioning to the value "O" by more than one If the threshold voltage Vt is below the voltage value 56, then the load transistor for this column line never switched on, and only the discharge of the stored ones Energy of the column line capacitance results in an energy consumption. The delay however, the application of clock signal # 2 to capacitors 63 and 64 may result in a Cause increase in the access time of the memory arrangement. The instant Applying the clock signal p2 results in the fastest access time, however could the energy consumption can be increased by a negligible amount because the load transistor of the side taking the value AO "are turned on for a short period of time could as explained above.

The use of a small component ratio for the transistor As a result, the gain for the "O" side becomes insufficient is.

For this reason, the transistor 52 is provided so that another Gain is generated so that the column line 37 or 38, whose signal is a should assume a low value, receives a good level. Since in the course of reading or write interfering signals appear from other circuits must be good digital signal values are generated on lines 37 and 38, so that a reliable Operation is guaranteed. A transmission link is used for the selected Y line 38 80 made conductive so that this line is connected to a collecting line 81, to an output buffer or an input buffer in the input / output control unit 18 leads. These have additional capacitance and noise. For these reasons, the high digital signal levels are required, the larger ones Transistor 52 results.

Description of the second implementation game (Fig. 6) Si of the second Embodiment of the invention includes the sense amplifier 30 of Figure 6 according to a The main feature is a special arrangement for controlling the conductance of the load transistors 33 and 34 when the clock signal p2 assumes a high value. The circuit of Fig. 6 is similar to the circuit of FIG. 3 with the exception of the one to be described now Differences Connection points 61 and 62 on the gate electrodes of the load transistors 33 and 34 are connected to the source of clock signal # 2 via switched capacitors 63 and 64 tied together; they are also connected via transistors 65 and 66, which are activated by clock signal # 3 (see 4k) are connected to the column lines 37 and 38. The clock signal # 3 does not switch from the voltage value Vdd to the ground value Vss, but it changes between the voltage value (Vdd-Vt) and an intermediate voltage, less than Vref of about 8 volts (at a voltage Vdd of +12 volts). The in Fig. 4d and in Clock signal # 2 shown in FIG. 7 also turns on transistor 52. The capacitors 63 and 64 act as bootstrap capacitors, and they generate a high drive voltage at the gate electrodes of the load transistors 33 and 34.

This allows a quick charge of the column line, which again is to be brought to the value 1 ", as indicated by line 56 in FIG. 5; this accelerates course the restoration of the voltage with the signal value 1 in the selected Memory cell 40. Transistors 65 and 66 provide the intermediate value 67 of the clock signal # 3 for the discharge of the drive voltage at one of the switching points 61 or 62 at the gate electrode of the load transistor on the one taking the value "O" Side of the sense amplifier. This has the effect of greatly reducing energy consumption of the sense amplifier.

During the duration of the clock signal 7 (see Figure 4a), the lines 37 and 38 are precharged while clock signals 81 and # 2 are ~ 0 "while clock signal # 3 is high; at this point in time, the connection points 61 and 62 to about (Vdd-2Vt) or the maximum value 68 of the voltage of the reduced by Vt Clock signal # 3 precharged, and the nodes 35 and 36 become charged to the voltage Vref. If the clock signal 7 assumes the value "O", then the column lines 37 and 38 are disconnected from the voltage Vref, and at the same time the clock signal # 3 transitions to the intermediate voltage value 67. This intermediate voltage value 67 is chosen so that (a) the charge on the bootstrap capacitor 63 or 64, which is on the side of the sense amplifier assuming the value "1" is connected, while reading is not discharged, and that (b) the charge on the other bootstrap capacitor, connected to the side accepting the value "On" is discharged when the voltage on the column line drops during reading. If there is a voltage difference between the column lines 37 and 38 by charge sharing of the dummy cell capacitor 46 and the memory cell capacitor 42 has set when the signal at the selected X line 29-1 or 29-2 goes high and the signal on the dummy cell select line 27 also becomes high, then the procedure is the same as that described above in connection was explained with the time period 58 of FIG. If the clock signal p1 at the time 55 assumes a high value, the amplification of the voltage difference begins. Later clock signal # 2 is then high at time 59, so that the voltage on the gate electrodes the load transistors 33 and 34 is tracked, and the transistor 52 also switches and accelerates the discharge of the side accepting the value "On", such as the Line 57 in Figure 5 indicates. When the column line voltage on the on the value "O" by the value of a threshold voltage Vt below the level 67 of the clock signal # 3 decreases, then the transistor 65 or the transistor 66 is turned on, so that it begins to adjust the voltage on bootstrap capacitor 63 or 64 of this page to discharge and thus to block the load transistor 33 or 34.

For the embodiment of Fig. 6 it is assumed, for example, that node 35 is the side transitioning to the value "O" (where a selected cell on column line 37 stores the value "O" when a selected one Cell on column line 38 stores the value "1") when the address signal X goes high, then the voltage at node 35 will be slightly less than the voltage at node 36; in Eg.5 the line 56 corresponds to the switching point 36 and line 57 to node 35. If clock signal # 1 at time 55 becomes high, the difference in the voltages at nodes 35 and 36 amplified during time period 58. When the voltage at node 35 by the value of a threshold voltage Vt below the voltage level 67 at the gate electrode of the transistor 65 drops, then the discharge of the voltage at the node begins 61.

If the clock signal 2 goes high at time 59, then the gain is the voltage difference between 56 and 57 increases, and node 36 begins, to discharge quickly to the voltage value Vdd. When the voltage value at the node 35 sufficiently below voltage level 67 of clock signal # 3 before power-up of the clock signal # 2 has fallen, then the node 61 is never tracked, and transistor 33 does not turn on.

If the voltage at node 35 when the clock signal transitions ~ 2 has not dropped far enough to a high value, then the voltage tracked at node 61 by clock signal p2 until the voltage at node 35 far enough to discharge the circuit point 61 sinks. this happens in a very short period of static operation, which means that the Load transistor 33 and the ground terminal transistors 51, 52 conduct simultaneously.

When selecting the timing of the clock signals # 1 and # 2 exists a reduction in speed / energy.

When the clock signal # 2 when applied to the bootstrap capacitors 63 and 64 is slightly delayed from being applied to transistor 52, so that the column line voltage taking the value "O" is sufficiently wider than by a threshold voltage value Vt below the voltage level 67 of the clock signal # 3 is, then the load transistor of this column line is never switched through, and only discharging the stored energy of the column line capacitance leads to an energy consumption.

The delayed application of the clock signal # 2 to the capacitors 63 and 64, however, may result in an increase in the access time of the device. The delay-free application of the clock signal # 2 results in the fastest access 5 times, however, the power consumption is slightly increased because the load transistor is on the value "O" is turned on for a short period of time.

As mentioned above, clock signal # 3 of Figure 4k is a signal with two values, namely a high value 68 and a low value 67 which is below the voltage Vdd, but is far above the ground value Vss. The high level 68 causes an acceleration of the equalization of the voltages at the circuit points 61 and 62. At the expense of slowing the equalization, clock signal # 3 may pass through a constant voltage value with the level 67 can be replaced.

Description of the third exemplary embodiment (FIGS. 7 to 11) The third Embodiment is a buffer circuit in which the principles of the foregoing Embodiments are applied. The circuit of Figure 7 is attached to the circuit points 35 and 36 of FIG. 3 are connected via lines 91 and 92.

7 shows an intermediate output buffer 19 according to the third embodiment the invention. This output buffer contains two driver transistors 81 and 82, which are connected in series with two precharge and load transistors 83 and 84. Sampling nodes 85 and 86 between the drive and precharge / load transistors are on the column line halves 37 and 38 of Figure 3 for the selected column via input transistors 87 and 88, Y select transistors 89 and 9P and lines 91 and 92 connected. The input transistors 87 and 88 are connected to ground via transistors 93 and 94, which are switched on by clock signal # 1 will. The gate electrodes of the precharge load transistors 83 and 84 are at node points 95 and 96 connected through transistors 97 and 98 from the source of the voltage + Vdd are charged and balanced by transistor 99; all of these transistors are switched on with the clock signal 7. The nodes 95 and 96 are during the operation of the circuit with the help of two switched capacitors 103 and 104 raised to a higher value, these capacitors being the capacitors 63 and 64 of the sense amplifier 30 correspond. The lower part of these capacitors is applied to clock signal 02Y. Nodes 95 and 96 are with the help. of shunt transistors 105 and 106 (according to the transistors 65 and 66 in the sense amplifier) to a node 100 in a ground supply arrangement created. The node 100 connects the source electrodes of the driver transistors 81 and 82 via two transistors 101 and 102 with ground, which are different sizes and act in the same way as those discussed above in connection with the sense amplifier Transistors 51 and 52.

Thus, nodes 95 and 96 are across transistors 105 and 106 grounded using node 100; in the same Way, the driver transistors are grounded. A transistor 107 connects the gate electrodes of the transistors 81 and 82 and thus the switching points 85 and 86 when the clock signal 7 occurs.

In the operation of the intermediate output buffer 19 of Fig. 7, the initial state becomes established when the signal EA-§ and the clock signal are high; thereby become transistors 97, 98, 99 and 107 are turned on, and nodes 95 and 96 are charged to voltage (Vdd-Vt) and balanced. The precharge / load transistors 83 and 84 are turned on by the precharge on the gate electrodes, so that nodes 85 and 86 are charged to the voltage (Vdd-2Vt) and be balanced by transistor 107. In Figure 9, line 115 gives the voltage at nodes 95 and 96, while line 116 applies the voltage to the Circuit points 85 and 86 indicates. At time 71, when the clock signal 7 low isolates nodes 85, 86, 95, and 96 as all Precharge and equalization transistors are blocked. The circuit point 100 is of mass separated because the transistors 101 and 102 are blocked so that transistors 105 and 106 do not discharge nodes 95 and 96, although their gate electrodes of nodes 85 and 86 are at a high Worth being held.

When the clock signal 01Y begins at time 117 of FIG Assuming a high value, the creation of the switching point 100 begins over the small one Transistor 101 to ground, and transistors 93 and 94 are turned on, so that the column data applied to the input transistors 87 and 88 take effect. For the addressed column line, transistors 87 and 90 are of signal Y. has been turned on from the column decoder 13 so that the voltages 56 and 57 on lines 37 and 38 to the gate electrodes of transistors 87 and 88 be created. This can take place before time 77 of FIG. One of the tensions 56 and 57 is higher than the other, so that one of the switching points 85 or 86 tends to go through transistors 87 and 93 or 88 and 94 faster unload. In FIG. 9, the voltages at circuit points 85 and 86 are through lines 118 and 119 indicated; the voltages at nodes 95 and 96 and indicated by lines 120 and 121. At time 122, the tensions have at nodes 95, 96, 85, 86 and 100 such values that one of the transistors 105 or 106 switches on and the circuit point 95 or 96 on which the value "0" accepting side discharges. Starting at time 122 and before time 123, with clock signal 02Y going high, lines 120 and 121 recede and lines 118 and 119 are much faster from each other as the node is 85 or 86 on the ~ 1 ~ side by the voltage Vdd across the transistor 83 or 84 charges and since the node is on the ~ 0 "side via the driver transistor 81 or 82 discharges.

At time 123 of FIG. 9, clock signal 02Y goes high, and high Transistor 102 begins to conduct, so that transistor 81 or the transistor 82 on the 0 "side rapidly discharges to ground Vss, as can be seen by line 124 leaves. Also with regard to the ~ 0 "side, the transistor 105 or the transistor discharges 106 rapidly against ground Vss as shown by line 125; the gate electrode of the transistor 105 or transistor 106 on the ~ 0 "side is due to the cross-coupling held at a high value with the opposite node 85 or 86, while the voltage at the gate electrode of the transistor 105 or the transistor 106 on the "1" side within a range of a threshold voltage Vt with respect to the voltage at node 100 is maintained as it is with the node 85 or 86 is connected and there is transistor 81 or transistor 82 on the ~ 0 "side is highly conductive at this point. The clock signal # 2Y also provides tracking the level of the "1" node 95 or 96 due to the coupling across the capacitors 103 and 104. A charge is also coupled to the "0" side, but this is Charge is diverted to ground via transistor 105 or transistor 106, the is now highly conductive via transistor 102.

The output of the buffer circuit 19 is in the embodiment 4 taken from the circuit points 95 and 96. Lines 110 and 111 connect these nodes to driver transistors switched on by the clock signal 02Y 108 and with earth connection transistors 109, thus on lines 112 and 113 output data are generated in direct or negated form. The output pin 21 can be used to obtain a three-state output from two transistors 114 and 115 can be controlled.

The input into the matrix via the pin 20 is made via two Transistors 116, which are pin 22 by a read / write command R / W at terminal 22 derived write signal are observed.

In Fig.10 is a variant of the third embodiment of the invention shown. In this case, nodes 85 and 86 are directly connected to the column line halves 37 and 38 of Fig. 3 via lines 91 and 92 and via transistors 89 and 90 and not connected across input transistors 87 and 88. So one begins of nodes 85 and 86, move to the "0" side of the column line to discharge as soon as the signal Yn is switched on, as the line 117 in Fig.11 shows. In the circuit of FIG. 10, the ground connection transistor 102 is also not used used; transistor 101 switched on by clock signal 01Y at time 118 is large enough to generate an output signal with a full logic level. The switched capacitors 103 and 104 apply the clock signal at time 118 01Y to nodes 95 and 96 so that there is no corresponding clock signal 02Y Clock signal is required. Another variation on the circuit is to use transistors 83 'and 84' to provide transistors 83 and 84 for the duration of the clock signal 7 so that the circuit points 85 and 86 subpoenaed will. This has the consequence that the nodes 85 and 86 to a level 119 which corresponds to the value (Vdd-Vt), i.e. the value to which the Circuit points 95 and 96 are charged.

Description of the fourth exemplary embodiment (Fig. 12 to 14) Fig. 12 is a detailed block diagram showing the paths of data and clock signals in the 1 shows the memory arrangement of FIG Embodiment can be used. A read process is carried out externally with the help of a certain Signal sequence triggered on the RAS, CAS and R / W lines. This signal sequence activates the clock generator 18 which causes the clock signals # 4 and # 14 to have a state accept, which marks a read process. The clock signals # 4 and # 14 become from sense amplifiers 16 and from differential read clock generator 19 received. The sense amplifiers 16 respond to the clock signals # 4 and # 14 in such a way that they correspond to those in the cells of the Read the information stored in the addressed line and transfer this information to the Lay column lines YO to Y127.

The circuit of the sense amplifier can be designed as in Fig.3 is given as an example. The clock generator 19 triggers depending on the clock signals # 4 and # 14 execute a clock generation process. The clock generator 19 has an output line 65 connected to the column decoder 15. The column decoder 15 samples the output voltage V65 on line 65 and reacts to it in the Way that it has the memory cell information on the selected column line to the signal line 26 switches through. The signal on line 26 is then from the input / output buffer 17 recorded and read externally via line 27.

In the reading process described above, the time relationship is between the stabilization of the sense amplifiers 16 and the switching through of the selected ones Column line on the signal line 16 is critical. When the selected column line is switched through to the signal line 26 before the sense amplifier 16 stabilizes errors occur. This is the case because the line 65 is due to their connection to each column line gating transistor has a large intrinsic capacitance which leads to an asymmetry of the sense amplifier and thus an unsuitable one Stabilization caused.

On the other hand, if the selected column line becomes the information line 26 is only switched through after the sense amplifier 15 has stabilized for a long time have, the access time of the memory arrangement 10 is unnecessarily increased. It is therefore to strive to deliver a signal on the line 65 that the stabilization time the sense amplifier 16 indicates, and this signal immediately to switch through the selected column line to signal line 26 to use. The job of the generator 19 is to deliver such a signal. In Fig.13 is the circuit diagram of a special Embodiment of the differential read clock generator 19 is shown. The generator 19 basically consists of a bistable amplifier 50 and a differential voltage sensor 60. The purpose of the bistable amplifier 50 is to provide a circuit with temporal To create properties that the temporal properties of the sense amplifier 16 are very similar, and the purpose of the differential voltage sensor 60 is to provide an output signal To generate V65 which indicates when the amplifier 50 is reaching a steady state Has.

The amplifier 50 consists primarily of a setting transistor 51, a Reset transistor 52, two load transistors 53 and 54, two precharge transistors 55 and 56 and a discharge transistor 57. The set transistor 51 and the reset transistor 52 are cross-coupled so that a set node 58 and a reset node The circuit points 58 and 59 are created by the selection of the component relationships (Channel length - to channel width) intentionally unbalanced; as an alternative, the Set circuit point 58 can also be designed so that its capacitance is slightly is less than the capacitance of the reset node 59. It is also possible, to use both ways of achieving the asymmetry.

The set node 58 is with the load transistor 53 and the precharge transistor 55 connected. In the same way, the reset circuit point 59 is also connected to the Load transistor 54 and the precharge transistor 56 connected.

This circuit structure is similar to the structure of the sense amplifiers 16 similar; this similarity makes it possible for the two circuits to also be very have similar properties in their temporal behavior.

The differential voltage sensor 60 consists primarily of a differential voltage sensor transistor 61 and a precharge transistor 62. The drain electrode 63 of transistor 61 is. is connected to the set node 58 and its gate electrode 64 is connected to the Reset node 59 connected. The output line 65 is with the source electrode 66 of the transistor 61 and connected to the drain electrode 67 of the precharge transistor 62.

The operation of the clock generator 19 is determined by the clock signals # 4 and ~ 14 controlled. The clock signal # 4 is on the gates of the precharge transistors 55, 56 and 62 applied; its job is to release a preload or to prevent. The clock signal # 14 is applied to the gate electrodes of the transistors 53, 54 and 57 applied; its task is to activate the clock generator 19 and thereby generating the output clock signal V65.

The way the clock signals # 4 and p14 as well as the resulting Voltages within the clock generator 19 are shown in detail in FIG. During an initial time interval 70, the clock signal # 4 has the signal value i, and the clock signal # 14 has the signal value ~ 0 ". The signal value ~ 1" of the clock signal # 14 turns on transistor 56 so that voltage V59 at node 59 rises to a potential one threshold voltage (Vt) below the voltage of clock signal # 4. Similarly, the voltage will be V58 at the node 58 and the voltage V65 on line 65 is also below a threshold voltage the voltage level of the clock signal # 4 is raised.

During a second time interval 71, both have clock signals # 4 and # 14 the signal value nO, the transistors 53, 54, 55, 56, 57, 61 and 62 become therefore blocked; the precharge voltages V58, V59 and V65 remain at the value that they accepted during time interval 70.

During a third time interval 72, the clock signal p14 goes up the signal value ~ 1 ", while the clock signal # 4 maintains the signal value ~ Of '. This will in the sense amplifiers 16, a memory cell read operation triggered because the clock signal # 4 reaches the load transistors of the sense amplifiers 16; at the same time, the clock signal # 4 in the clock generator 19 triggers the clock signal generation the end.

The following processes take place during this clock signal generation: The signal value "1" of the clock signal p4 causes the transistor 57 to be switched on, so that for the set circuit point 58 and the reset circuit point 59 discharge paths be created. The set node 58 discharges through the transistors 57 and 51, while the reset node 59 is simultaneously via the transistors 57 and 52 discharges. However, as previously explained, node 58 has a smaller capacitance than node 59. Therefore, the node discharges 58 faster than node 59. If the voltage at node 58 has dropped to a level which is the value of a threshold voltage above the Ground potential is then the transistor 52 is blocked, so that the discharge process of node 59 ends.

During the time interval 73, the node 59 overcharges load transistor 54 on, and node 58 continues to discharge through the Transistors 57 and 51.

The difference between the voltages at node 58 and 59 thus increases and soon reaches the size of a threshold voltage.

During the time interval 74 the voltage difference is between nodes 58 and 59 greater than a threshold voltage, so that the differential voltage sensing transistor 61 turns on. The pre-charge present on line 65 is therefore over-discharged the transistors 61, 51 and 57, and the voltage V65 almost drops to the ground potential away.

The negative transition in voltage V65 happens within a few Nanoseconds presently when the sense amplifiers 16 switch. This close time correlation is present because (1) the clock signal # 14 simultaneously drives the clock generator 19 and the sense amplifier 16 trips, (2) both circuits from a bistable amplifier make use of a similar circuit structure and therefore with similar time parameters, (3) the bistable amplifier 50 switches when the voltage V59 rises above a threshold voltage Vt is greater than voltage V58, and (4) the differential voltage sensing transistor 61 switches when the bistable amplifier 50 has switched through.

A low voltage value remains on line 65 until the clock signal # 4 assumes the signal value "1" and the clock signal # 14 assumes the signal value Assumes "0". When this occurs, a time interval 75 begins, during which the Precharge voltages of the time interval 70 are restored.

Description of the fifth exemplary embodiment (fix. 15 to Fig. 18) The fifth embodiment is an address buffer or memory circuit such as the row or column addresses Memory 12 or 14 of Fig. 1, seven row address buffers and seven column address buffers would be used.

In Fig.15 is a circuit diagram of an address buffer after the fifth Embodiment of the invention shown.

The main elements of this embodiment are a set transistor 40, a reset transistor 45, a first clocked load transistor 50, a second clocked load transistor 55, an address input transistor 60, an equalization transistor 70, a precharge circuit 80, two bootstrap capacitors 90 and 91, a strobe drain circuit 100 and an output circuit 130.

The set transistor 40 and the reset transistor 45 are to be formed a set node 41 and a reset node 46 cross-coupled. This cross-coupled transistor pair is asymmetrical in that either the transistors 40 and 45 are made different in size, the capacitance of the Reset node 46 is slightly smaller than the capacitance of the set node 41 is made or that both possibilities are used.

The first clocked load transistor 50 charges the set node 41 through a source electrode 51 connected to a clock signal # 12 and one to the set node connected drain electrode 52.

In the same way, the second clocked load transistor 55 charges the Reset node 46 via a source electrode connected to the clock signal ~ 12 56 and a drain electrode 57 connected to the reset node 46 on.

The conductivity of the load transistor 50 is determined by changing the voltage V53 changed at a set control node 53. The node 53 is connected to the gate electrode of transistor 50. The voltage V53 is calculated using a precharge circuit 80, a bootstrap capacitor 90 and the current diverting circuit 100 changed, all of these parts being connected to node 53.

In the same way, the conductivity of the load transistor 55 is through Change the voltage V58 at reset control node 58 changed. The switching point 58 is connected to the gate electrode of transistor 55. The voltage V 58 is with the help of the precharge circuit 80, a bootstrap capacitor 91, the current diverting circuit 100 and an address input transistor 60 are changed.

The voltages V53 and V58 determine the state of the output circuit 130. The output circuit 130 includes an output load transistor 131 whose gate electrode connected to node 53 and an output driver transistor 132, the gate electrode of which is connected to node 58. On the line 135, which connects the drain electrode of transistor 131 with the source electrode of the transistor 132 connects, an output signal Q is generated.

Similarly, the output circuit 130 includes an output load transistor 133, the gate electrode of which is connected to node 58, and a Output driver transistor 134, the gate electrode of which is connected to circuit point 53 connected is. On line 136, which is the drain electrode of transistor 133 with the source electrode of the transistor 134, an output signal tr is formed.

How the above-mentioned components interact is best shown with reference to the timing diagram of Figure 16 in conjunction with the circuit diagram understand from Fig.15. During a first time interval 110, the circuit is is set to a predetermined initial state from which an address signal IAD detected with a low value (typically T2L), converted into MOS voltage levels and then saved. The citation interval 110 is entered by raising it of a clock signal # 2 to a high MOS voltage level (typically around +12 Volts) and by lowering clock signals # 12 and # 22 to near ground Voltage value.

Ias clock signal # 2 is to the source electrode of the load transistors 50 and 55 created. The load transistors 50 and 55 therefore do not deliver any charge the set node 41 and the reset node 46 when the clock signal ~ 12 has a low voltage value.

The clock signal # 22 is on one side of the two bootstrap capacitors 90 and 91 created. When clock signal # 22 is low, will hence the voltage at the set control node 53 and the reset control node 58 based on mass.

The clock signal # 2 is applied to the gate electrode 73 of the equalizing transistor 70 created. The source electrode 71 of the equalization transistor 70 is with the set node 41 and its drain 72 is connected to reset node 46 tied together. A high MOS voltage level of the clock signal p2 therefore switches the transistor 70 so that the voltages at nodes 41 and 46 are equalized.

Due to the operation of the current diverting circuit 100, the value is this balanced tension almost at ground. This is because the set circuit point 41 with the gate electrode 106 of a bleeder transistor 101 connected is; the transistors 101 and 45 are therefore switched on and conduct Current from reset node 46 when the voltage on the set node 41 is greater than a threshold voltage.

Likewise, the reset node 46 is with the gate electrode 107 a diverter transistor 102 connected; the transistors 102 and 40 therefore become switched on and divert current from set node 41 when the voltage at reset node 46 is greater than a threshold voltage.

The clock signals p2 are also applied to the gate electrodes of three transistors 81 is applied in the precharge circuit 80. Depending on a high voltage value of the Clock signal # 2 turns these three transistors on. This process causes the charging of the set control node 53 and the reset control node 58 to a tension that is about one Threshold voltage below is the voltage value of the clock signal # 2. This precharge value makes both load transistors slightly conductive. The charge is not transferred by the bypass transistors 103 and 104 derived because their gate electrodes are connected to the set node 41 and the reset node, respectively 46 are connected; as indicated above, the voltage is across these nodes almost on earth. The circuit therefore stabilizes in a state in which on the circuit points 53 and 58 a precharge potential and at the circuit points 41 and 46 is almost at ground potential. The precharge potential at the circuit points 53 and 58 determine that the output signals Q and 5 have a low voltage value to have.

The voltage V53 turns on the transistor 134, so that the conduction 136 is connected to ground. In the same way, the voltage V58 switches the Transistor 132 on so that line 135 is connected to ground.

During a second time interval 111, clock signal # 2 goes on has a low voltage level close to ground. In response to that the equalization transistor 70 is turned off and the precharge transistors 81 become also blocked. In this way the circuit is prepared to work with the Begin sampling the low level address signal IAD. Actual sampling begins when clock signal # 12 is at a high M05 voltage level transforms. Typically, the actual sampling occurs as soon as the clock signal is received # 2 goes low.

When the clock signal # 10 goes high, it becomes a third time interval 112 started. During the time interval 112, the two are Load transistors 50 and 55 slightly conductive. The actual Conductivity is determined by the precharge voltage at set control node 53 and at Reset control node 57 is determined as previously discussed.

The conductive state of the load transistors 50 and 55 causes the lifting the voltage at set node 41 and reset node 46. The voltage however, at one node, the voltage rises faster than the voltage at the other node. When the address signal IAD has a high TL voltage value, the transistor conducts 60 removes a small portion of the charge from reset node 46 so that the The voltage at the set circuit point 41 rises faster. On the other hand, if the address signal IAD has a low voltage value, then transistor 60 is turned off, so that the voltage at reset node 46 rises faster. This is why the case because node 46 has a smaller capacitance than the node 41 as described above.

During the time interval 112, the voltages at the nodes increase 41 and 46 continue to operate at different speeds; finally achieved the voltage at one of these nodes has a value that is around a threshold voltage is above the voltage at node 105. When this occurs, the time interval ends 112, and the time interval 113 begins.

The time interval 112 typically has a duration of about 10 ns.

In the course of a fifth time interval 114, the signal IAD can be Change state; the tensions on the Circuit points155 and 158 remain slightly changed, however.

This is because the node 53 or the node 58, after it has been discharged once, remains discharged until the precharge potential again is created. Node 53 and 58 therefore depress the pinned input address signal IAD converted into MOS voltage levels.

During a sixth time interval 115, clock signal # 2 goes off goes high and clock signals # 12 and # 22 go low above. This activates the precharge circuit 80 and the equalization transistor O.

The voltages previously recorded at circuit points 53 and 54 therefore disappear and the precharge voltages of time interval 110 reappear on. The circuit is then back to its original state, and they is ready to perform another save.

In Fig.17 is a second variant of the fifth embodiment of the Invention shown. The structure of this variant is the structure of the variant of Fig. 15 very similar; however, there are the following differences: The source electrodes 82 of the precharge transistors 81 are on the clock signal ~ 2 and not on the source the constant voltage Vdd is applied. The gate electrode 107 of the bypass transistor 102 is applied to clock signal # 22 and is not connected to node 46.

The gate electrode 106 of the diverter transistor 101 is connected to the clock signal # 2 applied and not connected to the set node 41. In series with the input transistor 60 is a second address input transistor 65 switched. Further the node 41 has a slightly smaller capacitance than the node 46.

The operation of the circuit of Fig.17 is based on the timing diagram illustrated by Fig.18. During a time interval 120, the precharge circuit is 80 activated by clock signal # 2. This causes the nodes 53 and 58 to open the voltage value of the clock signal # 2 reduced by a threshold voltage; Furthermore, the nodes 41 and 46 are set to the voltage value of the clock signal ~ 2 reduced by two threshold voltages charged. The reason that the switching points 41 and 46 are preloaded and not unloaded to bulk as in the first variant, can be seen in clock signal # 12 passing diverter transistor 106 and clock signal # 22 blocks bleeder transistor 102 so that the discharge paths are opened. the Signals Q and h both have a low voltage level during the time interval due to the precharge voltage at nodes 41 and 46.

During a time interval 121, clock signal # 2 goes on low voltage value, so that the precharge process is terminated.

During a time interval 122, clock signal # 12 goes high Voltage value, so that a scanning process is initiated. The scanning is thereby executed that the nodes 41 and 46 at different speeds discharged, which is in contrast to the charging of the circuit points at different speeds 41 and 46 are in the first variant.

When the input address signal IAD has a high voltage T2L value, then the transistor 60 turns on slightly, so that the node 46 faster than the node 41 discharges. If the input address signal IAD has a low voltage value, then transistor 60 is turned off, so that the node 41 due to its smaller capacity faster than the node 46 discharges. When the voltage between the faster discharging Node and node 105 is less than a threshold voltage, then time interval 122 ends and time interval 123 begins.

During the time interval 123, the switching points 41 are charged and 53up and the nodes 46 and 48 discharge or vice versa. if node 41 is the faster discharging node, then will the transistors 45 and 103 blocked, the nodes 46 and 58 are charged, nodes 41 and 53 are discharged and signal Q goes high Value. If node 46 is the faster discharging node is, then the transistors 40 and 104 are blocked, the nodes 41 and 53 are charged, nodes 46 and 58 are discharged and the signal Q takes on a high value.

Fig.l8 shows the last-mentioned case. Charging is quick, because the high voltage level of the clock signal # 22 increases the conductivity of the transistors 50 and 55 increased; discharging is also quick because of the high voltage value of clock signal # 22 turns on bleeder transistor 102. The time interval 123 ends when the voltage difference between the switching points 41 and 46, 53 and 58 is large enough to cause a change in the state of the input address signal IAD without adversely affecting the storage process.

During the time interval 124, the input address signal IAD change his state; however, the voltages at nodes 53 and 58 are so that the Q and # signals do not change.

During the time interval 125, the precharge process begins, and the Circuit returns to its initial state.

Description of the sixth embodiment (Fig. 19 and 205 In 19 shows a circuit according to the sixth embodiment of the invention. An input terminal 10 is connected to the gate electrode of a transistor 11, whose source-drain path lies between a circuit point 12 and ground (Vss). Terminal 10 can have the # signal input 16 of a semiconductor memory arrangement be a multiplexed address as shown in Figure 1. The switching point 12 is connected to an output 14 via the source-drain path of the transistor 13. With the help of this circuit, the transition of the voltage at the input terminal is intended 10 from the value "1" to the value 0, i.e. from a positive voltage to approximately ground potential can be found in N-channel components. The voltage value at the input terminal 10 can be a TTL level (about 2V) or a full MOS level (about +10 or 12V). When the tension is on terminal 10 goes from + V to ground the voltage at output 14 from ground to a MOS level as quickly as possible increase from about + Vdd or +10 to 12 V.

A bootstrap load circuit is located between the output 14 and a + Vdd line 15; this load circuit contains a transistor 16 whose source-drain path between the line 15 and the output 14 is located; between a node 18 and the Output 14 are a switched capacitor 17 and a transistor 19, whose Gate and drain electrodes are connected. This is a traditional bootstrap load circuit, which ensures that the voltage at output 14 when transitioning to positive values completely up to the voltage + Vdd becomes positive, since due to the effect of the switched Capacitor 17 at the gate electrode of the transistor 16 has a voltage which is greater than Vdd.

The node 12 is to the gate electrode of a transistor 20 connected, the source-drain path between a node 21 and Ground Vss is.

The node 21 is to the gate electrode of the transistor 13 connected so that the transistor 13 is blocked when the transistor 20 is conductive is and is turned on when the transistor 20 is blocked so far that at the switching point 21 is a voltage which is a threshold voltage Vt above the voltage at the node 12 lies. The node 21 is precharged by a transistor 22 that turns on the Vdd line 15 is connected. To the gate electrode of transistor 22 is a clock signal source 23 for the clock signal ~ p is connected.

In the operation of the circuit of FIG. 19, the circuit points 12 are located and 14 before a time 25 at which the # signal 26 at the input 10 according to FIG passes from positive values to ground, almost or completely at ground.

This means that during a time interval 27 the gate electrode of transistor 10 is held high by signal 26, so that the Transistor 11 fully conducts. The transistor 13 is also fully conductive State held by a precharge voltage applied to circuit point 21, which refers to the # p voltage 28 (see Figure 20) at the gate electrode 23 of the transistor 22 is due. The clock signal pp has at the time 25 ground potential, so that the transistor 22 is non-conductive beginning at this point in time or before. if the voltage 26 at the input 10 drops almost to a threshold voltage Vt, then the voltage 26 begins to rise at the node 12, like the line 29 in FIG reveals. At time 30, the voltage at circuit point 12 reaches the value the threshold voltage Vt, and transistor 20 begins to turn on, which is the voltage 31 lowers at circuit point 21 and leads to transistor 13 being blocked will. When the voltage between nodes 21 and 12 is a When the threshold voltage Vt is reached, the transistor 13 is blocked. At this point node 14 begins to charge to voltage Vdd faster, like the line 32 in FIG. 20 indicates that the capacitance assigned to the node 12 no longer needs to be loaded. Without this accelerator circuit, the Charge starting point 14 according to a line 33 so that it has the voltage Vdd substantially would reach later.

The operation of the bootstrap circuit connected to the load transistor 16 is conventional. The node 18 is from the transistor 19 on a voltage of about (Vdd-Vt) so that transistor 16 conducts (when the voltage on Starting point 14 is low) and the switched capacitor 17 is inverted or high capacitance state. When the transistors 11 and 13 block and the The voltage at the output 14 begins to rise to a high value, then the switched off Capacitor 17 a voltage going to positive values at the node 18 applied, which the voltage at this node to a value above the Voltage Vdd drives so that the output 14 via the transistor 16 to the voltage Vdd can charge.

In the sense amplifiers, the address decoders, the address memories and in the input / output control unit of Fig. 1, several clock voltages #, ##, 7, # 1 and # 2 according to FIGS. 4a to 4 are used. These clock voltages are triggered by the §: § signal and timed so that the arrangement is fast must respond to the § signal. The clock generator generates the various clock signals, and for this purpose it receives the WA3 signal from pin 16 via a capacitive one Isolation circuit which is the same as the circuit of FIG. 19 according to the sixth embodiment of the invention.

The clock generator naturally speaks in the conventional manner the trailing or rising edge of the RAS or CAS signal, since the temporal Location is not critical here. That means that this function of a transistor is achieved whose drain-source path between the starting point 14 of Fig.19 and ground and its gate electrode at input 10 connected is, but during the transition from the positive voltage value to ground from the Circuit is disconnected.

The circuit of Fig. 19 can also be used as an edge trigger circuit will. This means that the circuit emits an output signal when the input signal transitioning from a positive voltage to ground while on a transition does not respond from ground to a positive voltage value.

When the input transistor 11 turns on because the input signal becomes positive, the voltage at output 14 does not go to ground unless the switching point has been precharged to turn on the transistor 13.

The clock signal ~ p can be set so that it occurs after the input has become positive, so that an edge trigger circuit is created.

Description of the seventh embodiment (Fig.21 to Fig.23) 1. The Address Sampling Circuit In Fig. 21 there is an address buffer circuit according to the invention shown. The sampling circuit 14 includes a flip-flop with two driver transistors 31 and 32, the drain electrodes of which via two precharge transistors 33 and 34 with the Vdd supply line 35 connected to a DC voltage of typically + 11V are. The sources of transistors 31 and 32 are at a node 36 connected to one another, which is connected to ground (Vss) via two transistors 37 and 38 is that at different times turn on. The transistor 37 is much smaller than the transistor 38 and switches with the clock signal ~ on while transistor 38 turns on with clock signal ~ d, the reasons for this are given above with reference to transistors 51 and 52 of FIG. A Transistor 39 connects the sources of the two precharge transistors together at the same time that transistors 33 and 34 during the time period 40 of FIG. 22a can be switched on by the clock signal X. Two sampling nodes 41 and 42 are in this way during the duration of a clock signal; on one high value preloaded; the voltage of the clock signal r is much higher than that Voltage Vdd so that the drop across transistors 33 and 34 is very low. The nodes 41 and 42 therefore charge for the duration of the clock signal W or the period 40 to the voltage Vdd. Small components 43 and 44 that operate in depletion mode and about a tenth the size of the precharge transistors have, lie in parallel with transistors 33 and 34. To ensure work In the first cycle, the circuit points are charged very slowly via the components 43 and 44 from the voltage Vdd, so that the circuit at the first pulse of the Clock ~ works without a clock signal W preceding it. The switching points 41 and 42 are connected to the gate electrodes of transistors 32 and 31, respectively, so that Due to the cross coupling, a bistable mode of operation (flip-flop operation) results. The node 41 is connected via two input transistors 45 and 46 Ground connected so that the address signal input results.

The transistor 46 is turned on by the clock signal ~, so that the Buffer circuit does not respond until the clock signal ~ becomes positive. The address signal from the input terminal 12 is the gate electrode of the transistor 45 via a Series transistor 46 supplied, which is turned on by the fact that its gate electrode 47 is charged during the clock signal ~, and it is then disabled after an address level is generated, as will be explained. This way becomes a Time window generated during which the circuit can receive an address. Identical capacitor components are connected to the circuit points 41 and 42 51 and 52, which couple charges to these circuit points when the delayed clock signal ~ d occurs.

To compensate for the temporary disturbance from the input signal AO a capacitor 48 connects the input line to node 42; this Capacitor has roughly the same value as the gate-drain capacitance of the transistor 45.

2. Operation of the Address Scanning Circuit During the Time Period 40 of FIG. 22a, the clock signal Bh has a high value, and the clock signals ~ and ~ d have a low value. The transistors 37 and 38 are controlled by the clock signals ~ and ~ d blocked so that the driver transistors 31 and 32 cannot conduct. The transistors 33, 34 and 35 are kept fully conductive by the clock signal r, whose Level is significantly higher than the voltage Vdd, so that the switching points 41 and 42 are charged to the voltage Vdd and on one indicated by a line 54 level balanced. The transistor 46 is blocked so that the sampling circuit does not open can address an address.

The gate electrodes of the switched capacitors 51 and 52 are connected high so that the silicon under these gate electrodes is inverted; the capacitors have great value. At time 55, which represents the start of the sampling period, the clock signal begins in; go low and the clock signal ~ begins to take on a high value. The transistors 33, 34 and 39 are blocked, when the voltage of the clock signal 7 reaches the voltage value Vdd. The transistors 37 begin to switch through when the clock signal ~ exceeds the threshold voltage value Vt achieved; this transistor is small, and it conducts a small current that carries that Palpation triggers. The nodes 41 and 42 begin over the transistors 31 and 32, via the switching point 36 and the transistor 37 to discharge to ground.

The two transistors 31 and 32 are switched on as long as the voltage at nodes 41 and 42 is high; one of the transistors conducts more than the other because it is larger, so that with an address input signal with the value "O" or Vss the flip-flop always switches in one direction. In a Embodiment, the transistor 31 has a ratio of channel width to channel length, which is a quarter smaller than that of transistor 32, so that the latter Transistor conducts more strongly with an input signal with the value "O". In this case, so when entering the signal value "O", the transistor conducts more current, so that the flip-flop finally reaches a steady state in which the transistor 32 conducts, the transistor 31 is blocked, the voltage on Switching point 31 is high and the voltage at node 42 is low. However, if at the entrance 12 a signal with the value 1 is applied, then the two transistors 45 and 45 begin 46 when the clock signal ~ reaches the threshold voltage value Vt, and the node 41 discharges faster than the node 42 due to the path leading to mass via these components.

With an input signal with the value ~ 1 #, the voltages at the circuit points 41 and 42 those indicated in FIG. 22b with the lines 56 and 57 Course.

The voltage at node 41 drops faster than the voltage at node 42, which tends to lower the gate voltage on transistor 32 and reduce its conductivity so that the voltage at node 42 is kept at a higher value. When the clock signal ~ d is above the threshold voltage value Vt increases, the transistor 38 begins to conduct, so that a low-resistance path after Ground arises and the transistor 31 or the transistor 32 conducts more strongly, what A more defined "O" value is generated on the side transitioning to the value "O". The scanning is improved by only the higher resistance transistor 37 in the initial Section of the scanning process. When the clock signal ~ d goes high, over becomes capacitors 51 and 52 coupled a pulse of charge; this leads to the 1 Page at a high value while the transistor 31 or the on the Value "O" passing side only dissipates this added charge to ground, since it is quite conductive at this point.

The actuation of capacitors 51 and 52 and the delayed clock signal ~ d have the effect of lowering the tension on the 1 side to a very wide extent at the Place 59 to prevent recharging. As the dashed line 59 shows, without this feature, this voltage would be applied to this Place too low and it would take time to recharge, so that the capacitors 51 and 52 accelerate the operation of the circuit. The voltage at node 42 stabilizes at a value that is slightly below one is below the voltage Vdd by a threshold voltage Vt, and they slowly recharges to Vdd due to the depletion components 44.

The voltage at node 41 discharges to ground; she achieved this value after about 50 ns.

3. The Address Output Circuit The nodes 41 and 42, on which are the voltages indicated by lines 56 and 57 in Figure 22b via lines 15 to the gate electrodes of two output transistors 61 and 62 connected in the output circuit 16. In parallel with each output transistor there is a transistor 63 or 64 which is switched on and off by the clock signal W. If the clock signal is high, the address outputs are on the output nodes 65 and 66 the ground value Vss. When the clock signal W has a low value, the transistors 63 and 64 are off, and the state the circuit point 65 or 66 is determined by the circuit points 41 and 42, since the gate electrodes of transistors 61 and 62 are connected to nodes 41 and 42 are connected.

The lines 15 are also with the help of transistors 67 and 68 Connection points 69 and 70 on the gate electrodes of the load transistors 71 and 72 tied together. The purpose of this, Arrangement is the tension at either node 69 or 70 to a voltage that is much higher than the voltage Vdd, so that the address output signal will be one is supposed to have a high level. To the drain electrodes of transistors 71 and 72 a clock signal PA is applied, which after the clock signal ~ d has a high value (against Vdd) assumes, as can be seen in Fig. 22c. The nodes 65 and 66 are to the gate electrodes of two transistors 73 and 74 via lines 75 and 76 tied together; these circuit points also form the output lines 17 at which the signals XO and U appear. The output of transistors 73 and 74 is the Node 47, which is also the gate electrode of the input series transistor 46 forms. This node 47 is over during the duration of the clock signal 7 a transistor 77 precharged, the switched capacitor applied to the clock signal ~ 78 releases a charge to node 47 when the clock signal ~ is high Assumes value, which is only done so that transistor 46 is at the beginning of the sampling period is fully switched.

4. Mode of operation of the address output circuit During the duration of the Clock signal yes, the transistors 63 and 64 are switched on, and the address output signals XO and 5 have the value Vss, the nodes 65 and 66 also have the Value Vss and the transistors 73 and 74 are therefore blocked. The switching point 47 is charged to the value (Vdd-Vt) via the transistor 77. After the transition of the clock signal yes to a low value and before the transition of the clock signal ~ A to a high value in the time interval 79 of FIG. 22c, the switching points change 65 and 66 not, since the supply voltage for transistors 71 and 72 is not yet available is, which means that the clock signal ~ A still has the value O. Even if the Voltage on lines 15 high enough to turn on transistors 61 and 62, no current is flowing yet. The voltage at nodes 69 and 70 has at this point in time due to the charging from the circuit points 41 and 42 via lines 15 and transistors 67 and 68 during the clock signal 7 approximately the value (Vdd-Vt). The gate electrodes of the transistors 67 and 68 are connected at the voltage value Vdd so that they act as separators. By the time, at which the clock signal XA goes high, nodes 41 and 42 have the sampling operation ended and almost reached their final separation, like lines 56 and 57 reveal. For the switching point 41 or 42 transitioning to the value O the corresponding circuit point 69 or 70 discharges via the transistor 67 or 68 to the voltage value Vss, as indicated by line 81 in FIG. 22b. For the circuit point that changes to the value "1", for example the circuit point 42, the corresponding circuit point 69 does not discharge via the transistor 67, but is raised to a high value by the capacitance of transistor 71, when the clock signal ~ A goes high, as indicated by line 82 of Figure 22b. the Transistors 71 and 72 are designed to have a fairly high capacitance have, and in the time period before the clock signal ~ A are the gate electrodes of this Transistors are high, and the source and drain electrodes are low, so the Components act as switched capacitors. The transistor remains for the ### side 67 blocked, switching point 69 remains high and the capacity value of transistor 71 also remains high. For the side that changes to the value "O" transistor 68 conducts so that it removes charge from node 70 * and the Capacitance value between the source-drain path and the gate electrode of the transistor 72 lowers; thus little charge is transported to node 70 by the clock signal ~ A. The timing of the clock signals should be carried out so that the value '0 "node passing over (for example, node 70) according to FIG Line 81 is discharged to the threshold voltage value Vt before the clock signal ~ A is switched on, otherwise at output node 66 in signal XA Glitch is generated.

Due to the raising of the 7-node 69 or 70 one has the signals XO or XO appearing at node 65 or 66 are high Value.

When either of these signals is high, one of the transistors becomes 73 or 74 is turned on, and node 47 discharges, causing the transistor 46 locks, so that the sampling circuit 14 no longer opens until the next cycle Addresses on lines 10 responds.

5. System time control As can be seen in Fig. 23a, the chip enable clock signal is ~ a recurring clock signal with a cycle time of around 150 ns. The address signals should be valid during a window 84 indicated in Fig. 23b. fltte address input signals at pins 12 and 13 should be valid when the clock signal ~ a assumes a high value, and they are only intended for a short period of time after this point in time remain valid. The input data on pin 23 should be read shortly after the clock signal ~ be valid, which also applies to the read / write input signal w am Pin 25 applies, as can be seen in FIGS. 23c and 23d. The data output in the case of a reading process, it is only valid during a period of time which can be seen in FIG. 23e.

6. Further embodiments The circuit described could also are used without the depletion-operating components 43 and 44, since designs of memory arrays are often not based on a first cycle operation Make use. The capacitor 78 is not critical; it could be left out. Two main features of the circuit i.e. the timed charging by the Capacitors 51 and 52 and the operation of transistors 71 and 72 on the clock signal ~ A and its influence on nodes 69 and 70 could be independent of one another can be applied, which means that one characteristic of: benefit even without the other is. The features of the invention could be used in sense amplifiers for cell arrays, in Intermediate output buffers and also in input circuits other than address input circuits be applied. For example, data can be entered into fast-working microprocessors Circuits with these capabilities require.

The most diverse control signal or logic inputs into any MOS / LSI chips can make use of the invention.

Summary: In the first embodiment, an integrated Random access memory arrangement in MOS technology is a matrix of rows and columns with one-transistor memory cells with bistable sense amplifier circuits in the Applied to the middle of each column. To the gate electrodes of the load transistors in each bistable sense amplifier circuit are clock voltages after an initial Reading period is applied so that the initial reading occurs without any burdens on the bistable circuit are present. After this initial period, the load transistors turned on by bootstrap capacitors. Then transistors cause the one shunt connection between the gate electrodes of the load components and the column lines, the blocking of the load device on the ~ O "side. The gate electrodes of these shunt transistors are each of the voltages on the column line on the other side of the sense amplifier.

In the second embodiment, transistors operate instead of a controlled gate voltage are applied to a fixed bias voltage and a Shunt connection between the gate electrodes of the load elements and the column lines generate a locking of the load element on the on-side.

In the third embodiment, an integrated random access memory device In MOS technology, a matrix of rows and columns with one-transistor memory cells with sense amplifier circuits in the middle of each column and an intermediate output buffer applied with inputs connected to both sides of the column lines. Of the Intermediate output buffer makes use of principles of the first and second embodiments, and it is a bistable circuit in which load transistors are provided at their gate electrodes Clock voltages are applied after an initial read period, so that the initial Reading of the data on the column lines takes place without load elements.

After this initial read period, the load transistors are switched off Bootstrap capacitors switched on. Subsequently, transistors cause a shunt connection between the gate electrodes of the load devices and Establish the read nodes, locking the load device on the page. The gate electrodes of these shunt transistors are each of the voltages controlled at the read node on the other side of the bistable circuit.

The fourth embodiment is a read clock generator for use in a semiconductor memory device. The reading clock generator makes of the principles the first, second and third embodiments use; it contains a bistable Amplifier and a differential voltage sensor.

The bistable amplifier is only activated during a read cycle, and it simulates the settling process of several sense amplifiers, which are those in the memory array read stored binary information. The differential voltage sensor is on the bistable Amplifier connected and it generates an output signal when the bistable is Has stabilized amplifier.

The fifth embodiment is an address buffer circuit for the Use in semiconductor memories. The address buffer circuit makes of the principles the first, second, third and fourth embodiments use; it contains two cross-coupled transistors with set and reset circuit points, which is precharged to a predetermined level prior to sampling the input address signals will. The set and reset circuit points are connected to two load transistors, which are also precharged before the scanning process. The actual scanning takes place by further charging or by discharging the set and reset circuit points at speeds that express the state of the input address signal. One Current discharge circuit provides the different charging or discharging speed and it selectively conducts the precharge on a load transistor so that the state of the input address signal is retained.

In the sixth embodiment, includes a circuit for isolating one input node from one output node two input transistors, which are in series between ground and the output node.

The gate electrode of a first of these transistors is the input node, and the drain electrode of this transistor is connected to the gate electrode of a control transistor connected whose drain electrode to the gate electrode of the second input transistor connected is; this gate electrode is used before the time the input signal goes from value "1" to value "O", precharged. When the first input transistor is blocked because the input signal is low, the control transistor of the second input transistor blocked so that the output node isolates and can be charged quickly. The seventh embodiment is one with high speed operating address buffer circuit for use in a MOS LSI semiconductor random access memory or similar. For sampling an address input signal during a short The time window is an asymmetrical, dynamic, cross-coupled MOS driver transistor pair used; internal address signals are generated from the state of the scanning circuit. Sample circuit points are precharged and balanced before this time window; the node that should keep the value "1" is made by bootstrap capacitors held high to which a delayed clock signal is applied.

The state of the sampling circuit is delayed at a point in time after Clock signal is sampled, and address signals of high level are generated.

The invention is here in connection with specific exemplary embodiments has been described, but this is in no way a limitation of the invention For those skilled in the art, numerous modifications are readily within the scope of the invention and modifications of the exemplary embodiments described.

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Claims (21)

Claims Semiconductor memory arrangement with eXwrMatrix from line and column wise arranged memory cells and a sense amplifier in the middle each column line, characterized in that the sense amplifier has two crosswise coupled driver transistors and a load transistor for each driver transistor and means for precharging the column lines in front of a selected one Time in an operating cycle that a switching device is provided is the gate electrode of each load transistor with the associated side of the Column line connects that the switching devices have gate electrodes, which are connected to the other column line and that a coupling device is provided to the gate electrodes of the load transistors on one after the voltage is applied to the selected point in time. 2. Arrangement according to claim 1, characterized in that the driver transistors, the load transistors and the switching devices are MOS transistors, the one Source-drain path and a gate electrode that the sense amplifier first and second means for connecting one side of the driver transistors to one Have reference potential, these first and second devices during of the operating cycle are sequentially operated that the first and second devices first and second MOS transistors, which are selectively connected to different Times are actuated that per bit the ratio of width to length of the Channel of the first MOS transistor is very small compared to the corresponding one The ratio of the channels of the driver transistors is that of the first MOS transistor during a given period of time prior to the selected time in the course of a Duty cycle is switched on and that the coupling device switched capacitors contains, which are connected with one side to a clock signal source, whose #output signal a .voltage value change at the selected point in time during each operating cycle shows. 3. Circuit arrangement for a semiconductor memory arrangement with two cross-coupled driver transistors and two load transistors that make up the driver transistors connect to a supply voltage, each driver transistor with its Drain electrodes each connected to one of two opposite circuit points and two switching devices for connecting the control electrodes separately of the load transistors with the switching points, whereby the load transistor for the the node assuming the signal value wO at a given point in time in a cycle of operation becomes non-conductive, characterized by coupling devices to control each switching device by the voltage on the one on the respective switching point lying on the other side of the circuit. 4. Circuit arrangement according to claim 3, characterized in that two separate control transistors the source electrodes of the driver transistors Connect to a reference potential that a control voltage generator is provided is the one of the control transistors at a first point in time in an operating cycle actuated and actuated the other control transistor at a selected point in time, which is later than the first point in time in each operating cycle that the one control transistor significantly less current than the other control transistor conducts that the driver transistors, the load transistors and the switching devices are MOS transistors that the Device for connecting the control electrodes of the load transistors to the switching points consist of 2 MOS transit gates, the gate electrodes of which point to the connection point the other side of the circuit arrangement are connected that capacitor devices independently of one another the control electrodes of the load transistors with a clock voltage source connect a clock voltage approximately at the second point in time in each operating cycle generated, and that precharge devices are provided, which points the circuit precharge at a point in time that is in this operating cycle before the first point in time lies. 5. Circuit arrangement according to claim 3, characterized in that it is an intermediate output stage that the load transistors precharge / load transistors for each driver transistor are that the nodes are two Sense nodes are attached to the halves of the column lines of the memory array are connected that the precharge / load transistors containing devices for Precharging the sampling nodes prior to a selected time in an operating cycle it is provided that the switching devices control the gate transistors of each precharge / load transistor separately to a reference potential, each switching device with its Gate electrode connected to the opposite sense node, and that a coupling device to the gate electrodes of the precharge / load transistors applies a voltage at a point in time that is after the selected point in time. 6. Circuit arrangement according to claim 5, characterized in that the driver transistors, the precharge / load transistors and the switching devices MOS transistors are that have a channel as a source-drain path and a gate electrode comprise the intermediate output stage having first and second devices for applying the driver transistors and the switching devices at a reference potential, the first and second devices sequentially during the cycle of operation operated so that the first and second devices make first and second MOS transistors which are activated in selected ways at different times, namely, one at the selected time and the other at the one after the selected Point in time that the ratio of width to length of the canal of the first: MOS transistor very one compared to the corresponding ratio of the channels of the driver transistors is that the second MOS transistor has a ratio from channel width to channel length, that is larger than that of the first MOS transistor and that the coupling devices are switched capacitors included, which are connected with one side to a clock signal source, the during each operating cycle at the point in time after the selected point in time shows a change in voltage value. 7. Semiconductor memory arrangement according to Claim 1, characterized in that that a clock device is connected to the sense amplifier, which the clock signals for triggering the reading process of binary information stored in the memory arrangement generated, and that a differential read clock generator is connected to the clock device which is responsive to the clock signals to produce an output signal when the sense amplifier stabilizes while reading the binary information to have. 8. Semiconductor memory arrangement according to Claim 7, characterized in that that the differential read clock generator consists essentially of MOS transistors and from a bistable amplifier device and a differential voltage sensor is formed according to claim 3 that the bistable amplifier device one of the The circuit structure of the sense amplifier has the same circuit structure, and of one There is a set transistor and a reset transistor cross-coupled to it, the cross-coupling forming set and reset nodes that the Differential voltage sensors connected to the set and reset circuit points and generates an output signal in response to the voltage at the Set circuit point by more than a threshold voltage different on the voltage at the reset node and that the differential voltage sensor includes a transistor whose gate is connected to the reset node and the drain of which is connected to the set node. 9. Memory arrangement according to claim 1, characterized by a read clock generator for generating clock signals that indicate when a number of sense amplifiers are present has stabilized in the semiconductor memory during a read cycle, the read clock generator contains the following components: a) a bistable amplifier device, which during of the read cycle simulates the settling process of the read amplifier and b) a Differential voltage sensor, which is sent to the bistable amplifier device for generating of the clock signal depending on the reaching of the stable state of the bistable Amplifier device is connected. 10. Memory arrangement with a reading clock generator according to claim 9, characterized in that the bistable amplifier device has a circuit structure which is similar to the circuit structure of the sense amplifier that the bistable amplifier device and the differential voltage sensor consists essentially of MOS transistors, that the bistable amplifier device has a setting transistor and one with it crosswise coupled reset transistor for the formation of set and reset switching points contains, which are asymmetrical in terms of their capacity, that the differential voltage sensor includes a transistor whose gate is connected to the reset node and its drain connected to the set node is that the bistable amplifier device includes a setting transistor which crosswise with a reset transistor to form set and reset circuit points is connected, with the set and reset nodes having two unbalanced Load transistors are connected, and that the differential voltage sensor is a transistor contains its gate electrode with the reset node and its drain electrode is connected to the set circuit point. 11. Circuit arrangement according to claim 3, characterized in that the circuit is used as a row and column address buffer for the semiconductor memory that the buffers contain several flip-flops, each of which crosses the two contain coupled driver transistors with set and reset nodes, wherein the set node having a first load transistor for charging the set node at a rate proportional to the potential at a set control node while the reset node is connected to a second load transistor for charging the reset node with one of the potential at a reset control node proportional speed is connected that a compensation device for Equalization of the voltages at the set and reset circuit points is provided is that a precharge device is connected to the set control node and to the reset control node a precharge applies that a Vtrrichtung a voltage difference between the Set node and the reset node depending on an address input signal generated and that a current deriving device for determining a voltage difference between the Set node and the reset node and for deriving the precharge in dependence on one of the control circuit points of which is provided. 12. Circuit arrangement for a memory arrangement according to claim 11, characterized in that all transistors are MOS transistors, # that the current diverter contains first and second MOS diverting transistors that the gate electrode of the first Bypass transistor is connected to the reset node that the source electrode this first bleeder transistor is connected to the set control node, that the gate electrode of the second diverter transistor with the set node that the source electrode of the second diverter transistor is connected to the reset control node is connected that the current diverter third and fourth MOS diverter transistors includes that the gate electrode of the third diverter transistor with the reset node that the source electrode of the third diverting transistor is connected to the drain electrodes of the first diverter transistor and is connected to the set transistor that the gate electrode of the fourth diverter transistor is connected to the set node that the Source electrode of the fourth diverting transistor with the drain electrodes of the second Diverting transistor and the reset transistor is connected that the current diverting device third and fourth MOS diverting transistors contains that the third diverting transistor a clocked gate electrode and one with the drain electrodes of the first shunt transistor and the source electrode connected to the set transistor, that the fourth diverter transistor a clocked gate electrode and one with the drain electrodes of the second diverting transistor and the reset transistor has the connected source electrode that the compensation device is a transistor its source electrode with the set circuit point and the drain of which is connected to the reset node and the having a clocked gate electrode that the precharge device first, second and third precharge transistors comprising the drain of the first precharge transistor connected to the second set control node is that the drain electrode of the second precharge transistor is connected to the reset control node, that the source electrode of the third precharge transistor with the set control node that the drain electrode of the third precharge transistor is connected to the reset control node is connected, each precharge transistor having a clocked gate electrode, and that the address input device has a first input transistor, whose source is connected to the reset node and whose Gate electrode can receive a digital input signal. 13. A circuit according to claim 3 for forming a buffer circuit for Storage of digital signals, characterized in that a) the driver transistors Set and reset transistors are used to form set and reset nodes are cross-coupled, b) that a first load transistor device with one output connected to the set node for charging the set node and a set control node for changing its conductivity of the has charge applied to it, c) that a second load transistor device an output connected to the reset node for charging it, and a reset control node for changing its conductivity of the charge applied to him, d) that a balancing device for Balancing of the voltage at the set and reset circuit points is provided, e) that a precharge device is provided which is connected to the set control node and applying a precharge voltage to the reset control node to make each of the load transistors becomes slightly conductive, f) that to the reset node an address input device is connected, the charge from the reset node derives an address input signal as a function of a first state, and g) that to the set and reset nodes and to the set control and reset control nodes a current discharge device is connected, which depends in a selected manner from a voltage difference between the set and reset circuit points charge from the set control node or from the reset control node. 14. Memory arrangement with a matrix of rows and columns arranged memory cells and a sense amplifier in the middle of each column line, whereby. the sense amplifier has two cross-coupled driver transistors and a load transistor for each driver transistor, characterized by a switching device that connects the gate electrode of each load transistor with its side the column line connects, the switching devices having gate electrodes, to which a selected voltage is applied that is lower than the supply voltage is a coupling device for applying a voltage to the gate electrodes of the load transistors that are used to turn on the load transistors on a selected one Time is sufficient, and a device for precharging the column lines the selected time. 15. Circuit arrangement with an input terminal, an output terminal and first and second field effect transistors each having a source-drain path and a gate electrode characterized by a device comprising the gate electrode of the first transistor connects to the input terminal, a device which the Source-drain paths of the first and second transistors in series between the Output terminal and a reference potential via a first connection point between the first and second transistors puts a third field effect transistor with a source-drain path that connects the gate electrode of the second transistor to the Sets reference potential, and with a gate electrode, which is connected to the first circuit; point connected, a device for precharging the gate electrode of the second transistor and one the output terminal with a supply voltage device connecting load device. 16. Circuit arrangement according to claim 15, characterized in that that a voltage at the input terminal is a change from a first signal value approximately points to the reference potential at a selected point in time, the precharge process before this point in time occurs that the second transistor from the third transistor is blocked at a first time after the selected time that the Load device pushes the output terminal at a first speed before the first Time and at a faster rate after the first time, and that the load device is a bootstrap circuit. 17. Capacitance separation circuit, characterized by an input switching point, an output node, an intermediate node, a control node, first, second and third control devices each having a current path and a control electrode, a connecting device for connecting the input node with the control electrode of the first control device, a connecting device to connect the current path of the first connecting device between the Intermediate connection point and a reference potential, a connection device for Connecting the current path of the second control device between the output node and the intermediate point , a connecting device for connecting the current path of the third control device between the control switching point and the reference potential, the control circuit point being connected to the control electrode connected to the second control device, a precharge device for precharging of the control node prior to a given point in time, an impedance device for tying the output node to a supply voltage and a Device for applying a digital voltage value to the input node at the given time. 18. A circuit according to .Anspruch 17, characterized in that the control devices MOS field effect transistors are that the field effect transistors are N-channel field effect transistors are that the supply voltage is positive, that the digital voltage value is on changes from a positive value to a reference potential at the given point in time, that the precharge device contains a field effect transistor, which is the control node connects to the supply voltage, and that dielmpedanzvorrichtung a field effect transistor i # st, whose gate electrode is switched from the output node via a Capacitor is raised in terms of potential. 19. Input buffer circuit for an input address of a semiconductor memory arrangement, characterized by two driver transistors, which in terms of their size and their properties are considerably asymmetrical, one control electrode each and having two output electrodes and by connecting the control electrode to an output electrode of the respective other transistor cross-coupled are, a precharge transistor for each driver transistor, the precharge transistors are considerably asymmetrical in terms of their size and properties and each in series with one of the driver transistors and a supply voltage lie, a device for turning on the two precharge transistors and for blocking the precharge transistors at a selected point in time in an operating cycle, a device for producing a short-circuit connection between output electrodes of the two cross-coupled driver transistors to equalize the voltages at these output electrodes before the selected point in time in an operating cycle, one to an output electrode of one of the two cross-coupled driver transistors connected device for applying one output electrode to a reference potential, if the address input signal is available starting at the preselected time is a device for applying a charge to each of the output electrodes a short delay time later than the preselected time for delay reduction the discharge of one of the output electrodes and two address signal output circuits, each having an input that is connected to an output electrode of one in each case other of the two cross-coupled driver transistors is connected and to their voltage level at a point in time after the short delay time during of a cycle of operation, wherein one of the two address signal output circuits one address signal generates while the other generates the complement of the address signal generated. 20. Input buffer circuit according to claim 19, characterized in that that the output electrodes of each of the two cross-coupled driver transistors Source and drain electrodes are used, while the control electrode is a gate electrode is that the drain electrode of each of these transistors connects directly to the gate electrode of the other transistor is connected that each of the two precharge transistors a source electrode, a drain electrode and a gate electrode, wherein the source of each of these transistors directly to the drain of one the other of the two cross-coupled driver transistors is connected, that the device for producing a short-circuit connection between the output electrodes is an equalizing transistor which is one of the drain electrodes of the driver transistors connecting source-drain path has that to the gate electrodes of the precharge transistors a clock signal source is connected with a voltage value higher than the Supply voltage is, with the voltage value at the preselected time that the device for applying a charge goes to zero in each cycle of operation two MOS capacitors on the output electrodes of the cross-coupled driver transistors contains, each separated between the drain electrode of one of the two crosswise coupled driver transistors and a source are inserted, the consecutive Emits pulses a short time delay after the preselected time begin and end before the preselected time during each operating cycle, that the device for applying the one output electrode is one of the two crosswise coupled driver transistors to a reference potential of two input transistors contains whose source-drain paths in series between the drain electrode of a of the two cross-coupled driver transistors and a reference potential are connected that the gate electrode of one of the two input transistors to one Address input terminal is connected, while the gate electrode of the other of the two input transistors connected to a source, the consecutive Emits pulses during each operating cycle at approximately the preselected time begin that one of the two input transistors has a capacitance with a given Size that the address input terminal to the drain electrode of the other of the two cross-coupled driver transistors via a capacitive device which is essentially the same capacity size as the one of the two Has input transistors that the two address signal output circuits respectively first, second and third MOS transistors each containing a source electrode, a drain electrode and a gate electrode, wherein the source-drain paths of the first and second transistors in series between a supply device and a reference potential are applied, while the source-drain path of the third Transistor connected in parallel to the source-drain path of the second transistor is that the input of each of the address signal output circuits is a connection from the drain electrode of another of the two sparse-coupled driver transistors to the gate electrode of the first transistor in one of the output circuits and to the gate electrode of the second transistor in the other of the output circuits comprises that the gate electrodes of the third transistors in each output circuit are connected to a source that emits successive pulses of about at the preselected time during each cycle of operation that the supply device one Source is that emits successive pulses according to the point in time the short delay time in each cycle of operation that the address signal and the complement of the address signal at the node between the first and the second MOS transistor in the two address signal output circuits that a device is provided which has an input which Address signal and the complement of the address signal and receives an output which is connected to a gate electrode of a series transistor, its source-drain path in series between the address input terminal and the an input transistor, this device being responsive to an address input signal terminates a feedback device after an address signal or its complement occurs depending on the occurrence of the address signal and the complement of the address signal an input signal for a device at the address signal output circuits which is connected to receive an address input from the address terminal to the one input transistor that switches on the device for switching on and disabling the two load transistors in response to the operation of the address signal output circuits works that a device for blocking the load transistors according to a preselected Time period depending on the occurrence of an address signal at the address signal output circuits works that the source-drain paths of the driver transistors leading from the sense nodes are removed, connected to a reference potential via two ground connection transistors one of which will turn on at the first selected time during the other turns on at the second selected time and that the one ground terminal transistor essential is smaller than the other ground terminal transistor. 21. Input memory circuit for a semiconductor integrated circuit with field effect transistors with insulated gate electrode, characterized by two Driver transistors with asymmetrical properties, each with a source-drain path and a gate electrode, two precharge transistors, each with a cource-drain path and a gate electrode, a device covering the source-drain path of each of the Driver transistors in series with the source-drain path of a respective other precharge transistor switches in series and each series circuit consists of a driver transistor and a Precharge transistor connects between a supply voltage device, two Sampling nodes, one between each of which is connected in series Source-drain paths of the driver and load transistors is a connection device to cross-connect each sense node to the gate electrode of the each other driver transistor, one to the gate electrodes of the precharge transistors connected device for turning on the precharge transistors before a first selected time in an operating cycle and to turn off the precharge transistors at the first selected point in time, one connected to the two sampling nodes Device for balancing the tensions applied to them before the selected one Point in time in an operating cycle, one connected to one of the sampling nodes Input device for applying a reference potential to the circuit point, if an input signal is present at the time corresponding to the first selected point in time starts in a cycle of operation, one separate to each Sampling node connected charging device for applying a charge to the circuit points at a second point in time after the first selected point in time in each Duty cycle is, and a signal output circuit device having one at least has input device connected to one of the output nodes, and depending on the voltage applied to it, starting with a third selected one Time works after the second selected time in an operating cycle wherein the signal output circuit device is on during a period of time Signal generated after the third selected time in a Betd ebs cycle begins.